JP2013254826A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device, which uses silicon carbide having crystal defects, that allows efficiently improving the yield of the semiconductor device, and to provide a method of manufacturing the same.SOLUTION: A semiconductor device includes: an n-type silicon carbide substrate 11; a drift layer 12 formed on the silicon carbide substrate 11 and composed of first-conductivity-type silicon carbide; a bit 32 of a hollow shape formed on a surface of the drift layer 12 corresponding to a crystal defect of the drift layer 12; and a gate oxide film 21 as a field relaxation layer formed in association with the bit 32.

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and more particularly to a power semiconductor device mainly composed of silicon carbide.

  In order to save energy of power electronics devices such as inverters, semiconductors such as insulated gate bipolar transistors (IGBT) and metal-oxide-semiconductor field effect transistors (MOSFETs) are used. The loss of the switching element needs to be reduced.

  Since the loss is caused by the ON resistance of the element, development of an element using a wide band gap semiconductor material such as silicon carbide (SiC) or gallium nitride (GaN) is underway in order to reduce the ON resistance. Since such a wide band gap semiconductor material has a high dielectric breakdown electric field, it can be designed such that the internal electric field of the semiconductor is high, and a high-breakdown-voltage semiconductor element can be realized even in a unipolar device such as a MOSFET. it can.

  On the other hand, when a high voltage is applied to the drain side, the gate oxide film of the MOSFET is exposed to a high electric field stress, and there is a concern about the destruction of the element. If crystal defects such as threading dislocations exist in that portion, there is a concern that the reliability of the device further decreases.

  On the other hand, for example, Patent Document 1 discloses a method in which a semiconductor device using silicon carbide is selectively ion-implanted into a portion where a crystal defect exists to thereby inactivate and improve the yield.

  The method of manufacturing a semiconductor device in Patent Document 1 includes a step of forming an n-type drift layer on a silicon carbide substrate, a step of specifying a defect position that becomes a leakage current source of the drift layer, and implanting impurity ions at the defect position And a step of forming a p-type impurity layer and a step of forming an electrode pad on the drift layer. By using such a manufacturing method, the yield of the semiconductor device can be improved.

JP 2011-60939 A

  A method of manufacturing a semiconductor device (silicon carbide Schottky barrier diode) in Patent Document 1 will be described.

  First, an n-type silicon carbide substrate is prepared. Next, an n-type epitaxial layer is formed on the n-type silicon carbide substrate by epitaxial growth.

  Next, using a conductive atomic force microscope, a defect position that becomes a leak current source of the n-type epitaxial layer is specified. For example, the surface of the n-type epitaxial layer is monitored by operating a probe of a conductive atomic force microscope to monitor the capacitance with the n-type epitaxial growth layer, and an abnormal portion is specified as a defect position that becomes a leakage current source after the element is formed. . Thereby, defect mapping data is formed.

  Next, a silicon oxide film is deposited by a CVD (Chemical Vapor Deposition) method, and a resist is patterned thereon using a known photolithography technique. This pattern is a pattern of the p-type impurity layer in the termination region of the Schottky barrier diode.

  Next, the resist is removed, and a resist pattern is formed based on the defect mapping data. This pattern is a pattern for forming a p-type impurity layer at a defect position serving as a leakage current source of the Schottky barrier diode and inactivating this portion.

  Next, the silicon oxide film is etched by, for example, the RIE method using the photoresist as a mask.

  Next, for example, aluminum is ion-implanted using the silicon oxide film as a mask, thereby forming a p-type impurity layer in a termination region of the Schottky barrier diode and a p-type impurity layer for inactivating a defect position.

  Finally, a Schottky electrode and an electrode pad are formed on the n-type epitaxial layer, and an ohmic electrode is formed on the back surface, whereby the silicon carbide Schottky barrier diode described in Patent Document 1 is completed.

  However, in such a method of manufacturing a semiconductor device, it is necessary to use a conductive atomic force microscope on the entire surface of the wafer when forming defect mapping data, which requires a very long time. Therefore, there is a problem that there is a concern about a decrease in throughput.

  As the wafer diameter of the silicon carbide substrate increases, the throughput further decreases and the capacity of mapping data also increases.

  The present invention has been made to solve the above-described problems, and is a semiconductor device using silicon carbide having crystal defects, which can efficiently improve the yield of the semiconductor device. And it aims at provision of the manufacturing method.

  A semiconductor device according to one embodiment of the present invention includes a first conductivity type silicon carbide semiconductor substrate, a first conductivity type silicon carbide drift layer formed over the silicon carbide semiconductor substrate, and crystal defects in the drift layer. Correspondingly, the present invention is characterized by comprising a hollow shape formed on the surface of the drift layer and an electric field relaxation layer formed accompanying the hollow shape.

  A method of manufacturing a semiconductor device according to an aspect of the present invention includes: (a) a step of forming a drift layer of first conductivity type silicon carbide on a first conductivity type silicon carbide semiconductor substrate; and (b) the drift layer. And a step of forming a recess shape corresponding to the crystal defect on the surface of the drift layer, and (c) forming an electric field relaxation layer associated with the recess shape.

  According to the above aspect of the present invention, the first conductivity type silicon carbide semiconductor substrate, the first conductivity type silicon carbide drift layer formed on the silicon carbide semiconductor substrate, and the crystal defects of the drift layer are dealt with. Then, a semiconductor device using silicon carbide having crystal defects by including a recess shape formed on the surface of the drift layer and an electric field relaxation layer formed accompanying the recess shape, The yield of semiconductor devices can be improved efficiently.

It is sectional drawing which shows the semiconductor device regarding 1st Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device regarding 1st Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device regarding 1st Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device regarding 1st Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device regarding 1st Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device regarding 1st Embodiment of this invention. It is sectional drawing which shows the semiconductor device regarding the modification of 1st Embodiment of this invention. It is sectional drawing which shows the semiconductor device regarding the modification of 1st Embodiment of this invention. It is sectional drawing which shows the semiconductor device regarding 2nd Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device regarding 2nd Embodiment of this invention. It is sectional drawing which shows the semiconductor device regarding the modification of 2nd Embodiment of this invention. It is sectional drawing which shows the semiconductor device regarding the modification of 2nd Embodiment of this invention. It is sectional drawing which shows the semiconductor device regarding 3rd Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device regarding 3rd Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device regarding 3rd Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device regarding 3rd Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device regarding 3rd Embodiment of this invention. It is sectional drawing which shows the semiconductor device regarding the modification of 3rd Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device regarding 4th Embodiment of this invention.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

<First Embodiment>
<Configuration>
FIG. 1 is a cross-sectional view of a semiconductor device, specifically, an n-channel SiC-MOSFET in the first embodiment of the present invention. In the semiconductor device according to the present invention, since the portion where the crystal defect exists is important, the portion where the crystal defect exists in the SiC-MOSFET is extracted and shown. The type of crystal defects in FIG. 1 is threading dislocations, but other types of crystal defects may be used. In addition, the crystal plane of the silicon carbide substrate on which crystal defects are formed is assumed to be the (0001) plane, but other plane orientations are also applicable.

  As shown in FIG. 1, semiconductor device 101 has an n-type drift layer 12 formed on an n-type silicon carbide substrate 11. P-type well regions 13 are formed at a plurality of locations on the surface of the drift layer 12.

  An n-type source region 14 is formed inside the well region 13, and a p-type well contact region 15 is formed in a part thereof. The well contact region 15 can suppress the operation of the parasitic transistor by making the potentials of the source region 14 and the well region 13 the same. Further, an n-type channel doped region 16 is formed over the well region 13 and the drift layer 12.

  Here, threading dislocations 31 due to crystal defects of drift layer 12 exist from the surface of silicon carbide substrate 11 toward the surface of drift layer 12. The surface of the drift layer 12 around the portion where the threading dislocation 31 is present has a pit shape (dent shape) (pit 32 in FIG. 1). The channel dope region 16 is formed so as to avoid threading dislocations 31.

  A gate electrode 22 is formed from a part on the source region 14 to the channel dope region 16 and further to the drift layer 12 via an insulating gate oxide film 21. The gate oxide film 21 as the electric field relaxation layer is also filled in the pits 32. An interlayer insulating film 23 for separating the gate and the source is formed on the gate electrode 22, and a source electrode 24 in contact with the source region 14 and the well contact region 15 is formed thereon. On the other hand, a drain electrode 25 is formed under the silicon carbide substrate 11.

<Operation>
Next, the operation of the semiconductor device 101 will be described.

  In the semiconductor device 101, when a positive voltage is applied to the gate electrode 22, a current path is formed in the channel dope region 16 on the well region 13. When a positive voltage is applied to the drain electrode 25 in this state, a current flows from the drain electrode 25 to the source electrode 24 through the silicon carbide substrate 11, the drift layer 12, the channel dope region 16, and the source region 14.

  The channel dope region 16 has an effect of reducing the channel resistance of the semiconductor device 101. The impurity concentration of the first conductivity type (n-type) in the channel dope region 16 is set higher than that of the drift layer 12. In particular, in an element using a wide band gap semiconductor material such as silicon carbide, the drift layer 12 can increase the concentration of carriers and can be thinned, and has low resistance. It is very effective to reduce the loss.

  On the other hand, when the positive voltage of the gate electrode 22 is removed or a negative voltage is applied, the channel dope region 16 on the well region 13 is depleted. Thereby, even if a high voltage is applied to the drain electrode 25, the current between the drain and the source can be cut off.

  At this time, the gate oxide film 21 is exposed to a high electric field. In particular, the gate oxide film 21 on the threading dislocation 31 may reduce the reliability of the device due to the electric field concentration due to the surface shape and the influence of the property of the gate oxide film 21 on the threading dislocation 31.

  According to the semiconductor device of the present invention, since the channel dope region 16 is not formed in the portion where the threading dislocation 31 exists, the electric field concentration in the portion where the element destruction is most feared is alleviated, and the reliability of the element is improved. Can be realized.

  In particular, in the case of an element using silicon carbide as a semiconductor material, since the breakdown electric field of silicon carbide is large, it is often designed to apply a high electric field to silicon carbide, and the electric field strength applied to the gate oxide film 21 is accordingly increased. growing. Therefore, it is very effective to use the structure of the present invention for reducing the electric field concentration in the semiconductor device.

  As described above, the semiconductor device according to the present invention can achieve both low loss and high reliability.

<Manufacturing method>
Next, a method for manufacturing a semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS.

  First, as shown in FIG. 2, an n-type and low-resistance silicon carbide substrate 11 is prepared, and an n-type drift layer 12 is formed on the silicon carbide substrate 11 by epitaxial growth. As shown in FIG. 2, the drift layer 12 includes crystal defects such as threading dislocations 31 in at least one place.

In the present embodiment, the drift layer 12 has an n-type impurity concentration of 1 × 10 ¹³ cm ⁻³ to 1 × 10 ¹⁸ cm ⁻³ and a thickness of 4 μm to 200 μm.

  Next, as shown in FIG. 3, a silicon oxide film 41 is formed on the drift layer 12 by a thermal oxidation method. The silicon oxide film 41 is formed by heat treatment at 1000 to 1200 ° C. for about several tens of minutes to 2 hours, for example, in an atmosphere containing water vapor.

  When thermal oxidation is performed at such a relatively low temperature and in a wet atmosphere, the oxidation rate depends on the plane orientation, so that the surface of the drift layer 12 where the threading dislocations 31 are present increases as shown in FIG. The accelerated oxidation film 42 is formed by rapid oxidation.

  The film thickness of the silicon oxide film 41 is, for example, about 10 to 70 nm, and the film thickness of the accelerated oxide film 42 is about 2 to 4 times the film thickness of the silicon oxide film 41 and is 20 to 300 nm. A portion where the accelerating oxide film 42 is formed has a hollow shape.

Next, as shown in FIG. 4, for example, N ions are implanted from above the silicon oxide film 41 and the accelerated oxide film 42 to form the n-type channel doped region 16. The impurity concentration of the channel dope region 16 is larger than the impurity concentration of the drift layer 12 and is, for example, about 2 × 10 ¹³ cm ^{−3 to} 5 × 10 ¹⁸ cm ⁻³ . The implantation depth of the channel dope region 16 is set so as not to be formed in the portion where the threading dislocation 31 exists, that is, a depth shallower than the depth of the hollow shape. By implanting N ions at a relatively low energy of several keV to several hundred keV, formation of such a channel dope region 16 can be realized.

  Next, after removing the silicon oxide film 41 and the accelerating oxide film 42, as shown in FIG. 5, the p-type well region 13 and the n-type well region 13 surface separated from each other on the drift layer 12 surface. A p-type well contact region 15 on the surface of the source region 14 and the well region 13 is formed. Each region is formed, for example, by implanting Al ions in the p-type region and N ions in the n-type region using a resist or oxide film processed by photolithography as a mask.

The well region 13 is formed, for example, so that the impurity concentration is about 1 × 10 ¹⁵ cm ⁻³ to 1 × 10 ¹⁸ cm ⁻³ and the implantation depth is 0.3 μm to 2.0 μm. The source region 14 is formed so that the bottom surface thereof is not deeper than the bottom surface of the well region 13, the impurity concentration is higher than the impurity concentration of the well region 13, and 1 × 10 ¹⁷ cm ⁻³ to 1 × 10 ²¹ cm ^{−. It} is formed to be about ³ . The well contact region 15 is formed so that its impurity concentration is higher than that of the well region 13. The well contact region 15 is preferably formed at a substrate temperature of 150 ° C. or higher.

  At this time, the portion where the accelerating oxide film 42 has been formed has a pit shape (dent shape) (pit 32 in FIG. 5).

  Next, annealing is performed in an inert gas atmosphere such as Ar gas by a heat treatment apparatus. The annealing is performed at a temperature of 1300 ° C. to 1900 ° C. for about 30 seconds to 1 hour, for example. By this annealing, ion-implanted n-type impurities such as N and p-type impurities such as Al are activated.

  Next, as shown in FIG. 6, a gate oxide film 21 and a gate electrode 22 are formed as an electric field relaxation layer. The gate oxide film 21 is formed by, for example, a dry thermal oxidation method at 1150 ° C. or higher. When thermal oxidation is performed at a relatively high temperature and in a dry atmosphere as described above, the dependency of the oxidation rate on the plane orientation is hardly observed, so that the threading dislocation 31 portion is oxidized at a higher speed and the pits 32 are further enlarged. Can be suppressed.

  The gate oxide film 21 may be formed by a deposition method. Heat treatment in a nitrogen or ammonia atmosphere may be performed after the gate oxide film 21 is formed.

  The gate electrode 22 is formed, for example, by depositing polysilicon by a CVD method and performing etching using a resist processed by photolithography as a mask. Polysilicon may contain impurities such as phosphorus and boron. By including impurities, a low sheet resistance can be realized.

  Finally, by forming the interlayer insulating film 23 and then forming the source electrode 24 and the drain electrode 25, the SiC-MOSFET as shown in FIG. 1 is completed.

  The interlayer insulating film 23 is deposited by, for example, the CVD method, and is etched so as to expose at least a part of the source region 14, the well contact region 15, and the gate electrode 22 in order to separate and take out the gate and the source. Although not shown, the gate electrode 22 is exposed at the outer periphery of the MOSFET so that the source electrode 24 and the gate electrode 22 can be simultaneously formed in a separated form. Thereafter, in order to make ohmic contact between the source region 14, the well contact region 15 and the source electrode 24 exposed by etching, for example, Ni is formed on the entire surface of the substrate and heat treatment is performed at 600 to 1000 ° C. to form silicide. (Not shown).

  Ni remaining in the interlayer insulating film 23 is removed by wet etching. Similarly, silicide is also formed on the back surface. Thereby, good ohmic contact between silicon carbide substrate 11 and drain electrode 25 can be realized.

  The wiring for taking out the gate electrode 22 and the source electrode 24 are made of Al, Cu, Ti, Ni, Mo, W, Ta, nitrides thereof, a laminated film thereof, or a metal composed of an alloy layer thereof by sputtering or vapor deposition. It is formed by depositing and patterning. The drain electrode 25 is formed of a metal film such as Ti, Ni, Ag, or Au by a sputtering method or a vapor deposition method.

<Modification 1>
FIG. 7 is a view showing a modification (semiconductor device 102) of the semiconductor device according to the first embodiment. 7 is different from FIG. 1 in that the channel dope region 17 is formed in a region embedded from the surface of the drift layer 12. Since other configurations are the same as those in FIG. 1, the same reference numerals are given, and detailed descriptions thereof are omitted.

  As described above, the channel dope region 17 is formed so as to be embedded in the surface of the drift layer 12, so that not only the gate oxide film 21 portion on the threading dislocation 31 but also the electric field concentration in the gate corner portion 33 near the pit 32. Therefore, the reliability can be further improved.

<Modification 2>
FIG. 8 is a view showing another modified example (semiconductor device 103) of the semiconductor device according to the first embodiment. In FIG. 8, the channel dope region is divided into a low concentration region 18 in which the concentration of n-type impurities is relatively low and a high concentration region 19 in which the concentration of n-type impurities is higher than that of the low concentration region 18. The surface of the drift layer 12 is a low concentration region 18 having a low concentration, and a high concentration region 19 is formed thereunder. Since other configurations are the same as those in FIG. 1, the same reference numerals are given, and detailed descriptions thereof are omitted.

  In this way, the upper layer of the impurity layer is formed so as to have a lower impurity concentration than the lower layer thereof, so that not only the gate oxide film 21 portion on the threading dislocation 31 but also the gate corner portion in the vicinity of the pit 32 is formed. The electric field concentration at 33 can be suppressed, and the reliability can be further improved.

  In this modification, the channel dope region is shown as being divided into two layers, but may be formed as being divided into three or more layers. Furthermore, the channel doped region of one layer may have a concentration gradient in the depth direction, and the n-type impurity concentration in the surface layer portion may be formed to be relatively low. Further, by combining the modification example of FIG. 7 and the modification example of FIG. 8, a channel dope region having a plurality of layers or gradients may be formed in a region deeper than the surface of the drift layer 12.

  Similarly, the channel doped region 16, the n-type doped region 53, and the n-type doped region 73 in the embodiment described later may have a concentration gradient in the depth direction, or may be embedded from the surface of the drift layer. It may be formed.

<Effect>
According to the embodiment of the present invention, a semiconductor device includes a first conductivity type (n-type) silicon carbide substrate 11, a first conductivity type silicon carbide drift layer 12 formed on the silicon carbide substrate 11, and Corresponding to the crystal defects of the drift layer 12, a pit 32 having a hollow shape formed on the surface of the drift layer 12 and a gate oxide film 21 as an electric field relaxation layer formed accompanying the pit 32 are provided.

  According to such a configuration, in the semiconductor device using silicon carbide having crystal defects, the gate oxide film 21 as the electric field relaxation layer is formed in the pits 32 formed corresponding to the positions of the crystal defects. An electric field relaxation layer is effectively formed at a location where electric field concentration occurs due to crystal defects. Therefore, the reliability of the gate oxide film 21 can be improved, the leakage current can be reduced, the reduction in throughput can be suppressed, and the yield of the semiconductor device can be improved efficiently.

  Further, according to the embodiment of the present invention, the first conductivity type (n-type) having a higher impurity concentration than the drift layer 12 formed on the surface of the drift layer 12 excluding the region where the pits 32 having a hollow shape are formed. A channel doped region 16 which is an impurity layer of

  According to such a configuration, since the channel dope region 16 is not formed in the region where the pit 32 is formed, a high electric field is applied to the gate oxide film 21 on the crystal defect when a high voltage is applied to the drain side. Thus, the reliability of the gate oxide film 21 can be improved. Therefore, the yield of semiconductor devices can be improved efficiently.

  Further, according to the embodiment of the present invention, the low concentration region 18 that is the upper layer of the impurity layer has a lower impurity concentration than the high concentration region 19 that is the lower layer.

  According to such a configuration, electric field concentration at the gate corner portion 33 can be effectively suppressed. Thus, the yield of semiconductor devices can be improved.

  In addition, according to the embodiment of the present invention, the first conductivity type (n-type) having a higher impurity concentration than that of the drift layer 12 formed by being embedded in the surface of the drift layer 12 excluding the region where the pits 32 are formed. A channel dope region 17 which is an impurity layer is provided.

  According to such a configuration, electric field concentration at the gate corner portion 33 can be effectively suppressed. Thus, the yield of semiconductor devices can be improved.

  According to the embodiment of the present invention, (a) a step of forming a drift layer 12 of a first conductivity type (n-type) silicon carbide on the first conductivity type silicon carbide substrate 11, and (b) A step of forming a pit 32 having a hollow shape corresponding to a crystal defect of the drift layer 12 on the surface of the drift layer 12, and a step of forming a gate oxide film 21 which is an electric field relaxation layer attached to the pit 32. Is provided.

  According to such a method, in the semiconductor device using silicon carbide having crystal defects, the gate oxide film 21 as the electric field relaxation layer is formed in the pits 32 formed in a self-aligned manner corresponding to the position of the crystal defects. As a result, an electric field relaxation layer is formed at a location where electric field concentration occurs due to crystal defects. Therefore, the reliability of the gate oxide film 21 can be improved, the leakage current can be reduced, and the yield of the semiconductor device can be improved efficiently.

  In addition, according to the embodiment of the present invention, (b) the wet oxidation step in which the step of forming the pits 32 having a hollow shape corresponding to the crystal defects of the drift layer 12 on the surface of the drift layer 12 is performed in a steam atmosphere. It is.

  Thus, when thermal oxidation is performed at a relatively low temperature and in a wet atmosphere, the surface of the drift layer 12 where the threading dislocations 31 exist is accelerated and oxidized because the oxidation rate depends on the plane orientation. A film 42 is formed. Therefore, the surface of the drift layer 12 where the threading dislocations 31 exist can be found in a self-aligned manner, and the yield of the semiconductor device can be improved efficiently.

  In addition, according to the embodiment of the present invention, (d) the oxide film formed on the surface of the drift layer 12 after the step of forming the pits 32 on the surface of the drift layer 12 and before the step of forming the gate oxide film 21. The first conductivity type (n-type) impurity is implanted from above the silicon oxide film 41 and the accelerating oxide film 42, and is a first conductivity type (n-type) impurity layer having a higher impurity concentration than the drift layer 12. Forming a channel doped region 16.

  According to such a method, since the pits 32 are formed on the surface of the drift layer 12 where the threading dislocations 31 exist by accelerated oxidation, in the ion implantation performed over the accelerated oxide film 42 in that portion, Unlike in the case of ion implantation performed through the silicon oxide film 41 in other parts, the channel dope region 16 is not formed. Therefore, it is possible to avoid the channel dope region 16 from being formed on the surface of the drift layer 12 where the threading dislocation 31 exists in a self-aligning manner.

Second Embodiment
<Configuration>
FIG. 9 is a cross-sectional view of a semiconductor device according to the second embodiment of the present invention. In the semiconductor device according to the present invention, the portion where the crystal defect exists is important, so the portion where the crystal defect exists in the SiC-MOSFET is extracted and shown.

  As shown in FIG. 9, the semiconductor device 104 has a surface (pit 32) where crystal defects such as threading dislocations 31 exist on the surface of the drift layer 12 formed on the n-type silicon carbide substrate 11. The difference from the first embodiment is that the p-type layer 20 for relaxing the electric field is diffused. Since other configurations are the same as those in FIG. 1, the same reference numerals are given, and detailed descriptions thereof are omitted.

  In the semiconductor device 104 according to the present embodiment, when a high voltage is applied to the drain electrode 25, the p-type layer 20 is formed in a region (pit 32) where threading dislocations 31 in which reliability is a concern. Therefore, the electric field concentration in the portion most feared to be destroyed is more positively mitigated, and further improvement in reliability can be realized.

  In particular, in the case of an element using silicon carbide as a semiconductor material, since the breakdown electric field of silicon carbide is large, it is often designed to apply a high electric field to silicon carbide, and the electric field strength applied to the gate oxide film 21 is accordingly increased. growing. Therefore, it is very effective to use the structure of the present invention for reducing the electric field concentration in the semiconductor device.

<Manufacturing method>
Next, a method for manufacturing a semiconductor device according to the second embodiment of the present invention will be described. Since the process up to the formation of the channel dope region 16 shown in FIG. 4 is the same as that of the first embodiment, a detailed description thereof will be omitted.

  After the channel dope region 16 is formed, the silicon oxide film 41 and the accelerating oxide film 42 are removed, and then, as shown in FIG. 10, for example, Al ions are implanted to cause threading dislocations 31 on the surface of the drift layer 12. The p-type layer 20 is diffused and formed in the region (pit 32) to be formed.

  The impurity concentration of the p-type layer 20 is a condition that is larger than the impurity concentration of the drift layer 12 and the same as or smaller than the impurity concentration of the channel dope region 16. It is set to be the same as or shallower than the doped region 16.

  When ion implantation is performed under such conditions, the p-type region is not formed in the drift layer 12 in the region where the channel dope region 16 and the threading dislocation 31 are not present, and the surface of the drift layer 12 where the threading dislocation 31 is present is The p-type layer 20 is formed in a self-aligning manner. Thereafter, through the same process as in the first embodiment, the SiC-MOSFET as shown in FIG. 9 is completed.

<Modification 1>
FIG. 11 is a view showing a modification (semiconductor device 105) of the semiconductor device according to the second embodiment. 11 differs from FIG. 9 in that the surface of the drift layer 12 where the threading dislocations 31 are present is flattened and the back surface of the gate oxide film 21 is flat, and the channel dope region is not present. Since other configurations are the same as those in FIG. 9, the same reference numerals are given, and detailed descriptions thereof are omitted.

  As described above, the region where the gate oxide film 21 is formed is planarized leaving a part of the p-type layer 20, so that the reliability of the gate oxide film 21 when a high electric field is applied to the drain electrode 25. Is further improved. Further, since there is no channel dope region, the threshold voltage can be increased.

  The semiconductor device 105 of FIG. 11 can be manufactured by performing the following steps after performing the planarization process after the p-type layer 20 forming step shown in FIG. The planarization treatment can be performed by, for example, chemical mechanical polishing (CMP) or an etch back method. In the case of performing the planarization process, it is preferable that the thickness of the drift layer 12 is designed to be about several tens nm to several μm, assuming that the film thickness is reduced by the process. Similarly, the channel dope region 16 and the p-type layer 20 are preferably formed deeply.

<Modification 2>
FIG. 12 is a view showing another modified example (semiconductor device 106) of the semiconductor device according to the second embodiment. The structure shown in FIG. 12 is a structure when the semiconductor device manufacturing method according to the second embodiment is adopted in a portion having a relatively large defect such as the carrot defect 34. Components similar to those in FIG. 9 are denoted by the same reference numerals, and detailed description thereof is omitted.

  A prism area layer defect exists on the surface of the carrot defect 34, and the portion is oxidized at a higher speed to form a relatively wide concave shape as shown in FIG.

  The carrot defect 34 has a size of about several hundreds μm, and when a MOSFET is usually formed in that portion, it causes a defect such as drain leakage. However, when the method of manufacturing a semiconductor device according to the present embodiment is used. Since the portion is protected by the p-type layer 20 and inactivated, such a defect can be suppressed.

  In this embodiment, the cell pitch is 5 μm to 20 μm, and the carrot defect 34 extends over a plurality of cells. Therefore, since the p-type layer 20 is set to the same potential as the source, a stable switching operation of the MOSFET can be realized.

  Thus, if the structure is such that crystal defects are formed over the surface, the present invention can be applied because accelerated oxidation is performed by thermal oxidation regardless of the type of defects.

  Note that a semiconductor device may be formed by combining the modification in FIG. 12 with a planarization process as shown in FIG.

<Effect>
According to the embodiment of the present invention, the step of forming the electric field relaxation layer is a step of diffusing the p-type layer 20 which is the second conductivity type (p-type) layer on the surface of the pit 32 having a hollow shape.

  According to such a method, in the semiconductor device using silicon carbide having crystal defects, the p-type layer 20 as the electric field relaxation layer is formed in the pits 32 formed in a self-aligned manner corresponding to the position of the crystal defects. As a result, an electric field relaxation layer is formed at a location where electric field concentration occurs due to crystal defects. Therefore, leakage current can be reduced and the yield of the semiconductor device can be improved efficiently.

  In addition, according to the embodiment of the present invention, (e) the step of cutting and planarizing the surface of the drift layer 12 including the pits 32 so that the p-type layer 20 diffused on the surface of the pits 32 remains.

  According to such a method, when a high electric field is applied to the drain electrode 25, it is possible to suppress a high electric field from being applied to the gate oxide film 21 on the crystal defect, and the reliability of the gate oxide film 21 is improved. Is further improved. Further, since the channel dope region is not formed, the threshold voltage can be increased.

<Third Embodiment>
<Configuration>
FIG. 13 is a cross-sectional view of a semiconductor device according to the third embodiment of the present invention, specifically, an n-type silicon carbide Schottky barrier diode (SiC-SBD).

  As shown in FIG. 13, in semiconductor device 107, n type drift layer 52 is formed on n type silicon carbide substrate 51. An n-type doped region 53 is formed on the surface of the drift layer 52.

  Here, threading dislocations 35 are present from the surface of silicon carbide substrate 51 toward the surface of drift layer 52. The surface of the drift layer 52 around the region where the threading dislocations 35 are present has a pit shape (dent shape) (pits 36 in FIG. 13). A p-type layer 54 is diffused on the surface of the drift layer 52 (pits 36) where the threading dislocations 35 are present in order to relax the electric field. An anode electrode 62 is formed on the drift layer 52 via a Schottky electrode 61. On the other hand, a cathode electrode 63 is formed below the silicon carbide substrate 51.

  If crystal defects such as threading dislocations 35 are present at the interface between the Schottky electrode 61, which is a metal layer covering the pits 36, and the drift layer 52, there is a concern about an increase in leakage current and breakdown due to electric field concentration during reverse bias. In the semiconductor device according to the present invention, the p-type layer 54 is formed in that portion, whereby leakage current can be reduced and long-term reliability can be improved.

<Manufacturing method>
Next, a method for manufacturing a semiconductor device according to the third embodiment of the present invention will be described with reference to FIGS.

  First, as shown in FIG. 14, an n-type low-resistance silicon carbide substrate 51 is prepared, and an n-type drift layer 52 is formed by epitaxial growth. As shown in FIG. 14, the drift layer 52 includes crystal defects such as threading dislocations 35 in at least one place.

In the present embodiment, the n-type impurity concentration in the drift layer 52 is 1 × 10 ¹³ cm ⁻³ to 1 × 10 ¹⁸ cm ⁻³ , and the thickness is 4 μm to 200 μm.

  Next, as shown in FIG. 15, a silicon oxide film 43 is formed on the drift layer 52 by a thermal oxidation method. The silicon oxide film 43 is formed, for example, by heat treatment at 1000 to 1200 ° C. for several tens of minutes to 2 hours in an atmosphere containing water vapor.

  When thermal oxidation is performed at such a relatively low temperature and in a wet atmosphere, the oxidation rate is dependent on the plane orientation. Therefore, as shown in FIG. A fast oxide film 44 is formed.

  The film thickness of the silicon oxide film 43 is, for example, about 10 to 70 nm, and the film thickness of the accelerated oxide film 44 is about 20 to 300 nm, which is about 2 to 4 times the film thickness of the silicon oxide film 43.

Next, as shown in FIG. 16, an n-type doped region 53 is formed by implanting, for example, N ions through the silicon oxide film 43 and the accelerating oxide film 44. The impurity concentration of the n-type doped region 53 is larger than the impurity concentration of the drift layer 52 and is, for example, about 2 × 10 ¹³ cm ^{−3 to} 5 × 10 ¹⁸ cm ⁻³ . The implantation depth of the n-type doped region 53 is set so as not to be formed in the portion where the threading dislocation 35 exists, that is, a depth shallower than the depth of the hollow shape. Formation of such an n-type doped region 53 can be realized by implanting N ions with a relatively low energy of several keV to several hundred keV.

  After the n-type doped region 53 is formed, the silicon oxide film 43 and the speed-up oxide film 44 are removed, and then, as shown in FIG. A p-type layer 54 is formed in the existing region (pit 36).

  The impurity concentration of the p-type layer 54 is a condition that is larger than the impurity concentration of the drift layer 52 and the same as or lower than the impurity concentration of the n-type doped region 53. The formation depth of the p-type layer 54 is It is made to be the same as or shallower than the n-type doped region 53.

  When ion implantation is performed under such conditions, the p-type region is not formed in the drift layer 52 in the region where the n-type doped region 53 or the threading dislocation 35 does not exist, and the surface of the drift layer 52 where the threading dislocation 35 exists is formed. The p-type layer 54 can be formed in a self-aligning manner.

Next, a termination region for relaxing an electric field generated at the end of Schottky electrode 61 is formed in drift layer 52 (not shown). The termination region is formed, for example, by implanting Al ions, and the impurity concentration thereof is larger than the impurity concentration of the drift layer 52, for example, 2 × 10 ¹³ cm ^{−3 to} 5 × 10 ¹⁸ cm ^−3. Is done.

  Next, annealing is performed in an inert gas atmosphere such as Ar gas by a heat treatment apparatus. The annealing is performed at a temperature of 1300 ° C. to 1900 ° C. for about 30 seconds to 1 hour, for example. By this annealing, ion-implanted n-type impurities such as N and p-type impurities such as Al are activated.

  Finally, by forming the Schottky electrode 61, the anode electrode 62, and the cathode electrode 63 on the back surface, the SiC-SBD as shown in FIG. 13 is completed.

  In order to make ohmic contact between the silicon carbide substrate 51 and the cathode electrode 63, before forming the cathode electrode 63, for example, Ni is deposited on the entire surface of the substrate and heat treatment is performed at 600 to 1000 ° C. to form silicide (FIG. Not shown).

  The Schottky electrode 61 is formed, for example, by depositing Ti, Ni, Mo, W, or the like by sputtering or vapor deposition and annealing at about several hundred to 700 ° C.

  The anode electrode 62 is formed by depositing a metal made of Al, Cu, Ti, Ni, Mo, W, Ta, nitrides thereof, a laminated film thereof, or an alloy layer thereof by a sputtering method or an evaporation method, and performing patterning. Form with.

  The cathode electrode 63 is formed by sputtering or vapor deposition of a metal film such as Ti, Ni, Ag, or Au.

<Modification>
FIG. 18 is a view showing a modification (semiconductor device 108) of the semiconductor device according to the third embodiment. 18 differs from FIG. 13 in that the surface of the drift layer 52 where the threading dislocations 35 exist is flattened and the back surface of the Schottky electrode 61 is flat, and that the n-type doped region 53 does not exist. Since other configurations are the same as those in FIG. 13, the same reference numerals are given, and detailed descriptions thereof are omitted.

  As described above, the surface of the drift layer 52 is flattened while leaving a part of the p-type layer 54, and the back surface of the Schottky electrode 61 is flattened, whereby the leakage current reduction at the time of reverse bias can be further reduced. In addition, electric field concentration during reverse bias can be further suppressed, and long-term reliability can be improved.

  The semiconductor device 108 shown in FIG. 18 can be manufactured by performing the flattening process and subsequent steps after the formation process of the p-type layer 54 shown in FIG. The planarization process can be performed by, for example, chemical mechanical polishing (CMP) or an etch back method.

  In the case of performing the planarization process, it is preferable that the thickness of the drift layer 52 be designed to be about several tens nm to several μm, assuming that the film thickness is reduced by the process. Similarly, the n-type doped region and the p-type layer are preferably formed deeply.

  In the present embodiment, for example, if the structure is formed over the surface like a carrot defect, the present invention can be applied because the oxidation is accelerated by thermal oxidation regardless of the type of defect. It is not limited to threading dislocations.

<Fourth embodiment>
<Configuration>
In the first to third embodiments, the n-type doped region is selectively formed by performing ion implantation through the thermal oxide film. In the device process using silicon carbide, for example, Since the pit shape (recessed shape) is formed in the defective portion by epitaxial growth, sacrificial oxidation, or the like, selective ion implantation is possible without performing thermal oxidation using the shape.

<Manufacturing method>
FIG. 19 shows a method of manufacturing a semiconductor device according to the fourth embodiment of the present invention, specifically, a channel dope region forming step in the first and second embodiments, and an n-type doped region forming in the third embodiment. It is a figure which shows the manufacturing process corresponded to a process.

  The surface of drift layer 72 formed on silicon carbide substrate 71 has threading dislocations 37 and has a pit shape (dent shape). A mask material 45 that can relieve the electric field is formed flat thereon. By implanting N ions, for example, through the mask material 45, an n-type doped region 73 is formed in a region excluding the region where the threading dislocations 37 are present (pits 38).

  Formation of such an n-type doped region 73 can be realized by implanting N ions with a relatively low energy of several keV to several hundred keV.

  The mask material 45 can be formed flat, for example, by forming a resist material or a spin-on-glass film by a spin coating method. For example, such a mask material can be formed by performing a planarization process after forming a silicon oxide film by a CVD method.

  The manufacturing method of the semiconductor device according to the present embodiment is applicable to all of the first to third embodiments described above. In addition, the present embodiment can be applied regardless of the type of defect as long as it has a structure in which a recess shape is formed during the process regardless of threading dislocations.

  In the embodiment of the present invention, the material of each component, material, conditions for implementation, and the like are also described, but these are examples and are not limited to those described.

  In addition, within the scope of the present invention, the present invention can be freely combined with each embodiment, modified with any component in each embodiment, or omitted with any component in each embodiment.

  11, 51, 71 Silicon carbide substrate, 12, 52, 72 drift layer, 13 well region, 14 source region, 15 well contact region, 16, 17 channel doped region, 18 low concentration region, 19 high concentration region, 20, 54 p-type layer, 21 gate oxide film, 22 gate electrode, 23 interlayer insulating film, 24 source electrode, 25 drain electrode, 31, 34, 35, 37 threading dislocation, 32, 36, 38 pit, 33 gate corner, 34 carrot Defects, 41, 43 Silicon oxide film, 42, 44 Speed-up oxide film, 45 Mask material, 53, 73 N-type doped region, 61 Schottky electrode, 62 Anode electrode, 63 Cathode electrode, 101, 102, 103, 104, 105, 106, 107, 108 Semiconductor device.

Claims (21)

A first conductivity type silicon carbide semiconductor substrate;
A first conductivity type silicon carbide drift layer formed on the silicon carbide semiconductor substrate;
Corresponding to the crystal defects of the drift layer, a hollow shape formed on the surface of the drift layer,
An electric field relaxation layer formed in association with the hollow shape,
Semiconductor device. The electric field relaxation layer is an insulating layer,
The semiconductor device according to claim 1. The electric field relaxation layer is filled in the hollow shape,
The semiconductor device according to claim 1. The electric field relaxation layer is a layer of a second conductivity type,
The semiconductor device according to claim 1. The electric field relaxation layer is diffused on the depression-shaped surface,
The semiconductor device according to claim 1 or 4. Further comprising an insulating layer formed to cover the hollow shape,
The semiconductor device according to claim 4 or 5. The insulating layer back surface is flat,
The semiconductor device according to claim 6. Further comprising a metal layer formed to cover the hollow shape,
The semiconductor device according to claim 4 or 5. The metal layer back surface is flat,
The semiconductor device according to claim 8. It further comprises a first conductivity type impurity layer formed on the surface of the drift layer excluding the region where the hollow shape is formed and having an impurity concentration higher than that of the drift layer.
The semiconductor device according to claim 1. The upper layer of the impurity layer has a lower impurity concentration than the lower layer,
The semiconductor device according to claim 10. The semiconductor device further comprises an impurity layer of a first conductivity type having an impurity concentration higher than that of the drift layer, which is embedded in the surface of the drift layer excluding the region where the hollow shape is formed,
The semiconductor device according to claim 1. The crystal plane on which the hollow shape is formed is a (0001) plane,
The semiconductor device according to claim 1. (A) forming a drift layer of the first conductivity type silicon carbide on the first conductivity type silicon carbide semiconductor substrate;
(B) forming a recess shape corresponding to a crystal defect of the drift layer on the surface of the drift layer;
(C) including a step of forming an electric field relaxation layer associated with the hollow shape,
A method for manufacturing a semiconductor device. The step (b) is a step of oxidizing the drift layer surface to form the depression shape,
The method for manufacturing a semiconductor device according to claim 14. The step (b) is a step performed in a steam atmosphere,
The method for manufacturing a semiconductor device according to claim 15. (D) After the step (b) and before the step (c), the first conductivity type impurity is implanted from above the oxide film formed on the drift layer surface in the step (b), and the drift Forming a first conductivity type impurity layer having an impurity concentration higher than that of the layer;
The step (c) is a step of forming the electric field relaxation layer after removing the oxide film,
The method for manufacturing a semiconductor device according to claim 15 or 16. The step (a) is a step of forming the drift layer by epitaxially growing the drift layer;
The step (b) is performed together with the step (a), and is a step of forming the depression shape on the surface of the drift layer together with the epitaxial growth.
The method for manufacturing a semiconductor device according to claim 14. The step (c) is a step of filling an insulating layer in the hollow shape,
The manufacturing method of the semiconductor device in any one of Claims 14-18. The step (c) is a step of diffusing a layer of the second conductivity type on the depression-shaped surface,
The manufacturing method of the semiconductor device in any one of Claims 14-18. (E) further comprising a step of shaving and flattening the surface of the drift layer including the recess shape so that the layer of the second conductivity type diffused on the surface of the recess shape remains.
The method for manufacturing a semiconductor device according to claim 20.

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