JP2015162492A - Semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing technique which can prevent field concentration at a bottom of a trench gate and which is unlikely to cause a problem due to a layer structure such as a stage cut of an electrode and a decrease in withstand voltage.SOLUTION: A manufacturing method of a semiconductor device 1 by a gallium nitride semiconductor comprises the following processes: (a) a process of forming irregularities 30 on a surface of a first n-type semiconductor layer 20 provided on a substrate 10 of an n-type semiconductor on the side opposite to the substrate 10; (b) a process of forming a p-type semiconductor layer 40 which functions as a channel layer of the semiconductor device 1 on the first n-type semiconductor layer where the irregularities 30 are formed on the side opposite to the substrate 10; (c) a process of reducing a thickness of the p-type semiconductor layer 40 by etching the p-type semiconductor layer 40; and (d) a process of forming a second n-type semiconductor layer 50 on the etched p-type semiconductor layer 40 on the side opposite to the first n-type semiconductor layer 20.

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  In a trench gate type MOSFET (Metal-oxide-semiconductor field-effect transistor), it is known that strong electric field concentration occurs at the bottom of the trench gate. In order to alleviate this electric field concentration, a structure in which a p-type semiconductor layer is arranged around the bottom of the trench gate is used (Patent Document 1). Such a p-type semiconductor layer is formed, for example, by ion implantation when manufacturing a trench gate type MOSFET made of a SiC semiconductor.

Japanese Patent No. 3387563 Japanese Patent No. 4738562

  However, in a GaN semiconductor, a p-type semiconductor layer cannot be formed by ion implantation. Therefore, when manufacturing a trench gate type MOSFET made of a GaN semiconductor, (i) a drift layer (n type semiconductor layer) located under the p type semiconductor layer is formed, and (ii) a trench gate is formed afterwards. A drift layer near the position to be processed is processed into a desired shape by etching, and (iii) a p-type semiconductor layer is grown on the drift layer, and a p-type semiconductor layer can be disposed around the bottom of the trench gate. .

  In a GaN semiconductor, when a crystal is regrown on a patterned surface, the crystal growth rate varies depending on the plane orientation and growth conditions. Therefore, when a p-type semiconductor layer having a thickness of 1 μm or less, which is preferable as a channel layer of a trench gate type MOSFET, is crystal-grown on a patterned drift layer, the p-type semiconductor layer is grown so that the surface becomes flat. It is difficult to control. That is, unevenness due to the drift layer pattern (unevenness) is formed on the surface of the p-type semiconductor layer. When a contact layer (n-type semiconductor layer) is formed on the p-type semiconductor layer and an electrode is further formed thereon, unevenness due to the drift layer pattern is also formed on the surface of the contact layer. As a result, step breakage may occur in the electrode formed on the unevenness of the contact layer.

  For the above reason, it is difficult to control the growth of the p-type semiconductor layer so that the thickness of the p-type semiconductor layer formed on the patterned drift layer is constant in each part in the plane direction. For this reason, the following problems occur in the trench gate type MOSFET. That is, when the trench for the gate electrode is formed on the place where the pattern of the drift layer is formed, the thickness of the p-type semiconductor layer located in the vicinity of the trench is not accurately controlled. As a result, there may be a portion in the vicinity of the trench where the thickness of the p-type semiconductor layer separating the drift layer and the contact layer is not sufficient. For this reason, when the impurity concentration of the p-type semiconductor layer varies, the trench breakdown voltage may not be achieved as designed in the trench gate type MOSFET.

  Therefore, there has been a demand for a technique for manufacturing a trench gate type MOSFET that can prevent electric field concentration at the bottom of the trench gate and that does not easily cause problems due to the layer structure such as electrode step-out and breakdown voltage reduction. In addition, in the technical field of semiconductor devices, simplification of the manufacturing method, downsizing of the manufacturing apparatus, cost reduction, resource saving, and easy manufacturing method have been desired.

  SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following forms.

(1) According to one aspect of the present invention, a method for manufacturing a semiconductor device using a gallium nitride semiconductor is provided. In this method, (a) a first n-type semiconductor layer provided on an n-type semiconductor substrate has a step of forming irregularities on a surface opposite to the substrate; and (b) the irregularities are formed. Forming a p-type semiconductor layer functioning as a channel layer of the semiconductor device on a side opposite to the substrate with respect to the first n-type semiconductor layer; and (c) forming the p-type semiconductor layer Etching to reduce the thickness of the p-type semiconductor layer; and (d) a second side of the etched p-type semiconductor layer opposite to the first n-type semiconductor layer. Forming an n-type semiconductor layer. In such an embodiment, the p-type semiconductor layer is formed to be thicker than necessary for the channel layer of the semiconductor device, and then the p-type semiconductor layer is etched to reduce the thickness, thereby manufacturing the channel layer of the semiconductor device. doing. For this reason, the above-described aspect is different from the aspect in which the p-type semiconductor layer is formed to the necessary thickness as the channel layer, the formation of the p-type semiconductor layer is completed, and the second n-type semiconductor layer is formed thereon. The following advantages are provided. That is, the unevenness formed in the first n-type semiconductor layer is not easily reflected in the shape of the layer formed after the p-type semiconductor layer. Therefore, in the semiconductor device manufactured by the above manufacturing method, the electric field concentration at the bottom of the trench gate can be reduced by appropriately setting the configuration of the first n-type semiconductor layer and the p-type semiconductor layer formed with unevenness. It can be prevented, and step breakage hardly occurs in an electrode formed on a layer formed after the p-type semiconductor layer.

(2) In the above method, the step (b) is a mode in which the p-type semiconductor layer having a thickness of 400% or more of the dimension of the irregularities in the stacking direction of the layers is formed. it can. According to such an embodiment, in the step (b), a p-type semiconductor layer having a small degree of surface unevenness due to the unevenness of the first n-type semiconductor layer can be formed. For this reason, in the above-described aspect, each layer formed after the p-type semiconductor layer is compared with an aspect in which the p-type semiconductor layer is formed to a thickness necessary for the channel layer and the formation of the p-type semiconductor layer is finished. Unevenness formed in the first n-type semiconductor layer is difficult to be reflected.

(3) In the above method, the step (b) has unevenness on the surface having a size of 1/10 or less of the unevenness in the stacking direction of the layers, or has unevenness on the surface. It can be set as the aspect which is the process of forming the said p-type semiconductor layer which is not. Such an aspect has the following advantages compared to an aspect in which the p-type semiconductor layer is formed to the necessary thickness as the channel layer and the formation of the p-type semiconductor layer is finished regardless of the surface irregularities. That is, the unevenness formed in the first n-type semiconductor layer is not easily reflected in each layer formed after the p-type semiconductor layer.

  A plurality of constituent elements of each aspect of the present invention described above are not indispensable, and some or all of the effects described in the present specification are to be solved to solve part or all of the above-described problems. In order to achieve the above, it is possible to appropriately change, delete, replace with another new component, and partially delete the limited contents of some of the plurality of components. In order to solve part or all of the above-described problems or to achieve part or all of the effects described in this specification, technical features included in one embodiment of the present invention described above. A part or all of the technical features included in the other aspects of the present invention described above may be combined to form an independent form of the present invention.

  The present invention can be realized in various forms other than the above-described method. For example, a titanium nitride layer manufacturing apparatus, a titanium nitride layer manufacturing method, a semiconductor device manufacturing apparatus, a semiconductor device manufacturing apparatus control apparatus, a semiconductor device manufacturing apparatus control method, a computer program that implements the control method, and the like The present invention can be realized in the form of a non-temporary recording medium on which a computer program is recorded.

The flowchart which shows the manufacturing method of the trench gate type MOSFET 1 as 1st Embodiment of this invention. Sectional drawing which shows the n-type GaN substrate 10 prepared by step S10 of FIG. The figure which shows the intermediate product 2 of the state which completed the process of step S20. The figure which shows the intermediate product 3 of the state which the process of step S30 was completed. The figure which shows the intermediate product 4 of the state which the process of step S40 was completed. The figure which shows the intermediate | middle goods 5 of the state which the process of step S50 was completed. The figure which shows the intermediate product 6 of the state which the process of step S60 was completed. Sectional drawing which shows the main structures of trench gate type MOSFET1. Sectional drawing which shows the intermediate goods 6c of the state after step S60 in the case of employ | adopting another process instead of step S40, S50 of FIG.

A. Embodiment:
FIG. 1 is a flowchart showing a method of manufacturing a trench gate type MOSFET 1 as a first embodiment of the present invention. In step S10 of FIG. 1, an n-type GaN substrate 10 is prepared.

  FIG. 2 is a cross-sectional view showing the n-type GaN substrate 10 prepared in step S10 of FIG. The XYZ axes orthogonal to each other are shown in the lower left of FIG. In the following description, the position and size of each component in the manufacturing process of the trench gate type MOSFET 1 may be described with reference to the XYZ axes. In this specification, the positive z-axis direction is “upward”. The negative z-axis direction is “downward”. Further, the exposed surface of the layer where the z-axis positive side is exposed in each step is referred to as the “surface” of the layer. The same applies to FIGS. 3 to 9 and the description with reference to those drawings.

The n-type GaN substrate 10 is an n-type semiconductor wafer mainly composed of gallium nitride. In the present specification, “having X as a main component” means that the ratio of X in the total composition is 90 atomic% or more. The n-type GaN substrate 10 has a thickness of 330 μm. The carrier concentration of the n-type GaN substrate 10 is 3 × 10 ¹⁸ cm ⁻³ . In the present specification, the “thickness” of a layer means the dimension of the layer in the z-axis direction.

In step S <b> 20 of FIG. 1, an n ⁻ -GaN drift layer 20 is formed on the n-type GaN substrate 10. The n ⁻ -GaN drift layer 20 is formed by metal organic chemical vapor deposition (MOCVD). Specifically, the n-type GaN substrate 10 is placed in the furnace of the MOCVD apparatus, and the temperature of the susceptor of the MOCVD apparatus is set so that the growth temperature is 1050 ° C. Thereafter, tri-methyl gallium (TMG) as a raw material of gallium which is a group III element, NH ₃ as a raw material of nitrogen which is a group V element, and SiH ₄ as a raw material of Si which is a dopant are furnaces Introduced in. As a result, an n ⁻ -GaN drift layer 20 made of an n-type semiconductor containing gallium nitride as a main component and Si as a dopant is formed on the n-type GaN substrate 10.

FIG. 3 is a diagram illustrating the intermediate product 2 in a state where the process of step S20 is completed. In the manufacturing process of the trench gate type MOSFET 1, each layer is sequentially formed on the n-type GaN substrate 10 in the positive z-axis direction. In the present specification, the z-axis direction may be referred to as a “stacking direction”. The n ⁻ -GaN drift layer 20 formed on the n-type GaN substrate 10 has a thickness of about 10 μm. The donor concentration of the n ⁻ -GaN drift layer 20 is 8 × 10 ¹⁵ cm ⁻³ . In addition, in order to make an understanding of a technique easy, in FIGS. 2-9, the exact dimension of the thickness of each layer of an intermediate product is not reflected.

In step S <b> 30 of FIG. 1, a plate-like convex portion 30 having a substantially rectangular cross section is formed on the surface of the n ⁻ -GaN drift layer 20. The protrusion 30 is formed on the surface of the n ⁻ -GaN drift layer 20 opposite to the n-type GaN substrate 10. More specifically, after step S20, the intermediate product 2 shown in FIG. 3 is taken out from the MOCVD apparatus. Then, an etching mask is formed on the n ⁻ -GaN drift layer 20 of the intermediate product 2 by photolithography. This etching mask is made of SiO ₂ . Then, the intermediate product 2 with the etching mask is placed in an etching apparatus and dry etching is performed. As a result, the portion not covered with the etching mask is removed by an amount corresponding to the thickness of 1 μm, and the convex portion 30 is formed in the n ⁻ -GaN drift layer 20.

FIG. 4 is a diagram illustrating the intermediate product 3 in a state where the process of step S30 is completed. The convex portion 30 is a portion of the n ⁻ -GaN drift layer 20 that has not been removed in the etching performed in step S30. The dimension h in the z-axis direction of the convex portion 30 is 1 μm. A trench gate is formed in the region Rg where the protrusion 30 is provided in a later step.

In step S <b> 40 of FIG. 1, the pGaN channel layer 40 is formed on the n ⁻ -GaN drift layer 20 provided with the protrusions 30. The pGaN channel layer 40 is formed on the side opposite to the n-type GaN substrate 10 with respect to the n ⁻ -GaN drift layer 20. The pGaN channel layer 40 functions as a channel layer in the trench gate type MOSFET 1 as a finished product.

The pGaN channel layer 40 is also formed by metal organic chemical vapor deposition (MOCVD). Specifically, the intermediate product 3 for which the processing in step S30 has been completed is placed in the furnace of the MOCVD apparatus, and the temperature of the susceptor of the MOCVD apparatus is set so that the growth temperature is 1050 ° C. Then, trimethylgallium (TMG) as a raw material of gallium, NH ₃ as a raw material of nitrogen, and bis (cyclopentadienyl) magnesium (Cp ₂ Mg) as a raw material of magnesium as a dopant Is introduced into the furnace. As a result, a pGaN channel layer 40 made of a p-type semiconductor containing gallium nitride as a main component and magnesium as a dopant is formed on the n ⁻ -GaN drift layer 20.

FIG. 5 is a diagram showing the intermediate product 4 in a state where the process of step S40 is completed. The thickness T40 of the pGaN channel layer 40 formed on the n ⁻ -GaN drift layer 20 is about 4 μm. The Mg concentration as the dopant of the pGaN channel layer 40 is 4 × 10 ¹⁸ cm ⁻³ . In step S40, the pGaN channel layer 40 is formed with a thickness of 400% with respect to the dimension h (1 μm) in the z-axis direction of the protrusion 30 of the n ⁻ -GaN drift layer 20 formed in step S30. At that time, the dimension in the z-axis direction of the unevenness caused by the convex portion 30 of the n ⁻ -GaN drift layer 20 is 100 nm or less. That is, the z-axis dimension of the unevenness is 1/10 or less of the z-axis dimension h (1 μm) of the protrusion 30 on the surface of the pGaN channel layer 40.
That is, the surface of the pGaN channel layer 40 is substantially flat (see FIG. 5).

  In step S50 of FIG. 1, the pGaN channel layer 40 is etched until the thickness L of the portion of the pGaN channel layer 40 laminated on the plate-like convex portion 30 becomes about 0.7 μm. That is, the thickness of the pGaN channel layer 40 is reduced by etching until the thickness T41 of the pGaN channel layer in the finished trench gate MOSFET 1 is reached. More specifically, after step S40, the intermediate product 4 shown in FIG. 5 is taken out from the MOCVD apparatus. Then, the intermediate product 4 is placed in an etching apparatus, and dry etching is performed. As a result, the thickness L of the portion of the pGaN channel layer 40 stacked on the plate-like convex portion 30 is reduced to 0.7 μm.

  FIG. 6 is a diagram illustrating the intermediate product 5 in a state where the process of step S50 is completed. In the etching in step S50, the surface of the pGaN channel layer 40 is uniformly etched. In step S40, the pGaN channel layer 40 is formed so that the surface thereof is substantially flat (see FIG. 5). For this reason, the surface of the pGaN channel layer 40 is substantially flat even in the intermediate product 5 in the state in which the process of step S50 is completed.

In step S <b> 60 of FIG. 1, the n ⁺ -GaN contact layer 50 is formed on the pGaN channel layer 40 having a reduced thickness. The n ⁺ -GaN contact layer 50 is formed on the side opposite to the n ⁻ -GaN drift layer 20 with respect to the pGaN channel layer 40.

The n ⁺ -GaN contact layer 50 is also formed by metal organic chemical vapor deposition (MOCVD). Specifically, the intermediate product 5 for which the processing in step S50 has been completed is placed in the furnace of the MOCVD apparatus, and the temperature of the susceptor of the MOCVD apparatus is set so that the growth temperature is 1050 ° C. Thereafter, trimethylgallium (TMG) as a gallium raw material, NH ₃ as a nitrogen raw material, and SiH ₄ as a Si raw material as a dopant are introduced into the furnace. As a result, an n ⁺ -GaN contact layer 50 made of an n-type semiconductor containing gallium nitride as a main component and Si as a dopant is formed on the pGaN channel layer 40.

FIG. 7 is a diagram illustrating the intermediate product 6 in a state where the process of step S60 is completed. The n ⁺ -GaN contact layer 50 formed on the pGaN channel layer 40 has a thickness of about 0.2 μm. The donor concentration of the n ⁺ -GaN contact layer 50 is 3 × 10 ¹⁸ cm ⁻³ .

FIG. 8 is a cross-sectional view showing the main configuration of the trench gate type MOSFET 1. In step S70 of FIG. 1, the gate electrode 80, the source electrode 90, the drain electrode 100, etc. are formed on the intermediate product 6 shown in FIG. 7, and the trench gate type MOSFET 1 shown in FIG. 8 is completed. More specifically, a trench 60 that penetrates the n ⁺ -GaN contact layer 50 and the pGaN channel layer 40 in the negative z-axis direction and reaches the convex portion 30 of the n ⁻ -GaN drift layer 20 is formed. That is, the trench 60 is formed in the region Rg in the Y axis direction. The trench 60 is a groove extending along the x-axis direction in the trench gate type MOSFET 1.

Then, (i) ⁿ constituting the bottom surface of the trench 60 - and the exposed surface of the -GaN drift layer 20 (projecting portions 30), ⁿ defines the side surface of (ii) a trench 60 - -GaN drift layer 20 (projecting portions 30 ), The exposed surface of the pGaN channel layer 40, the exposed surface of the n ⁺ -GaN contact layer 50, and (iii) a part of the surface of the n ⁺ -GaN contact layer 50, an insulating film 70 is formed on the exposed surface. It is formed. Insulating film 70 is composed of SiO _2. A gate electrode 80 is formed on the insulating film 70 in the trench 60 and a part of the insulating film 70 on the n ⁺ -GaN contact layer 50. In this way, a trench gate electrode is formed.

Further, a source electrode 90 is formed in the pGaN channel layer 40 through the n ⁺ -GaN contact layer 50 in the negative z-axis direction at a position not included in the region Rg in the Y-axis direction. The source electrode 90 is electrically connected to the n ⁺ -GaN contact layer 50.

On the other hand, the drain electrode 100 is formed on the side opposite to the n ⁻ -GaN drift layer 20 of the n-type GaN substrate 10.

The trench gate type MOSFET 1 having such a configuration operates as follows. That is, when a voltage is applied to the gate electrode 80 in a state where a high voltage is applied between the source electrode 90 and the drain electrode 100, the insulating film 70 located on the side surface of the trench 60 in the pGaN channel layer 40. An inversion layer is formed at a portion C in the vicinity of. As a result, the n ⁺ -GaN contact layer 50, the inversion layer C (n-type) of the pGaN channel layer 40, the n ⁻ -GaN drift layer 20, and the n-type GaN substrate 10 are located between the source electrode 90 and the drain electrode 100. Through, and a current flows. On the other hand, when no voltage is applied to the gate electrode 80, the n ⁺ -GaN contact layer 50 and the n ⁻ -GaN drift layer 20 are separated by the pGaN channel layer 40. Between 100, no current flows.

In the present embodiment, as shown in FIG. 8, in the MOS (metal-oxide-semiconductor) structure of the trench gate electrode 80, the bottom of the trench (the gate electrode 80 and the insulating film 70) is n ⁻ -GaN drift layer 20. It is configured to bite into the convex part 30 of A corner portion at the bottom of the trench that has bitten into the convex portion 30 is indicated by “Ac” in FIG. 8. Further, the pGaN channel layer 40 forms a square portion Bc at the base of the convex portion 30. Of the pGaN channel layer 40, the portion C where the channel is formed when the trench gate type MOSFET 1 is ON is located between the protrusion 30 of the n ⁻ -GaN drift layer 20 and the n ⁺ -GaN contact layer 50. To position.

In such a configuration, when the trench gate type MOSFET 1 is ON, the electric field is divided into a corner portion Ac at the bottom of the trench and a corner portion Bc of the pGaN channel layer 40 and is concentrated. Therefore, the n ⁻ -GaN drift layer 20 is not provided with the plate-like convex portion 30 and the electric field concentrates only on the corner portion at the bottom of the trench, even when the trench gate type MOSFET 1 is ON. It is possible to prevent a strong electric field concentration from occurring at the bottom of the trench gate.

The trench gate type MOSFET 1 in the above embodiment corresponds to a “semiconductor device” in “Means for Solving the Problems”. The n ⁻ -GaN drift layer 20 corresponds to a “first n-type semiconductor layer”. The convex portion 30 corresponds to “unevenness”. The pGaN channel layer 40 corresponds to a “p-type semiconductor layer”. The n ⁺ -GaN contact layer 50 corresponds to a “second n-type semiconductor layer”.

  FIG. 9 is a cross-sectional view showing the intermediate product 6c in the state after step S60 when another process is employed instead of steps S40 and S50 in FIG. In the above embodiment, after step S30, in step S40, the pGaN channel layer 40 having a thickness T40 larger than the thickness T41 of the pGaN channel layer in the trench gate type MOSFET 1 is formed (see FIGS. 5 and 8). In step S50, the pGaN channel layer 40 was etched to the thickness of the pGaN channel layer in the trench gate type MOSFET 1 (see FIG. 6). On the other hand, the case where the following processes that do not include the process of reducing the thickness of the pGaN channel layer 40 are employed will be considered.

Also in this embodiment, after step S30 of FIG. 1, the pGaN channel layer 140 is formed on the n ⁻ -GaN drift layer 20 provided with the protrusions 30. The formation of the pGaN channel layer 140 is performed in the same manner as the formation of the pGaN channel layer 140 in step S40. However, the formation of the pGaN channel layer 140 is completed when the thickness Lc of the portion of the pGaN layer laminated on the plate-like convex portion 30 becomes 0.7 μm. Other points in the process of forming the pGaN channel layer 140 are the same as those in step S40 in FIG. In this step, the thickness Lc of the pGaN channel layer 140 formed on the portion of the n ⁻ -GaN drift layer 20 laminated on the plate-like convex portion 30 is 0.7 μm.

Thereafter, the step S60 of FIG. 1 is performed in the same manner as in the above embodiment, and the n ⁺ -GaN contact layer 150 is formed. The processing content of the step of forming the n ⁺ -GaN contact layer 150 is the same as that of step S60 in FIG. 1 except that the configuration of the intermediate product before and after the processing is different. FIG. 9 shows an intermediate product 6c obtained through such a process.

In the lamination by the metal organic vapor phase epitaxy method, the layer grows on the lower layer so that the unevenness on the surface of the lower layer is eliminated as time passes, in other words, the unevenness on the surface of the lower layer is filled. However, when the growth time of the layer is not sufficient with respect to the size (depth) of the surface roughness of the lower layer, the surface roughness of the lower layer is not sufficiently eliminated. In this comparative example, the formation of the pGaN channel layer 140 is completed when the thickness Lc of the portion of the pGaN layer stacked on the plate-like convex portion 30 becomes 0.7 μm. In that state, the time for the growth of the pGaN channel layer 140 is still so long that the shape of the convex portion 30 formed in the n ⁻ -GaN drift layer 20 is completely eliminated on the surface of the pGaN channel layer 140. It has not passed. Then, the n ⁺ -GaN contact layer 150 grows on the pGaN channel layer 140 that has the unevenness on the surface. As a result, in the intermediate product 6 c shown in FIG. 9, the shape of the convex portion 30 of the n ⁻ -GaN drift layer 20 is not the shape as it is on the surface of the n ⁺ -GaN contact layer 150, but is caused by the convex portion 30. A step D exists.

In this aspect, the portion of the pGaN channel layer 140 located on the upper surface of the convex portion 30 is formed substantially flat, and the step D is formed in the portion located outside the convex portion 30. In addition to the portion of the pGaN channel layer 140 located on the upper surface of the convex portion 30, the portion adjacent to that portion and located outside the convex portion 30 is also a portion located on the upper surface of the convex portion 30. In some cases, a step D is formed on the outer side. The n ⁺ -GaN contact layer 150 is formed along the upper surface of the pGaN channel layer 140 thus formed.

As a result, for example, when an electrode is formed on the n ⁺ -GaN contact layer 150 by vapor deposition from above (see the n ⁺ -GaN contact layer 50 and the gate electrode 80 in FIG. 8), The electrode layer becomes thinner. In such places, the resistance of the electrode increases. In addition, the electrode layer becomes discontinuous at the position of the step D, and so-called step breakage may occur. In such a place, the electrode across the stepped portion will not conduct.

On the other hand, in the present embodiment, first, the pGaN channel layer 40 is formed to a thickness of 400% of the step size of the protrusion 30 (see step S40 in FIG. 1 and FIG. 5). The resulting step is eliminated from the surface of the pGaN channel layer 40. Thereafter, the pGaN channel layer 40 is etched, and the thickness of the pGaN channel layer 40 is set to the thickness T41 of the pGaN channel layer in the trench gate type MOSFET 1 which is a finished product (Step S50 in FIG. 1 and FIG. 6). reference). For this reason, there are almost no irregularities on the surface of the pGaN channel layer 40 (see FIG. 6) and the surface of the n ⁺ -GaN contact layer 50 (see FIG. 7). As a result, even if an electrode layer is provided on the n ⁺ -GaN contact layer 50, there is a low possibility that a thin portion is formed in a part of the electrode layer or a portion that is not conductive is generated.

In the intermediate product 6c shown in FIG. 9, the thickness of the pGaN channel layer 40 may not be uniform in the portion of the pGaN channel layer 40 stacked on the plate-like convex portion 30. For example, the upper surface of the pGaN channel layer 40 may be inclined with respect to the upper surface of the protrusion 30. The shapes of the pGaN channel layer 140i and the n ⁺ -GaN contact layer 150i in such a case are indicated by broken lines in FIG. This phenomenon is presumed to occur when the n-type GaN substrate 10 is not formed with the C-plane as the upper surface and the OFF angle is set.

In this aspect, the portion of the pGaN channel layer 140 located on the upper surface of the convex portion 30 is formed in a planar shape inclined with respect to the upper surface of the convex portion 30, and is located outside the convex portion 30. In the portion, a step D is formed (see broken line portion in FIG. 9). In addition to the portion of the pGaN channel layer 140 located on the upper surface of the convex portion 30, the portion adjacent to that portion and located outside the convex portion 30 is also a portion located on the upper surface of the convex portion 30. In some cases, a step D is formed on the outer side. The n ⁺ -GaN contact layer 150 is formed along the upper surface of the pGaN channel layer 140 thus formed.

In the above case, the thickness Lc of the pGaN channel layer 140 that separates the convex portion 30 and the n ⁺ -GaN contact layer 150 is not constant. As a result, when the concentration of the dopant in the pGaN channel layer 140 varies, there is a possibility that dielectric breakdown occurs at a portion where the distance between the convex portion 30 and the n ⁺ -GaN contact layer 150 is short, and sufficient breakdown voltage is not realized. is there.

  On the other hand, in the present embodiment, the pGaN channel layer 40 is formed with a thickness of 400% with respect to the dimension h in the z-axis direction of the protrusion 30 in the process of step S40 of FIG. And in the lamination | stacking by a metal organic chemical vapor deposition method, a layer grows so that the unevenness | corrugation of the surface of a lower layer may be eliminated with progress of time. For this reason, even if the thickness of the portion of the pGaN channel layer 40 laminated on the convex portion 30 is not uniform in the middle of the layer growth, the convex portion is not formed when the process of step S40 is completed. The thickness of the pGaN channel layer 40 on the portion 30 is substantially constant. Thereafter, in step S50 of FIG. 1, the pGaN channel layer 40 is etched until the thickness L of the portion of the pGaN channel layer 40 laminated on the convex portion 30 becomes about 0.7 μm (FIGS. 6 and 6). 7).

Therefore, in the present embodiment, the thickness L of the pGaN channel layer 40 that separates the convex portion 30 and the n ⁺ -GaN contact layer 50 is constant (see FIGS. 7 and 8). . As a result, a sufficient region where a depletion layer is formed can be ensured between the convex portion 30 and the n ⁺ -GaN contact layer 50. Therefore, even if the dopant concentration in the pGaN channel layer 40 varies, there is a low possibility that dielectric breakdown will occur between the convex portion 30 and the n ⁺ -GaN contact layer 50, and a sufficient breakdown voltage is realized.

B. Variation:
The present invention is not limited to the above-described examples and embodiments, and can be implemented in various modes without departing from the gist thereof. For example, the following modifications are possible.

B1. Modification 1:
In the above embodiment, the protrusion 30 of the n ⁻ -GaN drift layer 20 has a substantially rectangular cross-sectional shape. However, the unevenness formed in a certain layer is not limited to such a shape. That is, it is possible to adopt a mode in which convex portions and concave portions having a triangular cross section and convex portions and concave portions having a trapezoidal cross section are formed on the surface of the layer.

  However, the unevenness formed in the layer preferably includes a convex portion having a flat upper surface. In the semiconductor device, a trench is preferably formed on the flat upper surface. In such an aspect, the upper surface of the channel layer disposed on the convex portion is formed almost flat, so that the thickness of the channel layer is substantially constant on the convex portion (see L in FIG. 8). As a result, the thickness of the channel layer is substantially constant in the vicinity of the trench, and it is easy to realize the breakdown voltage as designed in the trench gate type MOSFET.

B2. Modification 2:
In the above embodiment, in step S40 of FIG. 1, the pGaN channel layer has a thickness of 400% with respect to the dimension h in the z-axis direction of the projection 30 of the n ⁻ -GaN drift layer 20 formed in step S30. 40 is formed. However, the ratio of the dimension of the formed unevenness to the thickness of the layer formed thereafter is not limited to 400%.

  In the growth of the layer, the layer grows on the lower layer so that the unevenness on the surface of the lower layer is eliminated as time passes, in other words, the unevenness on the surface of the lower layer is filled. For this reason, it is considered that the unevenness of the upper surface of the provided layer becomes smaller as the growth time of the layer provided on the uneven layer is longer and the thickness of the layer is increased. Therefore, the ratio between the size of the formed irregularities and the thickness of the layer formed thereafter may be more than 400%.

  Further, the flatness of the lower structure required for exhibiting performance differs depending on the material of the electrode formed later and the structure formed thereafter. Therefore, the ratio between the size of the formed irregularities and the thickness of the layer formed thereafter may be smaller than 400%.

B3. Modification 3:
In the above embodiment, the dimension of the irregularities in the z-axis direction on the surface of the pGaN channel layer 40 formed in step S40 of FIG. 1 is 1 / axis dimension of the axial direction of the convex part 30 of the n ⁻ -GaN drift layer 20. It is 10 or less. However, the flatness required for exhibiting performance differs depending on the material of the electrode formed later and the structure formed thereafter. Therefore, the ratio between the dimension of the formed irregularities and the dimension of the irregularities on the surface of the layer formed thereafter may be larger than 1/10. The “surface unevenness dimension” refers to the distance between points that are farthest in the stacking direction within the region corresponding to the unevenness provided in the layer below the surface.

B4. Modification 4:
In the above embodiment, the pGaN channel layer 40 as the channel layer is first formed with an excessive thickness in step S40 of FIG. 1, and then the thickness of the pGaN channel layer 40 is reduced in step S50. Unevenness on the surface of the contact layer on which the electrode is formed is reduced.

  However, the processing for reducing the unevenness of the surface in the semiconductor device is performed by forming the layer formed after the channel layer, such as the contact layer, with an excessive thickness first and then reducing the thickness later. May be. Even in such an embodiment, unevenness on the surface of the layer on which the electrode is formed can be reduced, and disconnection of the electrode can be prevented.

  Note that the aspect in which the channel layer is formed with an excessive thickness and then the thickness is reduced is that the fluctuation of the thickness of the channel layer can be reduced, and the layer formed after the channel layer is excessive. It is preferable to an embodiment in which the thickness is formed and the thickness is reduced. If such an aspect is adopted in the trench gate type MOSFET, the variation in channel length in the vicinity of the trench can be reduced.

B5. Modification 5:
In the above ^embodiment, n - after forming the -GaN protrusion 30 into the drift layer ^20, n - -GaN and in contact drift layer 20, pGaN channel layer 40 as a channel layer is formed. However, after the step of forming irregularities in a layer and before the step of forming the channel layer, the same type of semiconductor layer as the layer having irregularities (for example, if the layer having irregularities is an n-type semiconductor, It is also possible to further include a step of forming an n-type semiconductor layer.

  In a mode in which different types of semiconductor layers B are grown in contact with the layer A after forming irregularities on the layer A, an n-type semiconductor donor is generated at the interface between the layers A and B due to the generation of impurity levels. There is a possibility that the concentration and the acceptor concentration of the p-type semiconductor may deviate from the target values. However, in the above aspect, the type of the semiconductor layer regrowth on the layer A with the formation of the unevenness is the same as the layer A. For this reason, the above problems do not occur at the interface. As described above, other layers can be formed between the respective layers within a range in which the functions of the respective layers formed in the above embodiment can be prevented.

B6. Modification 6:
In the above embodiment, the thickness of the pGaN channel layer 40 is reduced by dry etching. However, the processing method for reducing the thickness of the layer may be dry etching or wet etching. Further, the treatment for reducing the thickness may be performed by both dry etching and wet etching.

B7. Modification 7:
In the above embodiment, the semiconductor device including the npn junction has been described. However, the gist of the present invention can also be applied to a semiconductor device having a pnp junction.

B8. Modification 8:
As a semiconductor device to which the present invention is applied, an example of manufacturing a trench gate type MOSFET has been described in the above embodiment (see FIG. 8). However, the present invention is not limited to these examples, and a method for manufacturing a semiconductor device in which a channel layer is formed after forming a layer having unevenness, a method for manufacturing a semiconductor device in which an electrode is formed after forming a layer having unevenness, etc. Can be applied to.

1 ... Trench gate type MOSFET
2-6, 6c ... intermediate product 10 ... n-type GaN substrate 20 ... n ^-- GaN drift layer 30 ... convex part 40 ... pGaN channel layer 50 ... n ⁺ -GaN contact layer 60 ... trench 70 ... insulating film 80 ... gate electrode DESCRIPTION OF SYMBOLS 90 ... Source electrode 100 ... Drain electrode 140 ... pGaN channel layer 150 ... n ^<+>- GaN contact layer C ... The site | part in which the inversion layer of the pGaN channel layer 40 is formed L ... pGaN which separates between the convex part 30 and the contact layer 50 Thickness Lc of channel layer 40... Thickness of pGaN channel layer 140 separating convex portion 30 and contact layer 150. Rg... Region T40 where convex portion 30 is provided T. thickness T41 of pGaN channel layer 40. The thickness of the pGaN channel layer in the gate MOSFET 1 h: the dimension of the projection 30 in the z-axis direction

Claims (3)

A method of manufacturing a semiconductor device using a gallium nitride semiconductor,
(A) in the first n-type semiconductor layer provided on the substrate of the n-type semiconductor, a step of forming irregularities on the surface opposite to the substrate;
(B) forming a p-type semiconductor layer functioning as a channel layer of the semiconductor device on a side opposite to the substrate with respect to the first n-type semiconductor layer having the irregularities;
(C) etching the p-type semiconductor layer to reduce the thickness of the p-type semiconductor layer;
(D) forming a second n-type semiconductor layer on the opposite side of the etched p-type semiconductor layer from the first n-type semiconductor layer. The method of claim 1, comprising:
The method in which the step (b) is a step of forming the p-type semiconductor layer having a thickness of 400% or more of the dimension of the irregularities in the stacking direction of the layers. The method according to claim 1 or 2, comprising:
In the step (b), in the stacking direction of the respective layers, the p-type semiconductor layer is formed which has irregularities having a size of 1/10 or less of the irregularities on the surface or has no irregularities on the surface. A method of performing.

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