JP7045180B2 - Power semiconductor devices, modules and manufacturing methods - Google Patents

Power semiconductor devices, modules and manufacturing methods Download PDF

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JP7045180B2
JP7045180B2 JP2017241562A JP2017241562A JP7045180B2 JP 7045180 B2 JP7045180 B2 JP 7045180B2 JP 2017241562 A JP2017241562 A JP 2017241562A JP 2017241562 A JP2017241562 A JP 2017241562A JP 7045180 B2 JP7045180 B2 JP 7045180B2
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protective film
power semiconductor
electrode
layer
semiconductor device
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JP2019110183A (en
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直樹 櫻井
靖 池田
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Hitachi Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode

Description

本発明は、パワー半導体装置、モジュール及び製造方法に関する。 The present invention relates to power semiconductor devices, modules and manufacturing methods.

パワーエレクトロニクスの分野では、省エネルギーのため、産業、鉄道、自動車、家電、エレベータ、家電、医療等広い分野で電力変換器としてインバータの導入が進んでいる。インバータ化により、例えば、ポンプではバルブによる制御に対して、約２５％の消費電力の削減が見込まれる。また、鉄道では回生により停止時、モータのエネルギーを架線に戻すことができ、約５０％消費電力を削減できる。 In the field of power electronics, in order to save energy, inverters are being introduced as power converters in a wide range of fields such as industry, railways, automobiles, home appliances, elevators, home appliances, and medical care. By using an inverter, for example, in a pump, power consumption is expected to be reduced by about 25% compared to control by a valve. In addition, in railways, the energy of the motor can be returned to the overhead line when stopped by regeneration, and power consumption can be reduced by about 50%.

インバータの普及に当たっては、キーとなるパワーデバイスの発展が大きな役割を果たしてきた。すなわち、サイリスタ、ゲートターンオフサイリスタ、バイポーラトランジスタ、絶縁ゲートバイポーラトランジスタ（Insulated Gate Bipolar Transistor、以下IGBTと呼ぶ）と発展するに従い、パワーデバイスは、低損失化とともに、高周波でのスイッチングが可能になるとともに、IGBTではバイポーラトランジスタまでの電流制御から電圧制御になりCPUによる制御性が向上した。さらに破壊しにくくなり、初期のインバータが数ｋW程度であったのに対して、現在では数10MWのインバータも実現可能になっている。 The development of key power devices has played a major role in the spread of inverters. That is, with the development of thyristors, gate turn-off thyristors, bipolar transistors, and insulated gate bipolar transistors (hereinafter referred to as IGBTs), power devices have become possible to switch at high frequencies while reducing losses. In the IGBT, the controllability by the CPU has been improved by changing from the current control up to the bipolar transistor to the voltage control. It is even more difficult to destroy, and while the initial inverter was about several kW, it is now possible to realize an inverter with several tens of MW.

パワーデバイスとしては、パワーMOSFET（Metal Oxide Semiconductor Field Effect Transistor）がある。しかしながら、シリコンは抵抗が高いため、特に600V以上では、伝導度変調によりオン時の抵抗を下げられるサイリスタ、ゲートターンオフサイリスタ、バイポーラトランジスタ、IGBTが用いられてきた。これに対して、近年シリコンカーバイト(Silicon Carbide、以下SiCと呼ぶ)を用いたパワーデバイスが製品化されてきた。SiCは絶縁破壊電圧Eｃが１ケタ高く、耐圧を確保するためのチップの厚さを薄くできるとともに、不純物濃度を高くすることができる。このため、シリコンではオン抵抗が大きく実用的ではない耐圧600Vから6500Vまでの範囲で、SiCを使ったパワーMOSFETが開発されている。 As a power device, there is a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor). However, since silicon has a high resistance, thyristors, gate turn-off thyristors, bipolar transistors, and IGBTs, which can reduce the resistance when turned on by conductivity modulation, have been used, especially at 600 V or higher. On the other hand, in recent years, power devices using Silicon Carbide (hereinafter referred to as SiC) have been commercialized. SiC has a breakdown voltage Ec that is one digit higher, and the thickness of the chip for ensuring the withstand voltage can be reduced and the impurity concentration can be increased. For this reason, power MOSFETs using SiC have been developed in the range of withstand voltage of 600V to 6500V, which is not practical because of the large on-resistance of silicon.

パワーデバイスの進歩に合わせて小型化、低コスト化のために冷却技術も進歩して来ている。特に水冷は放熱能力が高く、小型化が必須な電気自動車やハイブリッド自動車に広く使われている。当初は、水に浸かる冷却フィンとパワーデバイスを実装したモジュール間を放熱グリスで接着し、冷却フィンとモジュールをボルト締めにより固定していた。次に、モジュールの底面を冷却フィンとする直接冷却方式が開発された。直接冷却方式では、放熱グリスがなくなるため熱抵抗が下がるという利点がある。この直接冷却方式をモジュールの上下に施したのが両面冷却モジュールである。両面冷却もモジュールは、片面冷却に比べ熱抵抗を半減できる。 With the progress of power devices, cooling technology is also advancing in order to reduce the size and cost. In particular, water cooling has a high heat dissipation capacity and is widely used in electric vehicles and hybrid vehicles that require miniaturization. Initially, the cooling fins soaked in water and the module on which the power device was mounted were glued together with thermal paste, and the cooling fins and the module were fixed by bolting. Next, a direct cooling method was developed in which the bottom surface of the module was used as a cooling fin. The direct cooling method has an advantage that the thermal resistance is lowered because the thermal paste is eliminated. The double-sided cooling module applies this direct cooling method to the top and bottom of the module. For double-sided cooling, the module can reduce the thermal resistance by half compared to single-sided cooling.

ここで、熱変化によって生じる応力により半導体素子が破壊されることを防止できるモールド型半導体装置が知られている（例えば、特許文献１参照）。特許文献１には、「ＩＧＢＴが形成された半導体チップの表面に、Ａｌ合金からなる第１金属層、Ｎｉからなる第２金属層、Ａｕからなる第３金属層を形成することでエミッタ電極を形成し、エミッタ電極の上にはんだを形成してなるモールド型パワーデバイスにおいて、はんだの降伏応力が少なくとも第１金属層の降伏応力よりも小さくなるようにする。」と記載されている。 Here, a molded semiconductor device capable of preventing a semiconductor element from being destroyed by stress generated by a thermal change is known (see, for example, Patent Document 1). In Patent Document 1, "an emitter electrode is formed by forming a first metal layer made of an Al alloy, a second metal layer made of Ni, and a third metal layer made of Au on the surface of a semiconductor chip on which an IGBT is formed. In a molded power device formed and solder formed on an emitter electrode, the yield stress of the solder should be at least smaller than the yield stress of the first metal layer. "

特開2005-19447号公報Japanese Unexamined Patent Publication No. 2005-19447

ところで、最近、特に自動車では、はんだに鉛を含まないこと（鉛フリー）が求められている。普及している鉛フリーはんだはアルミ電極より降伏応力が大きい。そのため、普及している鉛フリーはんだのままでは、特許文献１に開示された技術を適用できず、特殊な鉛フリーはんだを開発する必要がある。 By the way, recently, especially in automobiles, it is required that the solder does not contain lead (lead-free). Popular lead-free solder has a higher yield stress than aluminum electrodes. Therefore, the technique disclosed in Patent Document 1 cannot be applied with the widely used lead-free solder as it is, and it is necessary to develop a special lead-free solder.

本発明の目的は、はんだ材料にかかわらず熱応力による破壊を防止することができるパワー半導体装置等を提供することにある。 An object of the present invention is to provide a power semiconductor device or the like capable of preventing fracture due to thermal stress regardless of the solder material.

上記目的を達成するために、本発明は、パワー半導体素子と、はんだ材と、前記はんだ材を介して前記パワー半導体素子と電気的に接続される導体と、を備え、前記パワー半導体素子は、一方の面に設けられる制御電極及び第１のアルミ電極と、他方の面に設けられる第２のアルミ電極と、前記第１のアルミ電極を覆うＮｉ層と、前記制御電極を覆う第１の保護膜と、を有し、前記Ｎｉ層及び第１のアルミ電極は、前記第１の保護膜から離れているパワー半導体装置であって、前記パワー半導体素子は、前記第１の保護膜を覆う第２の保護膜を有し、前記Ｎｉ層は、前記第２の保護膜を挟んで前記第１の保護膜と対向する。 In order to achieve the above object, the present invention comprises a power semiconductor element, a solder material, and a conductor electrically connected to the power semiconductor element via the solder material. A control electrode and a first aluminum electrode provided on one surface, a second aluminum electrode provided on the other surface, a Ni layer covering the first aluminum electrode, and a first protection covering the control electrode. A power semiconductor device having a film, the Ni layer and the first aluminum electrode being separated from the first protective film, and the power semiconductor element covering the first protective film. It has 2 protective films, and the Ni layer faces the 1st protective film with the 2nd protective film interposed therebetween .

本発明によれば、はんだ材料にかかわらず熱応力による破壊を防止することができる。上記した以外の課題、構成及び効果は、以下の実施形態の説明により明らかにされる。 According to the present invention, it is possible to prevent fracture due to thermal stress regardless of the solder material. Issues, configurations and effects other than those described above will be clarified by the following description of the embodiments.

比較例によるＩＧＢＴの構成図である。It is a block diagram of the IGBT by the comparative example. 本発明の第１の実施形態によるＩＧＢＴの構成図である。It is a block diagram of the IGBT according to the 1st Embodiment of this invention. 本発明の第１実施形態によるＩＧＢＴの製造方法を示す図である。It is a figure which shows the manufacturing method of the IGBT by 1st Embodiment of this invention. 本発明の第２の実施形態によるＩＧＢＴの構成図である。It is a block diagram of the IGBT by the 2nd Embodiment of this invention. 本発明の第２実施形態によるＩＧＢＴの製造方法を示す図である。It is a figure which shows the manufacturing method of the IGBT by the 2nd Embodiment of this invention. 本発明を適用したＩＧＢＴモジュールの平面図である。It is a top view of the IGBT module to which this invention is applied. 図６Ａに示すＩＧＢＴモジュールの断面図である。It is sectional drawing of the IGBT module shown in FIG. 6A.

以下、図面を用いて、本発明の第1～第２の実施形態によるパワー半導体装置の構成を説明する。なお、各図において、同一符号は同一部分を示す。 Hereinafter, the configuration of the power semiconductor device according to the first and second embodiments of the present invention will be described with reference to the drawings. In each figure, the same reference numerals indicate the same parts.

（比較例）
初めに、図1を用いて、比較例に係るパワー半導体装置（パワーデバイス）の構成を説明する。図1は、パワー半導体装置としての絶縁ゲートバイポーラトランジスタ（Insulated Gate Bipolar Transistor、以下IGBTを称す）の両面冷却モジュールの断面を示す。詳細には、断面は、ゲート電極（ゲート配線）とアルミ電極（エミッタ電極）間の領域を示す。 (Comparative example)
First, the configuration of a power semiconductor device (power device) according to a comparative example will be described with reference to FIG. FIG. 1 shows a cross section of a double-sided cooling module of an insulated gate bipolar transistor (hereinafter referred to as an IGBT) as a power semiconductor device. In detail, the cross section shows the region between the gate electrode (gate wiring) and the aluminum electrode (emitter electrode).

IGBTはトレンチゲート構造で示している。IGBTチップ裏面には、アルミ電極さらにNi電極が設けられている。銅のコレクタ電極はチップのNi電極とはんだで接続されている。表面エミッタ側は裏面と同様に、アルミ電極さらにNi電極が設けられ、エミッタ電極とはんだで接続されている。ゲート電極は酸化膜上に形成され絶縁膜として、ポリイミドで覆われている。 The IGBT is shown by a trench gate structure. An aluminum electrode and a Ni electrode are provided on the back surface of the IGBT chip. The copper collector electrode is soldered to the Ni electrode of the chip. Similar to the back surface, the front emitter side is provided with an aluminum electrode and a Ni electrode, and is connected to the emitter electrode by soldering. The gate electrode is formed on an oxide film and is covered with polyimide as an insulating film.

図１でアルミ電極（エミッタ電極）上に形成されたNi電極はポリイミドと接している。ところで、IGBTを動作させると自己発熱によりIGBTチップの温度が上下する。各材料は熱膨張係数が違うため、熱応力が発生する。この温度変化が繰り返される（温度サイクル）とNi電極はポリイミドが接触しているところに熱応力の集中点が発生する。この熱応力によりアルミ電極（エミッタ電極）に亀裂（アルミクラック）が入りそこから表面側はんだが進入する。温度変化の回数の増加とともに、半田の進入距離も長くなり、最後にはゲート電極に達する。はんだがゲート電極に達するとゲートとエミッタが短絡しIGBTはオンできなり故障にいたる。 In FIG. 1, the Ni electrode formed on the aluminum electrode (emitter electrode) is in contact with the polyimide. By the way, when the IGBT is operated, the temperature of the IGBT chip rises and falls due to self-heating. Since each material has a different coefficient of thermal expansion, thermal stress is generated. When this temperature change is repeated (temperature cycle), a concentration point of thermal stress is generated at the place where the polyimide is in contact with the Ni electrode. Due to this thermal stress, cracks (aluminum cracks) are formed in the aluminum electrode (emitter electrode), and the surface side solder enters from there. As the number of temperature changes increases, the solder entry distance also increases, eventually reaching the gate electrode. When the solder reaches the gate electrode, the gate and emitter are short-circuited and the IGBT can be turned on, resulting in failure.

（第1の実施形態）
本発明の第1の実施形態によるＩＧＢＴを図２に示す。ｎ－層１の裏面（図２の下側）にはＡＬ（アルミ）電極層２０が形成されさらにその裏面にはＮｉ層２１が形成されている。Ｎｉ層２１裏面には半田２２が形成されコレクタ電極１００と接続されている。 (First embodiment)
The IGBT according to the first embodiment of the present invention is shown in FIG. An AL (aluminum) electrode layer 20 is formed on the back surface (lower side of FIG. 2) of the n- layer 1, and a Ni layer 21 is further formed on the back surface thereof. A solder 22 is formed on the back surface of the Ni layer 21 and is connected to the collector electrode 100.

基板中、裏面側にはｎ層２、ｐ＋層３が設けられＩＧＢＴのコレクタ層を形成している。ｎ－層1の表面側には溝状のトレンチゲートが形成されている。トレンチゲートは、トレンチゲート表面に形成されたゲート酸化膜１０と、トレンチを充填しているゲート電極材料であるポリシリコン１１で構成されている。トレンチゲートは複数設けられ、その間にはｐ層４が設けられている。ｐ層４中にはｎ＋層６が設けられている。ｐ層４がチャネル層、ｎ＋層６がエミッタ層それとトレンチゲートによりＭＯＳ（Metal Oxide Semiconductor）構造を形成している。この表面側のＭＯＳ構造と裏面側コレクタｎ層２、ｐ＋層３によりＩＧＢＴが形成されている。 In the substrate, the n layer 2 and the p + layer 3 are provided on the back surface side to form the collector layer of the IGBT. A groove-shaped trench gate is formed on the surface side of the n-layer 1. The trench gate is composed of a gate oxide film 10 formed on the surface of the trench gate and polysilicon 11, which is a gate electrode material that fills the trench. A plurality of trench gates are provided, and a p layer 4 is provided between them. An n + layer 6 is provided in the p layer 4. The p layer 4 is a channel layer, the n + layer 6 is an emitter layer, and a trench gate forms a MOS (Metal Oxide Semiconductor) structure. The IGBT is formed by the MOS structure on the front surface side, the collector n layer 2 on the back surface side, and the p + layer 3.

ｐ＋層５が、反転層が形成されないｐ層４の不純物濃度をあげ、抵抗率を下げることで、ＩＧＢＴの寄生サイリスタ動作を防止するため設けられている。ｎ－層1表面には酸化膜３０ａ、３０ｂが設けられている。酸化膜３０ａにはコンタクト３１が設けられている。コンタクト３１を通じてエミッタＡＬ（アルミ）電極２４とｐ＋層５及びｎ＋層６が接触している。エミッタＡＬ電極２４上には、Ｎｉめっき２５が形成されている。Ｎｉめっき層２５上には半田２７が設けられさらにその上に形成された裏面電極１０１と接続している。 The p + layer 5 is provided in order to prevent the parasitic thyristor operation of the IGBT by increasing the impurity concentration of the p layer 4 in which the inversion layer is not formed and lowering the resistivity. The oxide films 30a and 30b are provided on the surface of the n-layer 1. The oxide film 30a is provided with a contact 31. The emitter AL (aluminum) electrode 24 is in contact with the p + layer 5 and the n + layer 6 through the contact 31. Ni plating 25 is formed on the emitter AL electrode 24. A solder 27 is provided on the Ni plating layer 25 and is further connected to a back surface electrode 101 formed on the solder 27.

すなわち、パワー半導体装置は、ＩＧＢＴ（パワー半導体素子）と、半田２７（はんだ材）を介してＩＧＢＴと電気的に接続される裏面電極１０１（導体）と、を備える。 That is, the power semiconductor device includes an IGBT (power semiconductor element) and a back surface electrode 101 (conductor) that is electrically connected to the IGBT via a solder 27 (solder material).

チップにはＩＧＢＴの他にゲートに電圧を与えるゲート配線ＡＬ電極２６が形成されている。ゲート配線ＡＬ電極２６は、ｎ－層1基板中に形成されたｐ－ＷＥＬＬ層７、さらにその上の酸化膜３０ｂ上に形成されている。ｐ－ＷＥＬＬ層７は図には示されていないゲート酸化膜３０ｂのコンタクト穴を通じてエミッタ電極２４と接続されている。ｐ－ＷＥＬＬ層７をエミッタ電位とすることで、ゲートに加わる電位を安定させている。 In addition to the IGBT, the chip is formed with a gate wiring AL electrode 26 that applies a voltage to the gate. The gate wiring AL electrode 26 is formed on the p-WELL layer 7 formed in the n-layer 1 substrate, and further on the oxide film 30b on the p-WELL layer 7. The p-WELL layer 7 is connected to the emitter electrode 24 through a contact hole of the gate oxide film 30b (not shown in the figure). By using the p-WELL layer 7 as the emitter potential, the potential applied to the gate is stabilized.

ゲート配線ＡＬ電極２６はポリイミドなどの保護膜２８で覆われている。保護膜２８は、ゲート配線ＡＬ電極２６に使われているアルミが、外部から侵入した水分により腐食するのを防止する。また、半田２７が表面全面を覆うため、エミッタとゲートを絶縁するという役割も果している。 The gate wiring AL electrode 26 is covered with a protective film 28 such as polyimide. The protective film 28 prevents the aluminum used for the gate wiring AL electrode 26 from being corroded by moisture that has entered from the outside. Further, since the solder 27 covers the entire surface, it also plays a role of insulating the emitter and the gate.

このように、ゲート配線ＡＬ電極２６（制御電極）及びエミッタＡＬ電極２４（第１のアルミ電極）は、ＩＧＢＴ（パワー半導体素子）の一方の面（図２の上側面）に設けられ、ＡＬ電極層２０（第２のアルミ電極）は、他方の面（図２の下側面）に設けられる。Ｎｉめっき層２５（Ｎｉ層）は、エミッタＡＬ電極２４を覆う。保護膜２８（第１の保護膜）は、ゲート配線ＡＬ電極２６（制御電極）を覆う。 As described above, the gate wiring AL electrode 26 (control electrode) and the emitter AL electrode 24 (first aluminum electrode) are provided on one surface (upper side surface of FIG. 2) of the IGBT (power semiconductor element), and the AL electrode. The layer 20 (second aluminum electrode) is provided on the other surface (lower side surface of FIG. 2). The Ni plating layer 25 (Ni layer) covers the emitter AL electrode 24. The protective film 28 (first protective film) covers the gate wiring AL electrode 26 (control electrode).

なお、本実施形態では、ＡＬ電極層２０は、ＡＬ電極２４より高電位に接続される。つまり、ＡＬ電極層２０は、相対的に高電位であり、ＡＬ電極２４は相対的に低電位である。これにより、ゲート配線ＡＬ電極２６（制御電極）に供給される制御信号に応じて、ＡＬ電極層２０からＡＬ電極２４へ電流が流れる。 In this embodiment, the AL electrode layer 20 is connected to a higher potential than the AL electrode 24. That is, the AL electrode layer 20 has a relatively high potential, and the AL electrode 24 has a relatively low potential. As a result, a current flows from the AL electrode layer 20 to the AL electrode 24 according to the control signal supplied to the gate wiring AL electrode 26 (control electrode).

本発明の実施形態では、保護膜２８とＮｉめっき層２５の間にも半田２７が形成されている。これにより、Ｎｉ層と保護膜が接触することを回避できるため、Ni層と保護膜の界面に発生する熱応力集中点を排除し、アルミ電極に亀裂が入るのを防止できるため、特殊な半田を使うことなく高信頼な両面冷却モジュールが実現できる。 In the embodiment of the present invention, the solder 27 is also formed between the protective film 28 and the Ni plating layer 25. As a result, it is possible to prevent the Ni layer from coming into contact with the protective film, eliminating the thermal stress concentration point generated at the interface between the Ni layer and the protective film, and preventing cracks from forming in the aluminum electrode. A highly reliable double-sided cooling module can be realized without using.

換言すれば、Ｎｉめっき層２５（Ｎｉ層）及びエミッタＡＬ電極２４（第１のアルミ電極）は、保護膜２８（第１の保護膜）から離れている。詳細には、Ｎｉめっき層２５（Ｎｉ層）とゲート配線ＡＬ電極２６（制御電極）との間において、Ｎｉめっき層２５は、半田２７（はんだ材）を挟んで保護膜２８（第１の保護膜）と対向する。これにより、Ｎｉめっき層２５と保護膜２８による熱応力集中点が排除される。 In other words, the Ni plating layer 25 (Ni layer) and the emitter AL electrode 24 (first aluminum electrode) are separated from the protective film 28 (first protective film). Specifically, between the Ni plating layer 25 (Ni layer) and the gate wiring AL electrode 26 (control electrode), the Ni plating layer 25 sandwiches the solder 27 (solder material) and protects the protective film 28 (first protection). Facing the membrane). As a result, the thermal stress concentration point due to the Ni plating layer 25 and the protective film 28 is eliminated.

図３に本発明の第1実施形態によるＩＧＢＴの製造方法を示す。（Ｓ１）では、表面ＡＬ電極を形成する。（Ｓ２）では、表面ＡＬ電極にホトレジスト６０を塗布し、図2には示していないホトマスク及び露光装置を用いたフォトリソグラフィにより、表面ＡＬ電極のうちエミッタＡＬ電極２４とゲート配線ＡＬ電極２６となる領域のみレジスト６０を残す。（Ｓ３）では、表面ＡＬ電極をエッチングし、エミッタＡＬ電極２４とゲート配線ＡＬ電極２６を形成する。 FIG. 3 shows a method for manufacturing an IGBT according to the first embodiment of the present invention. In (S1), a surface AL electrode is formed. In (S2), the photoresist 60 is applied to the surface AL electrode, and the emitter AL electrode 24 and the gate wiring AL electrode 26 of the surface AL electrodes are obtained by photolithography using a photomask and an exposure device (not shown in FIG. 2). The resist 60 is left only in the area. In (S3), the surface AL electrode is etched to form the emitter AL electrode 24 and the gate wiring AL electrode 26.

（Ｓ４）では、保護膜を形成し、（Ｓ５）では、保護膜ホトにより、ゲート配線ＡＬ電極２６の保護膜２８となる領域のみホトマスク及び露光装置によりレジスト６１を残す。（Ｓ６）では、保護膜をエッチングし保護膜２８を形成する。（Ｓ７）では、Ｎｉめっきを行う。このとき、無電解めっきを使うことで、Ｎｉめっき層２５はめっき液と触れる部分しか形成されない、すなわちエミッタＡＬ電極２４上にしか形成されない。（Ｓ８）では、半田層を塗布あるいはシート状の半田を置きリフローすることで形成する。 In (S4), a protective film is formed, and in (S5), the protective film photo leaves the resist 61 only in the region serving as the protective film 28 of the gate wiring AL electrode 26 by the photomask and the exposure apparatus. In (S6), the protective film is etched to form the protective film 28. In (S7), Ni plating is performed. At this time, by using electroless plating, the Ni plating layer 25 is formed only on the portion that comes into contact with the plating solution, that is, is formed only on the emitter AL electrode 24. In (S8), the solder layer is applied or a sheet-like solder is placed and reflowed to form the solder layer.

（Ｓ２）及び（Ｓ５）のホト工程において、図３でＡ－Ａ‘で示したエミッタＡＬ電極２４形成用のホトレジストの開口部は、Ｂ－Ｂ‘で示した保護膜２８形成用のレジスト６１よりも広く形成されている。これにより、保護膜２８とＮｉめっき層２５に隙間ができる。その後、（Ｓ８）の半田形成時に、この保護膜２８とＮｉめっき層２５間のすきまに半田が入り込み、図1で示した本発明の第1の実施形態を形成することができる。 In the photo steps of (S2) and (S5), the opening of the photoresist for forming the emitter AL electrode 24 shown by AA in FIG. 3 is the resist 61 for forming the protective film 28 shown by BB'. Is formed wider than. As a result, a gap is formed between the protective film 28 and the Ni plating layer 25. After that, when the solder is formed in (S8), the solder enters the gap between the protective film 28 and the Ni plating layer 25, and the first embodiment of the present invention shown in FIG. 1 can be formed.

以上説明したように、本実施形態によれば、はんだ材料にかかわらず熱応力による破壊を防止することができる。 As described above, according to the present embodiment, it is possible to prevent fracture due to thermal stress regardless of the solder material.

（第２の実施形態）
図４は本発明の第２の実施形態によるＩＧＢＴを示す。ゲート配線ＡＬ電極２６は、保護膜２８さらに半田２７より硬度が低く保護膜２８より硬度が高いレジンなどの第２の保護膜５０で覆われている。保護膜５０は、保護膜２８とＮｉめっき層２５間にも形成されている。 (Second embodiment)
FIG. 4 shows an IGBT according to the second embodiment of the present invention. The gate wiring AL electrode 26 is covered with a second protective film 50 such as a resin having a hardness lower than that of the solder 27 and a hardness higher than that of the protective film 28. The protective film 50 is also formed between the protective film 28 and the Ni plating layer 25.

換言すれば、ＩＧＢＴ（パワー半導体素子）は、保護膜２８（第１の保護膜）を覆う保護膜５０（第２の保護膜）を有する。Ｎｉめっき層２５（Ｎｉ層）は、保護膜５０を挟んで保護膜２８と対向する。これより、Ｎｉめっき層２５と保護膜２８による熱応力集中点が排除される。 In other words, the IGBT (power semiconductor element) has a protective film 50 (second protective film) that covers the protective film 28 (first protective film). The Ni plating layer 25 (Ni layer) faces the protective film 28 with the protective film 50 interposed therebetween. As a result, the thermal stress concentration points due to the Ni plating layer 25 and the protective film 28 are eliminated.

さらに、本実施形態では、半田２７より硬度が低い第２の保護膜５０と保護膜２８が接触するため、保護膜端部の応力を下げることができる。これにより、第１の実施形態よりも大きい温度差が発生するような使用環境でもアルミ電極に亀裂が入るのを防止できる。 Further, in the present embodiment, since the second protective film 50 having a hardness lower than that of the solder 27 comes into contact with the protective film 28, the stress at the end of the protective film can be reduced. This makes it possible to prevent the aluminum electrode from cracking even in a usage environment where a temperature difference larger than that of the first embodiment is generated.

詳細には、第２の保護膜５０は、半田２７（はんだ材）より硬度が低くかつ保護膜２８（第１の保護膜）より硬度が高い。これにより、第２の保護膜５０が熱応力に対するクッションとして機能する。 Specifically, the second protective film 50 has a lower hardness than the solder 27 (solder material) and a higher hardness than the protective film 28 (first protective film). As a result, the second protective film 50 functions as a cushion against thermal stress.

図５に本発明の第２の実施形態によるＩＧＢＴの製造方法を示す。（Ｓ１）の表面ＡＬ電極形成から（Ｓ６）の保護膜エッチングまでは、図３に本発明の第1実施形態の製造方法と同じである。（Ｓ７０）では、第２の保護膜を形成し、（Ｓ８０）では、第２の保護膜ホトにより、保護膜２８を覆う第２の保護膜５０となる領域のみホトマスク及び露光装置を用いたフォトリソグラフィによりレジスト６２を残す。（Ｓ９０）では、第２の保護膜をエッチングし保護膜２８を覆う第２の保護膜５０を形成する。フォトリソグラフィ（Ｓ８０）及びエッチング（Ｓ９０）により第２の保護膜５０を高精度に形成できる。以降Ｎｉめっき形成以降は、図３で示した本発明の第1実施形態の製造方法と同じである。 FIG. 5 shows a method for manufacturing an IGBT according to the second embodiment of the present invention. From the formation of the surface AL electrode in (S1) to the etching of the protective film in (S6), FIG. 3 shows the same manufacturing method as that of the first embodiment of the present invention. In (S70), a second protective film is formed, and in (S80), only the region to be the second protective film 50 that covers the protective film 28 by the second protective film photo is used as a photo using a photomask and an exposure apparatus. The resist 62 is left by lithography. In (S90), the second protective film is etched to form the second protective film 50 that covers the protective film 28. The second protective film 50 can be formed with high accuracy by photolithography (S80) and etching (S90). After that, after Ni plating is formed, it is the same as the manufacturing method of the first embodiment of the present invention shown in FIG.

（Ｓ２）及び（Ｓ５）のホト工程において、図５でＡ－Ａ‘で示したエミッタＡＬ電極２４形成用のホトレジストの開口部は、Ｂ－Ｂ‘で示した保護膜２８形成用のレジスト６１よりも広く形成されている。さらに、（Ｓ８０）の第２の保護膜ホトでは、Ｃ－Ｃ‘で示した第２の保護膜５０形成用のレジスト６２はＢ－Ｂ‘で示した保護膜２８形成用のレジスト６１よりも広く形成されている。これにより、保護膜２８は第２の保護膜５０で覆われる。その後、半田形成時に、この第２の保護膜５０とＮｉめっき層２５間のすきまに半田が入り込み図４で示した本発明の第２の実施形態を形成することができる。 In the photo steps of (S2) and (S5), the opening of the photoresist for forming the emitter AL electrode 24 shown by AA in FIG. 5 is the resist 61 for forming the protective film 28 shown by BB'. Is formed wider than. Further, in the second protective film photo of (S80), the resist 62 for forming the second protective film 50 indicated by CC'is higher than the resist 61 for forming the protective film 28 indicated by BB'. Widely formed. As a result, the protective film 28 is covered with the second protective film 50. After that, at the time of solder formation, the solder enters the gap between the second protective film 50 and the Ni plating layer 25, and the second embodiment of the present invention shown in FIG. 4 can be formed.

図６Ａ、６Ｂは本発明の第１あるいは第２の実施形態を適用したＩＧＢＴモジュールの実施形態を示す。図６Ａは平面図である。上下アームが１つのパッケージに実装された２ｉｎ１で示している。金属ケース１１０には、冷却用の柱状のフィン１１１が複数設けられている。すなわち、ＩＧＢＴモジュール（モジュール）は、パワー半導体装置を収納する金属ケース１１０（ケース）を備える。金属ケース１１０の表面及び裏面には、放熱用のフィンが設けられている。これより冷却性能が向上する。 6A and 6B show an embodiment of an IGBT module to which the first or second embodiment of the present invention is applied. FIG. 6A is a plan view. The upper and lower arms are shown as 2in1 mounted in one package. The metal case 110 is provided with a plurality of columnar fins 111 for cooling. That is, the IGBT module (module) includes a metal case 110 (case) for accommodating the power semiconductor device. Fins for heat dissipation are provided on the front surface and the back surface of the metal case 110. This improves cooling performance.

ＩＧＢＴモジュールは端子として、出力端子１２０、高電圧側端子１２１、低電圧側端子１２２、上アームエミッタ補助端子１２３ａ、下アームエミッタ補助端子１２３ｂ、上アームゲート端子１２４ａ、下アームゲート端子１２４ｂを有する。金属ケース１１０からの各端子の取り出し部には、樹脂などの補強材１０５が設けられている。 The IGBT module has an output terminal 120, a high voltage side terminal 121, a low voltage side terminal 122, an upper arm emitter auxiliary terminal 123a, a lower arm emitter auxiliary terminal 123b, an upper arm gate terminal 124a, and a lower arm gate terminal 124b as terminals. A reinforcing material 105 such as resin is provided at a portion where each terminal is taken out from the metal case 110.

図６Ｂは、図６Ａに示す平面図のＡ－Ａ‘断面図である。ＩＧＢＴチップ２００及びダイオードチップ２０１の表面側は半田２８ａ及び半田２８ｂにより低電圧側端子１２２と接続されている。低電圧側端子１２２は絶縁シート１３０ａを介して接着剤１５０により金属ケース１１０と接続している。ＩＧＢＴチップ２００及びダイオードチップ２０１の裏面側は半田２２ａ及び半田２２ｂにより出力端子１２０と接続されている。出力端子１２０は絶縁シート１３０ｂを介して接着剤１５０により金属ケース１１０と接続している。 FIG. 6B is a cross-sectional view taken along the line AA'shown in FIG. 6A. The surface side of the IGBT chip 200 and the diode chip 201 is connected to the low voltage side terminal 122 by the solder 28a and the solder 28b. The low voltage side terminal 122 is connected to the metal case 110 by the adhesive 150 via the insulating sheet 130a. The back surface side of the IGBT chip 200 and the diode chip 201 is connected to the output terminal 120 by the solder 22a and the solder 22b. The output terminal 120 is connected to the metal case 110 by an adhesive 150 via an insulating sheet 130b.

また、ＩＧＢＴチップ２００及びダイオードチップ２０１及び出力端子１２０、高電圧側端子１２１、低電圧側端子１２２、上アームエミッタ補助端子１２３ａ、下アームエミッタ補助端子１２３ｂ、上アームゲート端子１２４ａ、下アームゲート端子１２４ｂはレジン１４０でモールドされている。モールドされたレジン１４０は接着剤１５０を介して金属ケース１１０と接続している。本実施形態では、冷却フィンが上下に設けられているため、冷却フィンが裏面のみに設けられているＩＧＢＴモジュールに比べて冷却能力が高く、より大きな電流すなわち大きな出力を得ることができる。また、本発明を適用することで、より大きな温度変化に対しても信頼性が保障できるＩＧＢＴモジュールを提供することができる。 Further, the IGBT chip 200, the diode chip 201, the output terminal 120, the high voltage side terminal 121, the low voltage side terminal 122, the upper arm emitter auxiliary terminal 123a, the lower arm emitter auxiliary terminal 123b, the upper arm gate terminal 124a, and the lower arm gate terminal. The 124b is molded with the resin 140. The molded resin 140 is connected to the metal case 110 via an adhesive 150. In the present embodiment, since the cooling fins are provided on the upper and lower sides, the cooling capacity is higher than that of the IGBT module in which the cooling fins are provided only on the back surface, and a larger current, that is, a larger output can be obtained. Further, by applying the present invention, it is possible to provide an IGBT module whose reliability can be guaranteed even with a larger temperature change.

なお、本発明は上記した実施形態に限定されるものではなく、様々な変形例が含まれる。例えば、上述した実施形態は本発明を分かりやすく説明するために詳細に説明したものであり、必ずしも説明した全ての構成を備えるものに限定されるものではない。また、ある実施形態の構成の一部を他の実施形態の構成に置き換えることが可能であり、また、ある実施形態の構成に他の実施形態の構成を加えることも可能である。また、各実施形態の構成の一部について、他の構成の追加・削除・置換をすることが可能である。 The present invention is not limited to the above-described embodiment, and includes various modifications. For example, the above-described embodiment has been described in detail in order to explain the present invention in an easy-to-understand manner, and is not necessarily limited to the one including all the described configurations. Further, it is possible to replace a part of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add the configuration of another embodiment to the configuration of one embodiment. Further, it is possible to add / delete / replace a part of the configuration of each embodiment with another configuration.

上記実施形態ではＩＧＢＴで説明したが、ソース及びドレイン電極がはんだで接合されるパワーＭＯＳＦＥＴでも同じ効果が得られる。 In the above embodiment, the IGBT has been described, but the same effect can be obtained with a power MOSFET in which the source and drain electrodes are joined by soldering.

上記実施形態では、一例としてＮチャネルＩＧＢＴに本発明を適用したが、ＰチャネルＩＧＢＴに適用してもよい。つまり、極性を逆にしてもよい。 In the above embodiment, the present invention is applied to the N-channel IGBT as an example, but the present invention may be applied to the P-channel IGBT. That is, the polarity may be reversed.

１：ｎ－層
２：ｎ層
３：ｐ＋層
４：ｐ層
５：ｐ＋層
６：ｎ＋層
７：ｐ－ＷＥＬＬ層
１０：ゲート酸化膜
１１：ポリシリコン
２０：ＡＬ（アルミ）電極層２０
２１：Ｎｉ層２１
２２：半田
２４：エミッタＡＬ（アルミ）電極
２５：Ｎｉめっき層
２６：ゲート配線ＡＬ電極
２７：半田
２８：保護膜
３０：酸化膜
３１：コンタクト
５０：第２の保護膜
１００：コレクタ電極
１０１：裏面電極
１０５：補強材
１２０：出力端子
１２１：高電圧側端子
１２２：低電圧側端子
１２３：エミッタ補助端子
１２４：ゲート端子
１３０：絶縁シート
１４０：レジンモールド
１５０：接着剤 1: n-layer 2: n layer 3: p + layer 4: p layer 5: p + layer 6: n + layer 7: p-WELL layer 10: gate oxide film 11: polysilicon 20: AL (aluminum) electrode layer 20
21: Ni layer 21
22: Solder 24: Emitter AL (aluminum) electrode 25: Ni plating layer 26: Gate wiring AL electrode 27: Solder 28: Protective film 30: Oxidized film 31: Contact 50: Second protective film 100: Collector electrode 101: Back surface Electrode 105: Reinforcing material 120: Output terminal 121: High voltage side terminal 122: Low voltage side terminal 123: Emitter auxiliary terminal 124: Gate terminal 130: Insulation sheet 140: Resin mold 150: Adhesive

Claims (7)

パワー半導体素子と、はんだ材と、前記はんだ材を介して前記パワー半導体素子と電気的に接続される導体と、を備え、前記パワー半導体素子は、一方の面に設けられる制御電極及び第１のアルミ電極と、他方の面に設けられる第２のアルミ電極と、前記第１のアルミ電極を覆うＮｉ層と、前記制御電極を覆う第１の保護膜と、を有し、前記Ｎｉ層及び第１のアルミ電極は、前記第１の保護膜から離れているパワー半導体装置であって、
前記パワー半導体素子は、前記第１の保護膜を覆う第２の保護膜を有し、
前記Ｎｉ層は、前記第２の保護膜を挟んで前記第１の保護膜と対向する
ことを特徴とするパワー半導体装置。 A power semiconductor element, a solder material, and a conductor electrically connected to the power semiconductor element via the solder material are provided, and the power semiconductor element includes a control electrode provided on one surface and a first surface. It has an aluminum electrode, a second aluminum electrode provided on the other surface, a Ni layer covering the first aluminum electrode, and a first protective film covering the control electrode, and has the Ni layer and the first protective film. The aluminum electrode 1 is a power semiconductor device separated from the first protective film, and is a power semiconductor device.
The power semiconductor element has a second protective film that covers the first protective film.
The Ni layer faces the first protective film with the second protective film interposed therebetween.
A power semiconductor device characterized by this. 請求項１に記載のパワー半導体装置であって、
前記第２の保護膜は、
前記はんだ材より硬度が低くかつ前記第１の保護膜より硬度が高い
ことを特徴とするパワー半導体装置。 The power semiconductor device according to claim 1 .
The second protective film is
A power semiconductor device characterized by having a lower hardness than the solder material and a higher hardness than the first protective film. 請求項１に記載のパワー半導体装置であって、
第２のアルミ電極は、
第１のアルミ電極より高電位に接続される
ことを特徴とするパワー半導体装置。 The power semiconductor device according to claim 1.
The second aluminum electrode is
A power semiconductor device characterized in that it is connected to a higher potential than the first aluminum electrode. 請求項１に記載のパワー半導体装置を含むモジュール。 A module including the power semiconductor device according to claim 1. 請求項４に記載のモジュールであって、
前記パワー半導体装置を収納するケースを備え、
前記ケースの表面及び裏面に放熱用のフィンが設けられている
ことを特徴とするモジュール。 The module according to claim 4 .
A case for accommodating the power semiconductor device is provided.
A module characterized in that heat dissipation fins are provided on the front surface and the back surface of the case. 請求項１に記載のパワー半導体装置の製造方法であって、
前記Ｎｉ層は、
無電解めっき法により形成される
ことを特徴とする製造方法。 The method for manufacturing a power semiconductor device according to claim 1.
The Ni layer is
A manufacturing method characterized by being formed by an electroless plating method. 請求項１に記載のパワー半導体装置の製造方法であって、
前記第２の保護膜は、
フォトリソグラフィ及びエッチングにより形成される
ことを特徴とする製造方法。 The method for manufacturing a power semiconductor device according to claim 1 .
The second protective film is
A manufacturing method characterized by being formed by photolithography and etching.
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