JP4908475B2 - Semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device , and more particularly to a highly reliable high power semiconductor device made of gallium nitride (GaN) or the like.

  It is known that a field effect transistor (FET) using a gallium nitride (GaN) -based semiconductor has a large current collapse and leakage current. The cause is dislocations and crystal defects in the epitaxial crystal.

  Since crystal defects deteriorate basic performance such as increase of leakage current and occurrence of current collapse phenomenon, it is very important to obtain an epitaxial layer with few crystal defects.

  In order to reduce the dislocations and defects of this crystal, it is known to insert an aluminum gallium nitride (AlGaN) layer or an aluminum nitride (AlN) layer in the GaN layer.

  As shown in FIG. 8, the conventional semiconductor device is disposed on the AlGaN layer 14, the GaN layer 12 disposed on the substrate 10 made of SiC, the AlGaN layer 14 disposed on the GaN layer 12, and the like. A gate electrode 20, a source electrode 18, and a drain electrode 26 are provided. A source contact 18 a is disposed between the source electrode 18 and the AlGaN layer 14, and a drain contact 26 a is disposed between the drain electrode 26 and the AlGaN layer 14.

  Further, in the conventional semiconductor device, as shown in FIG. 8, an element isolation region 25 in which a part of the AlGaN layer 14 and the GaN layer 12 is formed by mesa etching is formed in the peripheral portion. An active region of the semiconductor device is defined by the element isolation region 25 formed by mesa etching. Note that an insulating layer 22 serving as a passivation film is formed on the side wall portion and active region of the element isolation region 25 formed by mesa etching, as shown in FIG.

  In addition, GaN and AlGaN or AlN have a large lattice constant difference, and electric charges are generated by piezo polarization between the GaN layer and the AlGaN layer. The electric charge generated in the GaN layer drastically reduces the high frequency characteristics of the semiconductor device. There is a problem of end.

  For example, the GaN layer 12 and the AlGaN layer 14 have a large lattice constant difference, and electric charges are generated between the GaN layer 12 and the AlGaN layer 14 due to piezoelectric polarization, and the electric charges generated in the GaN layer 12 are high-frequency characteristics of the semiconductor device. There is a problem that it drops extremely.

  Such charge due to piezo polarization increases the conductivity of the GaN layer 12, increases the leakage current between the gate electrode 20 and the source electrode 18 or between the gate electrode 20 and the drain electrode 26, and increases the power amplification gain of the semiconductor device. It causes a decrease.

  A field effect transistor using a GaN-based semiconductor that can be formed to a gate size of 0.1 μm and does not generate a leakage current between the gate electrode and the source or drain electrode and a method for manufacturing the same have already been disclosed. (For example, refer to Patent Document 1). In Patent Document 1, a gate leakage current is reduced by using a field effect transistor having a gate electrode having a T-shaped cross section.

In addition, a group III nitride semiconductor crystal, a group III nitride semiconductor substrate, a semiconductor device, and a method for manufacturing a group III nitride semiconductor crystal having a high resistance value have already been disclosed (for example, see Patent Document 2). In Patent Document 2, for example, a group III nitride semiconductor crystal to which Fe is added as a transition metal, and a Ga-doped GaN layer having a Ga atom vacancy density of 1 × 10 ¹⁶ cm ⁻³ or less is disclosed. . The Fe atom density of the Fe-doped GaN layer is 5 × 10 ¹⁷ cm ⁻³ to 10 ²⁰ cm ⁻³ . A semiconductor device having a semiconductor layer formed on a group III nitride semiconductor substrate made of the Fe-doped GaN layer is also disclosed.

  In addition, a semiconductor element that can form a plurality of nitride compound semiconductor layers having a lattice constant difference of a predetermined value or more in a multi-layered state with good crystallinity and can suppress propagation of threading dislocations in the epitaxial growth direction. It has already been disclosed (for example, see Patent Document 3).

  In a high power semiconductor device composed of a GaN layer, an AlGaN layer, and the like, there are two methods for electrically isolating elements: a method of isolating elements by ion implantation (implant isolation) and a method of isolating elements by mesa etching. There is a problem that the reliability of the element is lowered when the element is separated by the implantation isolation.

In the element isolation method by mesa etching, a step is formed in the device, so that there is a problem that it is difficult to focus when forming a wiring or the like with an exposure apparatus, and it is difficult to miniaturize.
JP 2002-141499 A (page 3-4, FIG. 1) JP 2007-184379 (page 6-7, FIGS. 4 and 5) JP 2007-22001 A (FIGS. 1, 7, and 10)

An object of the present invention is to provide a semiconductor device for high power that has high reliability and can be miniaturized.

According to one aspect for achieving the above object, a substrate, a nitride compound semiconductor layer disposed on the substrate, an aluminum gallium nitride layer (AlxGa1-) disposed on the nitride compound semiconductor layer, and xN) (0.1 ≦ x ≦ 1), an element isolation region for isolating the active regions from each other, a first groove portion formed by etching in a part of the arrangement portion of the gate electrode, with the active region being arranged on the gate electrode surrounded by the isolation region, a source electrode and a drain electrode, it is disposed on the isolation region, and a drain terminal connected electrode to the drain electrode, the gate A semiconductor device is provided in which the tip of the electrode and the drain terminal electrode face each other with the first groove interposed therebetween .

  According to the present invention, in a high-power semiconductor device composed of a GaN layer and an AlGaN layer separated by implant isolation, a part of the gate electrode is etched to form a groove, thereby providing high reliability. A semiconductor device for high power that can be miniaturized is provided.

According to the present invention, in a high-power semiconductor device composed of a GaN layer and an AlGaN layer separated by implant isolation, a trench is formed by etching a part under a gate electrode, thereby improving reliability. And a high-power semiconductor device that can be miniaturized.

According to the present invention, by etching a part under the gate electrode to form a groove, it is possible to prevent electrons from being injected into the GaN layer, thereby gradually increasing the drain current of the device. It is possible to provide a high-power semiconductor device that can suppress a decreasing current coplus phenomenon, has high reliability, and can be miniaturized.

According to the present invention, also, by the unevenness of the device surface is almost eliminated, focusing of the exposure device is facilitated, thereby, enables miniaturization of the gate electrode, a semiconductor device for high power to be improved high-frequency characteristics Can be provided.

  Next, embodiments of the present invention will be described with reference to the drawings. In the following, the same reference numerals are assigned to the same blocks or elements to avoid duplication of explanation and simplify the explanation. It should be noted that the drawings are schematic and different from the actual ones. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

  The following embodiments exemplify apparatuses and methods for embodying the technical idea of the present invention. In the embodiments of the present invention, the arrangement of each component is as follows. Not specific. Various modifications can be made to the embodiment of the present invention within the scope of the claims.

[First embodiment]
(Element structure)
A schematic planar pattern configuration of the semiconductor device according to the first embodiment of the present invention is expressed as shown in FIG. 1 is represented as shown in FIG. 2, and the schematic sectional structure along the line II-II in FIG. 1 is represented as shown in FIG. .

As shown in FIGS. 1 to 3, the semiconductor device according to the first embodiment includes a substrate 10, a nitride-based compound semiconductor layer 12 disposed on the substrate 10, and a nitride-based compound semiconductor layer 12. An active region AA composed of an aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 14, an element isolation region 24 that isolates the active region AA from each other, and a gate electrode 20 is provided with a groove 28a formed by etching in a part of the arrangement portion 20 and a gate electrode 20, a source electrode 18 and a drain electrode 26 arranged on the active region AA surrounded by the element isolation region 24.

The element isolation region 24 is formed up to a part in the depth direction of the aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 14 and the nitride-based compound semiconductor layer 12.

  As shown in FIG. 3, the groove 28 a is formed at the tip of the gate electrode 20 including a part of the active region near the gate electrode 20.

  Further, as shown in FIGS. 1 and 3, the device further includes a gate terminal electrode 21 connected to the gate electrode 20 and disposed on the element isolation region 24, and the groove 28 b is formed between the gate electrode 20 and the gate terminal electrode 21. It may be formed so as to include a part of the active region AA.

The element isolation region 24 is formed by ion implantation. As the ion species, for example, nitrogen (N), argon (Ar), or the like can be applied. Further, the dose accompanying ion implantation is, for example, about 1 × 10 ¹⁴ (ions / cm ² ), and the acceleration energy is, for example, about 100 keV to 200 keV.

A passivation insulating layer 22 is formed on the element isolation region 24 and the device surface. The insulating layer 22 is formed of, for example, a nitride film, an alumina (Al ₂ O ₃ ) film, an oxide film (SiO ₂ ), or an oxynitride film (SiON) deposited by PECVD (Plasma Enhanced Chemical Vapor Deposition). can do.

A source contact 18a is formed at the interface between the source electrode 18 and the aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 14, and the drain electrode 26 and the aluminum gallium nitride layer (Al _A drain contact 26 a is formed at the interface with _x Ga _1-x N) (0.1 ≦ x ≦ 1) 14. The source electrode 18 and the drain electrode 26 are made of, for example, aluminum (Al), Ti / Au, or the like.

  The gate electrode 20 can be formed of, for example, Ni / Au.

  The source contact 18a and the drain contact 26a can be formed by a laminated structure made of, for example, Al / Ti or Ni / Al / Ti.

At the interface between the nitride-based compound semiconductor layer 12 and the aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 14 disposed on the nitride-based compound semiconductor layer 12, A two-dimensional electron gas layer is formed.

  The substrate 10 can be composed of a silicon carbide (SiC) substrate, a semi-insulating silicon substrate, a sapphire substrate, or the like.

  The nitride compound semiconductor layer 12 is formed of, for example, a GaN layer.

(Experimental result)
FIG. 4 shows a comparison result of current change amounts I _dss / I _dss0 between the semiconductor device according to the first embodiment and the semiconductor device according to the conventional example, with the horizontal axis as time. In FIG. 4, the current change amount I _dss / I _dss0 represents the ratio of the saturation current value I _{dss to} the drain-source saturation current value I _{dss0 in} the initial state. Here, the conventional example to be compared is a complete planar structure in which the element isolation region 24 is formed by ion implantation and the grooves 28a and 28b are not formed, as in the semiconductor device according to the first embodiment. Corresponds to the case.

As is clear from FIG. 4, in the conventional example, the change with time of the current change amount I _dss / I _dss0 is remarkable, and the saturation current value between the drain and the source decreases with the passage of time. On the other hand, in the semiconductor device according to the first embodiment, the lowering of the saturation current value is suppressed by etching a part under the gate electrode to form the groove.

(Production method)
The method for manufacturing a semiconductor device according to the first embodiment includes a step of forming a nitride compound semiconductor layer 12 on a substrate 10 and an aluminum gallium nitride layer (Al _x Ga) on the nitride compound semiconductor layer 12. _1-x N) (0.1 ≦ x ≦ 1) 14 forming the active region AA, forming the device isolation region 24 that isolates the active region AA from each other, and the arrangement of the gate electrode 20 Etching a part of the portion to form the groove portions 28a and 28b and forming the gate electrode 20, the source electrode 18 and the drain electrode 26 on the active region AA surrounded by the element isolation region 24. .

In the step of forming the element isolation region 24, the element isolation region 24 has a depth of the aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 14 and the nitride-based compound semiconductor layer 12. Form up to part of the direction.

  In the step of forming the groove portion, the groove portion is formed including a part of the active region AA in the vicinity of the gate electrode 20 at the tip portion of the gate electrode 20.

  The semiconductor device further includes a step of forming a gate terminal electrode 21 on the element isolation region 24 connected to the gate electrode 20, and the groove 28 b includes a part of the active region AA between the gate electrode 20 and the gate terminal electrode 21. May be formed.

  In the step of forming the element isolation region, the element isolation region 25 is formed by ion implantation.

  The method for manufacturing the semiconductor device according to the first embodiment of the present invention will be described below.

(A) TMG (trimethylgallium) and ammonia gas are flowed on the SiC substrate 10, and the GaN layer 12 is formed to a thickness of, for example, about 1 μm to 2 μm by epitaxial growth.

(B) Next, an aluminum gallium nitride layer (Al _0.3 Ga _1-0.3 N) (0.1 ≦ x ≦ 1) 14 having an Al composition ratio of about 30% is formed by flowing TMAl (trimethylaluminum) and ammonia gas and epitaxially growing. Is formed to a thickness of about 20 nm to 100 nm, for example.

(C) Next, an element isolation region 24 for isolating the active areas AA from each other is formed by an ion implantation technique. As the ion species, for example, nitrogen (N), argon (Ar), or the like can be applied. Further, the dose accompanying ion implantation is, for example, about 1 × 10 ¹¹ (ions / cm ² ), and the acceleration energy is, for example, about 100 keV to 200 keV.

(D) Next, a part of the portion where the gate electrode 20 is to be arranged is etched by a dry etching technique to form the grooves 28a and 28b. As the dry etching technique, a reactive ion etching (RIE) technique or the like can be applied. As the reaction gas, for example, a chlorine-based etching gas such as BCl ₃ can be used. Here, the depth of the grooves 28a and 28b is deeper than the thickness of the aluminum gallium nitride layer (Al _x Ga ₁ -xN) (0.1 ≦ x ≦ 1) 14, and is, for example, about 100 nm to 200 nm. . Therefore, the bottom surfaces of the groove portions 28 a and 28 b are the nitride-based compound semiconductor layer (GaN layer) 12.

(E) Next, the source contact 18 a and the drain contact 26 a are formed on the active region AA surrounded by the element isolation region 24. As the contact formation technique, a vacuum deposition technique, a sputtering technique, or the like can be applied. The source contact 18a and the drain contact 26a are formed as ohmic electrodes by a laminated structure made of, for example, Al / Ti or Ni / Al / Ti.

(F) Next, the gate electrode 20 is formed. As an electrode forming technique, a vacuum deposition technique, a sputtering technique, or the like can be applied. The gate electrode 20 can be formed of Ni / Au, for example. The gate electrode 20 forms a Schottky contact with the aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 14. The width of the gate electrode 20 is, for example, about 0.1 μm to 1 μm.

(G) Next, a passivation insulating layer 22 is formed on the entire device surface. The insulating layer 22 can be formed of, for example, a nitride film, an Al ₂ O ₃ film, a SiO ₂ film, a SiON film, or the like deposited by PECVD.

(H) Next, the source electrode 18 and the drain electrode 26 are formed. As an electrode forming technique, a vacuum deposition technique, a sputtering technique, or the like can be applied. The source electrode 18 and the drain electrode 26 are made of, for example, aluminum (Al), Ti / Au, or the like.

  The semiconductor device according to the first embodiment is completed through the processes (a) to (h).

  According to the first embodiment of the present invention, a groove is formed by etching a part under a gate electrode in a semiconductor device composed of a GaN layer and an AlGaN layer separated by implant isolation. Accordingly, it is possible to provide a highly reliable semiconductor device that can be miniaturized and a manufacturing method thereof.

  According to the first embodiment of the present invention, by etching a part under the gate electrode to form a groove, it is possible to prevent electrons from being injected into the GaN layer. A current coplus phenomenon in which the drain current of the device gradually decreases can be suppressed, and a highly reliable semiconductor device that can be miniaturized and a manufacturing method thereof can be provided.

  According to the first embodiment of the present invention, since there is almost no unevenness on the surface of the device, it becomes easy to focus the exposure apparatus, thereby enabling miniaturization of the gate electrode and improving high-frequency characteristics. A semiconductor device and a manufacturing method thereof can be provided.

[Second Embodiment]
(Element structure)
An overall schematic planar pattern configuration of the semiconductor device according to the second embodiment is expressed as shown in FIG. An enlarged view of portion A in FIG. 5 is expressed as shown in FIG. Since the basic element cross-sectional structure is the same as that shown in FIGS. 2 to 3 shown in the first embodiment, description of each layer is omitted.

  The semiconductor device according to the second embodiment is characterized in that an electrode pattern arrangement for increasing power and a groove 28a formed under the gate electrode are provided.

As shown in FIGS. 2 to 3 and FIGS. 5 to 6, the overall schematic planar pattern configuration of the semiconductor device according to the second embodiment includes a substrate 10 and a nitride disposed on the substrate 10. An active region AA which is disposed on the nitride-based compound semiconductor layer 12 and on the nitride-based compound semiconductor layer 12 and includes an aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 14; An element isolation region 24 that isolates the region AA from each other, a groove portion 28a formed by etching in a portion of the arrangement portion of the gate electrode 20 having a plurality of fingers, and an active region AA surrounded by the element isolation region 24 A gate electrode 20, a source electrode 18 and a drain electrode 26, each having a plurality of fingers, disposed on one surface; and a gate electrode 20, a source electrode disposed on a first surface of the substrate 10; 8 and the gate terminal electrodes 240 are formed by bundling a plurality of fingers, respectively every the drain electrode 26, and a source terminal electrode 200 and the drain terminal electrode 220.

The element isolation region 24 is formed up to a part in the depth direction of the aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 14 and the nitride-based compound semiconductor layer 12.

  The groove 28a is formed including a part of the active region AA in the vicinity of the gate electrode 20 at the tip of the gate electrode 20 having a plurality of fingers.

  The groove portion may be formed so as to include a part of the active region AA between the gate electrode 20 and the gate terminal electrode 240, similarly to the structure of the groove portion 28b shown in FIG.

  The element isolation region 24 is formed by ion implantation.

  In the configuration example of FIG. 5, the dimensions of each part are, for example, a cell width W1 of about 120 μm, W2 of about 80 μm, a cell length W3 of about 100 μm, W4 of about 120 μm, and a gate width WG of 100 μm × 6 as a whole. × 4 cells = about 2.4 mm.

  In the example of FIG. 5, in the source terminal electrode 200, a VIA hole 260 is formed from the back surface of the substrate 10, and a ground conductor is formed on the back surface of the substrate 10. When the circuit element is grounded, the circuit element provided on the substrate 10 and the ground conductor formed on the back surface of the substrate 10 are electrically connected via the VIA hole 260 penetrating the substrate 10.

  The gate terminal electrode 240 is connected to the peripheral semiconductor chip with a bonding wire or the like, and the drain terminal electrode 220 is also connected to the peripheral semiconductor chip with a bonding wire or the like.

(Production method)
The method for manufacturing a semiconductor device according to the second embodiment includes a step of forming a nitride compound semiconductor layer on a substrate, and an aluminum gallium nitride layer (Al _x Ga _1-x on the nitride compound semiconductor layer). N) a step of forming an active region made of (0.1 ≦ x ≦ 1), a step of forming an element isolation region for isolating the active regions from each other, and a portion of the gate electrode having a plurality of fingers to be arranged Etching a portion to form a groove, forming a gate electrode, a source electrode and a drain electrode each having a plurality of fingers on the first surface of the active region surrounded by the element isolation region, and a substrate A gate terminal electrode, a source terminal electrode, and a drain end formed by bundling a plurality of fingers for each of the gate electrode, the source electrode, and the drain electrode on the first surface And a step of forming the electrode.

In the step of forming the element isolation region, the element isolation region is a part of the depth direction of the aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) and the nitride-based compound semiconductor layer. Form up to.

  In the step of forming the groove portion, the groove portion is formed including a part of the active region in the vicinity of the gate electrode at the tip portion of the gate electrode having a plurality of fingers.

  In the step of forming the element isolation region, the element isolation region is formed by ion implantation.

  The details of the method of manufacturing the semiconductor device according to the second embodiment are the same as those of the first embodiment, and thus the description thereof is omitted.

(Modification)
A schematic planar pattern configuration of a semiconductor device according to a modification of the second embodiment is expressed as shown in FIG.

  In the semiconductor device according to the modification of the second embodiment, as shown in FIG. 7, the groove 28 a is a part of the active region near the gate electrode at the tip of the gate electrode 20 having a plurality of fingers. Are formed in a stripe shape parallel to the arrangement direction of the plurality of finger electrodes.

  Also in the method of manufacturing a semiconductor device according to the modification of the second embodiment, in the step of forming the groove portion, the groove portion 28a is activated in the vicinity of the gate electrode 20 at the tip portion of the gate electrode 20 having a plurality of fingers. A part of the area AA is included and formed in a stripe shape parallel to the arrangement direction of the plurality of finger electrodes.

  Further, as shown in FIGS. 1 and 3, the groove 28b includes a part of the active region AA between the gate terminal electrode 240 disposed on the element isolation region 24 and the gate electrode 20 having a plurality of fingers. Thus, it may be formed under the gate electrode 20 having a plurality of fingers.

  Moreover, these groove parts 28b may be formed in stripes parallel to the arrangement direction of the plurality of finger electrodes, as in FIG.

  According to the second embodiment of the present invention, in the high-power semiconductor device composed of a GaN layer and an AlGaN layer separated by implant isolation, a part under the gate electrode is etched to form a groove. By forming the semiconductor device, it is possible to provide a high-power semiconductor device that is highly reliable and can be miniaturized, and a manufacturing method thereof.

  According to the second embodiment of the present invention, by etching a part under the gate electrode to form a groove, it is possible to prevent electrons from being injected into the GaN layer. It is possible to provide a high-power semiconductor device that can suppress a current coplus phenomenon in which the drain current of the device gradually decreases, is highly reliable, and can be miniaturized, and a method for manufacturing the same.

  According to the second embodiment of the present invention, since there is almost no unevenness on the surface of the device, it is easy to focus the exposure apparatus, thereby enabling miniaturization of the gate electrode and improving high-frequency characteristics. A power semiconductor device and a method for manufacturing the same can be provided.

[Other embodiments]
As described above, the present invention has been described according to the first to second embodiments. However, it should be understood that the descriptions and drawings constituting a part of this disclosure are exemplary and limit the present invention. should not do. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

  The semiconductor device of the present invention is not limited to a field effect transistor (FET), but a high electron mobility transistor (HEMT), a lateral doped metal-oxide-semiconductor field effect transistor (LDMOS). Needless to say, an amplifying element such as a heterojunction bipolar transistor (HBT) or a micro electro mechanical systems (MEMS) element can also be applied.

  The substrate region includes a GaAs substrate, a GaN substrate, a substrate in which a GaN epitaxial layer is formed on a SiC substrate, a substrate in which a GaN epitaxial layer is formed on a Si substrate, and a heterojunction epitaxial layer made of GaN / GaAlN on a SiC substrate. A substrate, a substrate in which a GaN epitaxial layer is formed on a sapphire substrate, a sapphire substrate, or a diamond substrate may be provided.

  As described above, the present invention includes various embodiments not described herein.

  The semiconductor device of the present invention can be applied to a wide range of fields such as an internal matching power amplification element, a power MMIC (Monolithic Microwave Integrated Circuit), a microwave power amplifier, a millimeter wave power amplifier, and a high-frequency MEMS element.

1 is a schematic plan pattern configuration diagram of a semiconductor device according to a first embodiment of the present invention. FIG. FIG. 2 is a schematic cross-sectional structure diagram of the semiconductor device according to the first embodiment of the present invention, taken along line II in FIG. 1. FIG. 2 is a schematic cross-sectional structure diagram of the semiconductor device according to the first embodiment of the present invention, taken along line II-II in FIG. 1. The comparison result of the electric current variation | change_quantity which makes time the horizontal axis | shaft of Idss / Idss0 of the semiconductor device which concerns on the 1st Embodiment of this invention, and the semiconductor device which concerns on a prior art example. FIG. 5 is an overall schematic plane pattern configuration diagram of a semiconductor device according to a second embodiment of the present invention. The enlarged view of A part of FIG. The typical plane pattern block diagram of the semiconductor device which concerns on the modification of the 2nd Embodiment of this invention. The typical plane pattern block diagram of the semiconductor device which concerns on a prior art example.

Explanation of symbols

10 ... Substrate 12 ... Nitride compound semiconductor layer (GaN layer)
14: Aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1)
DESCRIPTION OF SYMBOLS 18 ... Source electrode 18a ... Source contact 20 ... Gate electrode 21 ... Gate terminal electrode 22 ... Insulating layer 24, 25 ... Element isolation region 26 ... Drain electrode 26a ... Drain contact 28a, 28b ... Groove part 200 ... Source terminal electrode 220 ... Drain terminal Electrode 240 ... Gate terminal electrode 260 ... VIA hole AA ... Active region

Claims (9)

A substrate,
A nitride compound semiconductor layer disposed on the substrate;
An active region disposed on the nitride-based compound semiconductor layer and made of an aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1);
An element isolation region for isolating the active regions from each other;
A first groove formed by etching in a portion of the gate electrode planned to be disposed;
A gate electrode, a source electrode, and a drain electrode disposed on the active region surrounded by the element isolation region ;
A drain terminal electrode disposed on the element isolation region and connected to the drain electrode , wherein a front end portion of the gate electrode and the drain terminal electrode face each other with the first groove portion interposed therebetween. Semiconductor device. The element isolation region is formed up to a part in the depth direction of the aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) and the nitride-based compound semiconductor layer. The semiconductor device according to claim 1. A gate terminal electrode connected to the gate electrode and disposed on the element isolation region;
And a second groove formed by etching on a portion of the gate electrode scheduled to be disposed, wherein the second groove is formed between the gate electrode and the gate terminal electrode. Item 3. The semiconductor device according to Item 1 or 2. Each of the gate electrode, the source electrode, and the drain electrode includes a plurality of fingers,
Wherein arranged on the isolation region, a gate terminal electrode and the source terminal electrodes are formed by bundling a plurality of fingers, respectively every the gate electrode and the source electrode,
The semiconductor device according to claim 1, wherein the drain terminal electrode is formed by bundling a plurality of fingers of the drain electrode . The element isolation region is formed up to a part in the depth direction of the aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) and the nitride-based compound semiconductor layer. The semiconductor device according to claim 4. The semiconductor device according to claim 4, wherein a front end portion of the gate electrode having the plurality of fingers and the drain terminal electrode are opposed to each other with the first groove portion interposed therebetween . The tip of the gate electrode having the plurality of fingers and the drain terminal electrode are opposed to each other across the first groove, and the first groove is in a stripe shape parallel to the arrangement direction of the plurality of finger electrodes. The semiconductor device according to claim 4, wherein the semiconductor device is formed. The semiconductor device according to claim 4, wherein the second groove is formed between the gate electrode and the gate terminal electrode.   The semiconductor device according to claim 1, wherein the element isolation region is formed by ion implantation.

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