JP2011040597A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device that is reduced in thermal resistance by preventing an air bubble from being formed. <P>SOLUTION: The semiconductor device includes: a nitride-based compound semiconductor layer 12 disposed on a top surface of a substrate 10; an active region AA disposed on the nitride-based compound semiconductor layer; a gate electrode 24, a source electrode 20, and a drain electrode 22 disposed on the active region each of which has a plurality of fingers; a gate terminal electrode GE, a source terminal electrode SE, and a drain terminal electrode DE disposed on the nitride-based compound semiconductor layer in extension directions of the gate electrode, source electrode, and drain electrode and formed by bundling fingers for each of the gate electrode, source electrode, and drain electrode; a VIA hole CS disposed below the source terminal electrode; a back metal layer BE disposed on a reverse surface of the substrate 10 and connected to the source terminal electrode via the VIA hole; and a groove SC provided from the VIA hole on the reverse surface of the substrate to a substrate end where the source terminal electrode is arranged. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a semiconductor device that prevents generation of bubbles and reduces thermal resistance, and a manufacturing method thereof.

  Field effect transistors (FET) using compound semiconductors such as GaN (Gallium Nitride) have excellent high-frequency characteristics and are widely put into practical use as semiconductor devices that operate in the microwave / millimeter / submillimeter wave bands. Has been.

  As shown in FIG. 16, a schematic planar pattern configuration of a conventional semiconductor device includes, for example, a substrate 10 made of SiC, and a gate electrode 24, a source electrode 20 and a drain which are arranged on the substrate 10 and each have a plurality of fingers. The electrode 22 and the gate terminal electrodes GE1, GE2, GE3, the source terminal electrodes SE1, SE2,... Arranged on the substrate 10 and formed by bundling a plurality of fingers for each of the gate electrode 24, the source electrode 20 and the drain electrode 22. , SE4 and drain terminal electrode DE, and VIA holes CS1, CS2,..., CS4 formed for the source terminal electrodes SE1, SE2,.

  A general semiconductor device in which a VIA hole is formed and a manufacturing method thereof have already been disclosed (for example, refer to Patent Document 1).

  A schematic cross-sectional structure taken along line II in FIG. 16 is expressed as shown in FIG.

  The portions where the gate electrode 24, the source electrode 20 and the drain electrode 22 have a plurality of finger shapes are formed from an AlGaN layer 18 and a two-dimensional electron gas (2DEG) layer 16 as shown in FIGS. An active area AA is formed. The 2DEG layer 16 is formed at the interface between the AlGaN layer 18 and the GaN epitaxial growth layer 12. The source electrode 20 and the drain electrode 22 form an ohmic contact with the AlGaN layer 18, and the gate electrode 24 forms a Schottky contact with the AlGaN layer 18.

  In the example of FIG. 16, gate terminal electrodes GE1, GE2, GE3 and source terminal electrodes SE1, SE2,..., SE4 are arranged at one end of the substrate 10, and a drain terminal electrode DE is arranged at the other end.

  As shown in FIGS. 16 and 17, the source terminal electrodes SE1, SE2,..., SE4 are grounded back surface metal layers BE formed on the inner walls of the VIA holes CS1, CS2,. Connected with. The back metal layer BE is composed of, for example, a barrier metal layer made of Ti and a ground metal layer made of Au and formed on the barrier metal layer. Furthermore, as shown in FIG. 17, the solder layer 14a is formed in contact with the back surface metal layer BE.

  The reason why such VIA holes CS1, CS2,..., CS4 are formed for the source electrode 20 and the source terminal electrodes SE1, SE2,..., SE4 is that ground inductance that adversely affects the high frequency characteristics of the semiconductor device is reduced. Because.

  When the circuit element provided on the substrate 10 is grounded, the circuit element and the back metal layer BE are electrically connected through the VIA holes CS1, CS2,..., CS4 formed in the substrate 10.

  The gate terminal electrodes GE1, GE2, and GE3 are connected to the peripheral semiconductor chip by bonding wires, and the drain terminal electrode DE is also connected to the peripheral semiconductor chip by bonding wires.

  The FET including the VIA holes CS1, CS2,..., CS4 is an effective means for reducing the ground inductance. However, when the substrate 10 including the VIA holes CS1, CS2,..., CS4 is die-bonded to the package using the solder layer 14a, the air in the VIA holes CS1, CS2,. End up. Bubbles have very poor thermal conductivity. In particular, for a high output FET that requires low thermal resistance, bubbles existing between the substrate 10 of the FET chip and the solder layer 14a that is die-bonded to the package lead to an increase in thermal resistance, and deterioration of the high-frequency characteristics of the high output FET. There is a problem that reliability is lowered.

Japanese Patent Application Laid-Open No. 08-78437

  An object of the present invention is to provide a microwave / millimeter-wave / submillimeter-wave band semiconductor device that prevents generation of bubbles between a substrate and a solder layer, reduces thermal resistance, and prevents deterioration of high-frequency characteristics and deterioration of reliability. And providing a manufacturing method thereof.

According to one aspect of the present invention for achieving the above object, a substrate, a nitride compound semiconductor layer disposed on a first surface of the substrate, and disposed on the nitride compound semiconductor layer, An active region composed of an aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1), and a gate electrode, a source electrode, and a drain electrode disposed on the active region, each having a plurality of fingers And arranged on the nitride-based compound semiconductor layer in a direction in which the gate electrode, the source electrode, and the drain electrode extend, and a plurality of fingers are bundled for each of the gate electrode, the source electrode, and the drain electrode. A gate terminal electrode, a source terminal electrode, a drain terminal electrode, and a VIA hole disposed below the source terminal electrode and penetrating the substrate. A back metal layer disposed on the second surface opposite to the first surface of the substrate and connected to the source terminal electrode via the VIA hole, and the VIA hole on the second surface of the substrate. And a groove provided over the edge of the substrate.

According to another aspect of the present invention, a substrate, a nitride compound semiconductor layer disposed on the first surface of the substrate, an aluminum gallium nitride layer (Al) disposed on the nitride compound semiconductor layer, and _x Ga _1-x N) (0.1 ≦ x ≦ 1), a gate electrode disposed on the active region, each having a plurality of fingers, a source electrode and a drain electrode, the gate electrode, A gate terminal electrode that is disposed on the nitride-based compound semiconductor layer in a direction in which the source electrode and the drain electrode extend and is formed by bundling a plurality of fingers for each of the gate electrode, the source electrode, and the drain electrode; A source terminal electrode and a drain terminal electrode, and a VIA hole disposed below the source electrode and the source terminal electrode through the substrate A back metal layer disposed on a second surface opposite to the first surface of the substrate and connected to the source electrode and the source terminal electrode via the VIA hole, and a second surface of the substrate There is provided a semiconductor device including a groove provided from the VIA hole to an end of the substrate.

According to another aspect of the present invention, a nitride compound semiconductor layer is formed on the first surface of the substrate, and an aluminum gallium nitride layer (Al _x Ga _1-x is formed on the nitride compound semiconductor layer. N) a step of forming an active region made of (0.1 ≦ x ≦ 1), a step of forming a gate electrode, a source electrode and a drain electrode each having a plurality of fingers on the active region, and the gate electrode A gate terminal electrode and a source terminal electrode are formed by bundling a plurality of fingers for each of the gate electrode, the source electrode, and the drain electrode on the nitride compound semiconductor layer in a direction in which the source electrode and the drain electrode extend. Forming a drain terminal electrode and a drain terminal electrode; forming a VIA hole penetrating the substrate below the source terminal electrode; and Forming a back metal layer connected to the source terminal electrode via the VIA hole on the second surface opposite to the first surface; and from the VIA hole on the second surface of the substrate, A method for manufacturing a semiconductor device is provided that includes a step of forming a groove over an edge of a substrate.

  According to the present invention, a microwave / millimeter-wave / submillimeter-wave band semiconductor device that prevents generation of bubbles between a substrate and a solder layer, reduces thermal resistance, and prevents deterioration of high-frequency characteristics and deterioration of reliability. And a method for manufacturing the same.

1 is a schematic plan pattern configuration diagram of a semiconductor device according to a first embodiment of the present invention. FIG. FIG. 2 is a schematic cross-sectional structure diagram taken along line II-II in FIG. 1. FIG. 3 is a schematic cross-sectional structure diagram in which a solder layer is formed with respect to the structure of FIG. 2. FIG. 3 is a configuration example 1 of the semiconductor device according to the first embodiment of the present invention, and is a schematic cross-sectional configuration diagram taken along line III-III in FIG. 1. FIG. 3 is a configuration example 2 of the semiconductor device according to the first embodiment of the present invention, and is a schematic cross-sectional configuration diagram taken along line III-III in FIG. 1. FIG. 4 is a schematic cross-sectional configuration diagram of configuration example 3 of the semiconductor device according to the first embodiment of the present invention, taken along line III-III in FIG. 1. FIG. 4 is a schematic cross-sectional configuration diagram taken along line III-III in FIG. 1, which is a configuration example 4 of the semiconductor device according to the first embodiment of the present invention. The typical cross-section figure of the semiconductor device which concerns on the modification 1 of the 1st Embodiment of this invention. FIG. 9 is a schematic cross-sectional structure diagram in which a solder layer is formed with respect to the structure of FIG. 8. FIG. 9 is a schematic cross-sectional structure diagram of a semiconductor device according to Modification 2 of the first embodiment of the present invention. FIG. 11 is a schematic cross-sectional structure diagram in which a solder layer is formed on the structure of FIG. 10. The typical plane pattern block diagram of the semiconductor device which concerns on the 2nd Embodiment of this invention. FIG. 14 is a schematic cross-sectional structure diagram taken along line IV-IV in FIG. 12. FIG. 13 is a schematic cross-sectional structure diagram taken along line VV in FIG. 12. The typical cross-section figure which formed the solder layer with respect to the structure of FIG. The typical plane pattern block diagram of the conventional semiconductor device. FIG. 17 is a schematic cross-sectional structure diagram along the line II in FIG. 16.

  Next, an embodiment of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. Further, the embodiments described below exemplify apparatuses and methods for embodying the technical idea of the present invention, and the embodiments of the present invention have the following structure and arrangement of components. It is not something specific. The embodiment of the present invention can be variously modified within the scope of the claims.

[First embodiment]
(Element structure)
A schematic planar pattern configuration of the semiconductor device according to the first embodiment of the present invention is expressed as shown in FIG. Moreover, the schematic cross-sectional structure along the II-II line of FIG. 1 is represented as shown in FIG.

As shown in FIGS. 1 to 2, the semiconductor device according to the first embodiment includes a substrate 10, a nitride-based compound semiconductor layer 12 disposed on the first surface of the substrate 10, and a nitride-based compound. An active region AA that is disposed on the semiconductor layer 12 and includes an aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 18 and a plurality of fingers each disposed on the active region AA The gate electrode 24, the source electrode 20 and the drain electrode 22, and the nitride compound semiconductor layer 12 in the extending direction of the gate electrode 24, the source electrode 20 and the drain electrode 22 are disposed. And gate terminal electrodes GE1 to GE3, source terminal electrodes SE1 to SE4, and drain terminal electrodes formed by bundling a plurality of fingers for each drain electrode 22 E, VIA holes CS1 to CS4 arranged through the substrate below the source terminal electrodes SE1 to SE4, and a second surface opposite to the first surface of the substrate 10, and the source terminal electrodes SE1 to SE1 Back metal layer BE connected to SE4 via VIA holes CS1 to CS4, and grooves SC1 to SC4 provided from VIA holes CS1 to CS4 on the second surface of substrate 10 to the edge of substrate 10 are provided. Prepare.

1 to 2, an aluminum gallium nitride layer (Al _x Ga ₁₎ between the gate electrode 24 and the source electrode 20, between the gate electrode 24 and the drain electrode 22, and under the gate electrode 24, the source electrode 20 and the drain electrode 22. _-x N) (0.1 ≦ x ≦ 1) 18 constitutes the active area AA.

  The grooves SC <b> 1 to SC <b> 4 provided on the second surface of the substrate 10 are formed by removing the second surface of the substrate 10. The thickness of the layer from which the second surface of the substrate 10 is removed is, for example, about 5 μm to 30 μm.

  The depth of the grooves SC1 to SC4 provided on the second surface of the substrate 10 is, for example, 1 μm or more, and the width is, for example, 1 μm or more.

  A schematic cross-sectional structure in which the solder layer 14 is formed with respect to the structure of FIG. 2 is expressed as shown in FIG. As shown in FIG. 3, solder layers 14 are filled in the VIA holes CS1 to CS4.

  In the semiconductor device according to the first embodiment of the present invention, when the FETs are die-bonded to the package by forming the grooves SC1 to SC4 from the VIA holes CS1 to CS4 to the end surface of the substrate 10, the VIA hole is formed. The air present in CS1 to CS4 is discharged from the VIA holes CS1 to CS4 due to thermal expansion and is allowed to escape through the grooves SC1 to SC4, thereby preventing generation of bubbles between the substrate 10 and the solder layer 14. be able to.

  In FIG. 1, a schematic cross-sectional structure taken along line III-III corresponds to Configuration Example 1 to Configuration Example 4 of the semiconductor device according to the first embodiment shown in FIGS. 4 to 7.

(Structural example 1)
As a schematic cross-sectional configuration taken along the line III-III in FIG. 1, a configuration example 1 of the semiconductor device according to the first embodiment includes a substrate 10 and a nitride disposed on the substrate 10 as shown in FIG. 4. A physical compound semiconductor layer 12, an aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 18 disposed on the nitride compound semiconductor layer 12, and an aluminum gallium nitride layer ( A source electrode 20, a gate electrode 24, and a drain electrode 22 disposed on (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 18. A two-dimensional electron gas (2DEG) layer is provided at the interface between the nitride-based compound semiconductor layer 12 and the aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 18. 16 is formed. In the configuration example 1 shown in FIG. 4, a high electron mobility transistor (HEMT) is shown.

(Structural example 2)
As a schematic cross-sectional configuration taken along line III-III in FIG. 1, a configuration example 2 of the semiconductor device according to the first embodiment includes a substrate 10 and a nitridation arranged on the substrate 10 as shown in FIG. 5. The physical compound semiconductor layer 12, the source region 26 and the drain region 28 disposed on the nitride based compound semiconductor layer 12, the source electrode 20 disposed on the source region 26, and the nitride based compound semiconductor layer 12 And the drain electrode 22 disposed on the drain region 28. A Schottky contact is formed at the interface between the nitride-based compound semiconductor layer 12 and the gate electrode 24. In the configuration example 2 shown in FIG. 5, a metal-semiconductor field effect transistor (MESFET) is shown.

(Structural example 3)
As a schematic cross-sectional configuration along the line III-III in FIG. 1, a configuration example 3 of the semiconductor device according to the first embodiment includes a substrate 10 and a nitride disposed on the substrate 10 as shown in FIG. 6. A physical compound semiconductor layer 12, an aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 18 disposed on the nitride compound semiconductor layer 12, and an aluminum gallium nitride layer ( A source electrode 20 and a drain electrode 22 disposed on Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 18 and an aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 18 and a gate electrode 24 disposed in a recess portion. A 2DEG layer 16 is formed at the interface between the nitride-based compound semiconductor layer 12 and the aluminum gallium nitride layer (Al _x Ga ₁ -xN) (0.1 ≦ x ≦ 1) 18. In the configuration example 3 illustrated in FIG. 6, the HEMT is illustrated.

(Structural example 4)
As a schematic cross-sectional configuration taken along line III-III in FIG. 1, a configuration example 4 of the semiconductor device according to the first embodiment includes a substrate 10 and a nitride disposed on the substrate 10 as shown in FIG. 7. A physical compound semiconductor layer 12, an aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 18 disposed on the nitride compound semiconductor layer 12, and an aluminum gallium nitride layer ( A source electrode 20 and a drain electrode 22 disposed on Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 18 and an aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 18 and a gate electrode 24 disposed in a two-stage recess portion. A 2DEG layer 16 is formed at the interface between the nitride-based compound semiconductor layer 12 and the aluminum gallium nitride layer (Al _x Ga ₁ -xN) (0.1 ≦ x ≦ 1) 18. In the configuration example 4 illustrated in FIG. 7, the HEMT is illustrated.

In the above embodiment, the nitride-based compound semiconductor layer 12 other than the active area AA is used as an electrically inactive element isolation region. As another method for forming the element isolation region, aluminum nitride is used. The gallium layer (Al _x Ga ₁ -xN) (0.1 ≦ x ≦ 1) 18 and the nitride-based compound semiconductor layer 12 may be formed by ion implantation up to a part in the depth direction. As the ion species, for example, nitrogen (N), argon (Ar), or the like can be applied. The dose accompanying ion implantation is, for example, about 1 × 10 ¹⁴ (ions / cm ² ), and the acceleration energy is, for example, about 100 keV to 200 keV.

A passivation insulating layer (not shown) is formed on the element isolation region and the device surface. As this insulating layer, for example, a nitride film, an alumina (Al ₂ O ₃ ) film, an oxide film (SiO ₂ ), an oxynitride film (SiON) or the like deposited by PECVD (Plasma Enhanced Chemical Vapor Deposition) method is formed. be able to.

  The source electrode 20 and the drain electrode 22 are made of, for example, Ti / Al.

  The gate electrode 24 can be formed of, for example, Ni / Au.

  The back surface metal layer BE includes a barrier metal layer and a ground metal layer disposed on the barrier metal layer, but is not shown in FIG. The barrier metal layer is made of, for example, a Ti layer or a Ti / Pt layer, and the ground metal layer is made of, for example, an Au layer.

  Therefore, the back surface metal layer BE may have any one of an Au layer, a Ti / Au layer, a Ti / W / Au layer, and a Ti / Pt / Au layer. The thickness of the back metal layer BE is, for example, about 5 μm to 30 μm.

  The substrate 10 includes a SiC substrate, a GaAs substrate, a GaN substrate, a substrate having a GaN epitaxial layer formed on the SiC substrate, a substrate having a GaN epitaxial layer formed on the Si substrate, and a heterojunction epitaxial layer made of GaN / AlGaN on the SiC substrate. Or a sapphire substrate, a sapphire substrate, or a diamond substrate.

  In the semiconductor device according to the first embodiment, the pattern length in the longitudinal direction of the gate electrode 24, the source electrode 20, and the drain electrode 22 decreases as the operating frequency increases such as microwave / millimeter wave / submillimeter wave. Is set. For example, in the millimeter wave band, the pattern length is about 25 μm to 50 μm.

  The width of the source electrode 20 is about 40 μm, for example, and the width of the source terminal electrodes SE1 to SE4 is about 100 μm, for example.

  The formation width of the VIA holes CS1 to CS4 is, for example, about 10 μm to 40 μm.

(Production method)
The semiconductor device manufacturing method according to the first embodiment includes a step of forming a nitride-based compound semiconductor layer 12 on the first surface of the substrate 10, and an aluminum gallium nitride layer on the nitride-based compound semiconductor layer 12. A step of forming an active region AA composed of (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 18, and a gate electrode 24, a source electrode 20, and a plurality of fingers respectively on the active region AA On the nitride-based compound semiconductor layer 12 in the direction in which the drain electrode 22 is formed and in the direction in which the gate electrode 24, the source electrode 20, and the drain electrode 22 extend, a plurality of gate electrodes 24, source electrodes 20, and drain electrodes 22 are provided. Forming the gate terminal electrodes GE1 to GE3, the source terminal electrodes SE1 to SE4 and the drain terminal electrode DE by bundling the fingers respectively; A step of forming VIA holes CS1 to CS4 penetrating the substrate 10 below the terminal electrodes SE1 to SE4, and a VIA hole with respect to the source terminal electrodes SE1 to SE4 on the second surface opposite to the first surface of the substrate 10 Forming a back metal layer BE connected via CS1 to CS4 and forming grooves SC1 to SC4 from the VIA holes CS1 to CS4 on the second surface of the substrate 10 to the edge of the substrate 10; .

  The grooves SC <b> 1 to SC <b> 4 provided on the second surface of the substrate 10 may be formed by removing a part of the substrate 10 from the second surface of the substrate 10.

  The semiconductor device manufacturing method according to the first embodiment of the present invention will be described in detail below.

(A) TMG (trimethylgallium) and ammonia gas are flowed on the SiC substrate 10, and the nitride-based compound semiconductor layer 12 made of a GaN layer is formed to a thickness of, for example, about 1 μm by epitaxial growth.

(B) Next, TMAl (trimethylaluminum) and ammonia gas are allowed to flow, and by epitaxial growth, for example, an aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) having an Al composition ratio of about 30%. ) 18 is formed to a thickness of about 20 nm to 100 nm, for example.

(C) Next, Ti / Al or the like is deposited on the source electrode 20 and the drain electrode 22 to form ohmic electrodes.

(D) Next, Ni / Au or the like is deposited on the gate electrode 24 to form a Schottky electrode.

(E) Next, the substrate 10 is polished from the back surface by using a chemical mechanical polishing (CMP) technique to form a thin layer. Here, the thickness of the thinned substrate 10 is, for example, about 50 μm to 100 μm.

(F) Next, VIA holes CS1 to CS4 penetrating the substrate 10 are formed under the source terminal electrodes SE1 to SE4 from the back surface of the substrate 10 using, for example, reactive ion etching (RIE) technology. Form.

(G) Next, grooves SC <b> 1 to SC <b> 4 are formed from the VIA holes CS <b> 1 to CS <b> 4 on the second surface of the substrate 10 to the end of the substrate 10. In the process of forming the grooves SC1 to SC4, for example, the RIE technique can be used as in the process of forming the VIA holes CS1 to CS4.

(H) Next, the back surface metal layer BE is formed on the back surface of the substrate 10 using a vacuum deposition technique or the like. As a result, the grounding back surface metal layer BE is connected to the source terminal electrodes SE1 to SE4 via the VIA holes CS1 to CS4.

(I) Next, as shown in FIG. 3, the solder layer 14 is formed so as to completely embed the VIA holes CS1 to CS4 in the back surface metal layer BE, and the semiconductor chip is mounted on the package.

  Through the steps (a) to (i), the semiconductor device according to the first embodiment shown in FIGS. 1 to 3 is obtained.

  In the method of manufacturing a semiconductor device according to the first embodiment, when the FET is die-bonded to the package by forming the grooves SC1 to SC4 from the VIA holes CS1 to CS4 to the end surface of the substrate 10, the VIA hole is formed. The air present in CS1 to CS4 is discharged from the VIA holes CS1 to CS4 due to thermal expansion and is allowed to escape through the grooves SC1 to SC4, thereby preventing generation of bubbles between the substrate 10 and the solder layer 14. be able to.

(Modification 1)
A schematic cross-sectional structure of the semiconductor device according to the first modification of the first embodiment is represented as shown in FIG. 8, and a schematic cross-sectional structure in which a solder layer 14 is formed on the structure of FIG. As shown in FIG.

  In the semiconductor device according to the first modification of the first embodiment, as shown in FIGS. 8 and 9, the back surface metal layer BE is removed from the grooves SC <b> 1 to SC <b> 4 provided on the second surface of the substrate 10. It is formed by that. The other configuration is the same as that of the first embodiment, and a duplicate description is omitted.

The manufacturing method of the semiconductor device according to the first modification of the first embodiment is different from the first embodiment in the following points. That is, after forming the VIA holes CS1 to CS4 penetrating the substrate 10 from the back surface of the substrate 10 under the source terminal electrodes SE1 to SE4 using, for example, RIE technology,
A back metal layer BE is formed on the back surface of the substrate 10 using a vacuum deposition technique or the like. Thereafter, the back surface metal layer BE extends from the VIA holes CS1 to CS4 on the second surface of the substrate 10 to the edge of the substrate 10.
The grooves SC1 to SC4 are formed by removing. Next, as shown in FIG. 9, the solder layer 14 is formed so as to completely fill the VIA holes CS1 to CS4 in the back surface metal layer BE, and the semiconductor chip is mounted on the package.

  Through the above steps, the semiconductor device according to the first modification of the first embodiment shown in FIGS. 8 to 9 is obtained.

  In the manufacturing method of the semiconductor device according to Modification 1 of the first embodiment, grooves SC1 to SC4 are formed by removing back metal layer BE from VIA holes CS1 to CS4 to the end surface of substrate 10. Then, when die-bonding the FET to the package, the air present in the VIA holes CS1 to CS4 is discharged from the VIA holes CS1 to CS4 due to thermal expansion, and passes through the grooves SC1 to SC4. Generation of bubbles between the solder layer 14 and the solder layer 14 can be prevented.

(Modification 2)
A schematic cross-sectional structure of the semiconductor device according to the second modification of the first embodiment is represented as shown in FIG. 10, and a schematic cross-sectional structure in which a solder layer 14 is formed on the structure of FIG. 11 is represented.

  In the semiconductor device according to the second modification of the first embodiment, as shown in FIGS. 10 and 11, the grooves SC <b> 1 to SC <b> 4 provided on the second surface of the substrate 10 are formed on the back surface metal layer BE and the substrate 10. It is formed by removing a part of. The other configuration is the same as that of the first embodiment, and a duplicate description is omitted.

The method for manufacturing a semiconductor device according to the second modification of the first embodiment is different from the first embodiment in the following points. That is, after forming the VIA holes CS1 to CS4 penetrating the substrate 10 from the back surface of the substrate 10 under the source terminal electrodes SE1 to SE4 using, for example, RIE technology,
A back metal layer BE is formed on the back surface of the substrate 10 using a vacuum deposition technique or the like. Thereafter, the back surface metal layer BE and a part of the substrate 10 are removed from the VIA holes CS1 to CS4 on the second surface of the substrate 10 to the end of the substrate 10, thereby forming the grooves SC1 to SC4. Next, as shown in FIG. 11, the solder layer 14 is formed so as to completely fill the VIA holes CS1 to CS4 in the back surface metal layer BE, and the semiconductor chip is mounted on the package.

  Through the above steps, the semiconductor device according to the second modification of the first embodiment shown in FIGS. 10 to 11 is obtained.

  In the method of manufacturing the semiconductor device according to the second modification of the first embodiment, by removing the back surface metal layer BE and a part of the substrate 10 from the VIA holes CS1 to CS4 to the end surface of the substrate 10, When the grooves SC1 to SC4 are formed and the FET is die-bonded to the package, the air present in the VIA holes CS1 to CS4 is discharged from the VIA holes CS1 to CS4 due to thermal expansion and passes through the grooves SC1 to SC4. By doing so, the generation of bubbles between the substrate 10 and the solder layer 14 can be prevented.

  According to the first embodiment, the microwave / millimeter wave / submillimeter wave prevents the generation of bubbles between the substrate and the solder layer, reduces the thermal resistance, and prevents the deterioration of the high frequency characteristics and the deterioration of the reliability. A band semiconductor device can be provided.

[Second Embodiment]
A schematic planar pattern configuration of the semiconductor device according to the second embodiment of the present invention is expressed as shown in FIG. 12 is represented as shown in FIG. 13, and the schematic sectional structure along the line VV in FIG. 12 is represented as shown in FIG. .

As shown in FIGS. 12 to 14, the semiconductor device according to the second embodiment includes a substrate 10, a nitride compound semiconductor layer 12 disposed on the first surface of the substrate 10, and a nitride compound. An active region AA that is disposed on the semiconductor layer 12 and includes an aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 18 and a plurality of fingers each disposed on the active region AA The gate electrode 24, the source electrode 20 and the drain electrode 22, and the nitride compound semiconductor layer 12 in the extending direction of the gate electrode 24, the source electrode 20 and the drain electrode 22 are disposed. And gate terminal electrodes GE1 to GE3, source terminal electrodes SE1 to SE4 and drain terminals formed by bundling a plurality of fingers for each drain electrode 22 The electrode DE, the VIA holes CS11, CS12, CS21, CS22 to CS41, CS42 arranged below the source electrode 20 and the source terminal electrodes SE1 to SE4, and the second surface opposite to the first surface of the substrate 10 are arranged. The back metal layer BE connected to the source electrode 20 and the source terminal electrodes SE1 to SE4 via the VIA holes CS11, CS12, CS21, CS22 to CS41, CS42, and the VIA hole CS11 on the second surface of the substrate 10 , CS12, CS21, CS22 to CS41, CS42, and grooves SC11, SC12, SC21, SC22 to SC41, SC42 provided across the edge of the substrate 10.

12 to 14, an aluminum gallium nitride layer (Al _x Ga ₁₎ between the gate electrode 24 and the source electrode 20, between the gate electrode 24 and the drain electrode 22, and under the gate electrode 24, the source electrode 20, and the drain electrode 22. _-x N) (0.1 ≦ x ≦ 1) 18 constitutes the active area AA.

  In the second embodiment, the width of the source electrode 20 is about 40 μm, for example, and the width of the source terminal electrodes SE1 to SE4 is about 100 μm, for example.

  The formation width of the VIA holes CS11, CS12, CS21, CS22 to CS41, CS42 is, for example, about 10 μm to 20 μm.

  Further, the grooves SC11, SC12, SC21, SC22 to SC41, SC42 provided on the second surface of the substrate 10 are formed by removing a part of the substrate 10 from the second surface of the substrate 10. The thickness of the layer from which the second surface of the substrate 10 is removed is, for example, about 5 μm to 30 μm.

  The depths of the grooves SC11, SC12, SC21, SC22 to SC41, SC42 provided on the second surface of the substrate 10 are, for example, 1 μm or more, and the width is, for example, 1 μm or more.

  A schematic cross-sectional structure in which the solder layer 14 is formed with respect to the structure of FIG. 14 is expressed as shown in FIG. As shown in FIG. 15, the solder layer 14 is filled in the VIA holes CS11, CS12, CS21, CS22 to CS41, CS42.

  In the semiconductor device according to the second embodiment, grooves SC11, SC12, SC21, SC22 to SC41, SC42 are formed from the VIA holes CS11, CS12, CS21, CS22 to CS41, CS42 to the end surface of the substrate 10. When the FET is die-bonded to the package, the air present in the VIA holes CS11, CS12, CS21, CS22 to CS41, CS42 is discharged from the VIA holes CS11, CS12, CS21, CS22 to CS41, CS42 due to thermal expansion. Generation of bubbles between the substrate 10 and the solder layer 14 can be prevented by passing through the grooves SC11, SC12, SC21, SC22 to SC41, SC42.

  Also in the second embodiment, the same configuration example as the configuration examples 1 to 4 of the semiconductor device according to the first embodiment shown in FIGS. 4 to 7 can be applied.

  Moreover, since the configuration of each part is the same as that of the semiconductor device according to the first embodiment, a duplicate description is omitted.

  The method for manufacturing a semiconductor device according to the second embodiment is characterized in that, in the step of forming a VIA hole, the VIA hole is formed also through the substrate under the source electrode. Since this is the same as that of the first embodiment, redundant description is omitted.

  Similar to the first modification of the first embodiment shown in FIG. 8, the back surface metal layer BE is removed from the grooves SC11, SC12, SC21, SC22 to SC41, SC42 provided on the second surface of the substrate 10. May be formed.

  On the other hand, as in the second modification of the first embodiment shown in FIG. 10, the substrate is formed from the back surface of the substrate 10 below the source electrode 20 and the source terminal electrodes SE1 to SE4 using, for example, the RIE technique. After forming the VIA holes CS11, CS12, CS21, CS22 to CS41, CS42 penetrating through the substrate 10, a back surface metal layer BE is formed on the back surface of the substrate 10 using a vacuum deposition technique or the like, and then the second surface of the substrate 10 is formed. By removing the back metal layer BE and a part of the substrate 10 from the VIA holes CS11, CS12, CS21, CS22 to CS41, CS42 to the end of the substrate 10, the grooves SC11, SC12, SC21, SC22 to SC41, SC42 are removed. May be formed.

  According to the second embodiment, the microwave / millimeter wave / submillimeter wave prevents the generation of bubbles between the substrate and the solder layer, reduces the thermal resistance, and prevents the deterioration of the high frequency characteristics and the decrease in reliability. A band semiconductor device can be provided.

[Other embodiments]
As described above, the present invention has been described according to the first to second embodiments. However, it should be understood that the descriptions and drawings constituting a part of this disclosure are exemplary and limit the present invention. should not do. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

  The semiconductor device of the present invention is not limited to an FET, HEMT, and MESFET, but an amplifying element such as an LDMOS (Laterally Diffused Metal-Oxide-Semiconductor Field Effect Transistor) or a heterojunction bipolar transistor (HBT). Needless to say, the present invention can also be applied to MEMS (Micro Electro Mechanical Systems) elements.

Although the semiconductor device according to the first to second embodiments has been mainly described in the case of a GaN-based HEMT, the semiconductor device is not limited to this, and may be formed of a GaAs-based HEMT. In this case, for example, the substrate 10 is formed of a GaAs substrate, and the HEMT structure is formed of a GaAs layer / aluminum gallium arsenide layer (Al _y Ga _1-y As) (0.1 ≦ y ≦ 1). Also good.

  As described above, the present invention includes various embodiments not described herein.

  The semiconductor device of the present invention can be applied to a wide range of fields such as an internal matching power amplification element, a power MMIC (Monolithic Microwave Integrated Circuit), a microwave power amplifier, a millimeter wave power amplifier, and a high-frequency MEMS element.

10 ... Substrate 12 ... Nitride compound semiconductor layer (GaN epitaxial growth layer)
16: Two-dimensional electron gas (2DEG) layer 18: Aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1)
20 ... Source electrode 22 ... Drain electrode 24 ... Gate electrode 26 ... Source region 28 ... Drain region CS1, CS2, ..., CS4, CS11, CS12, CS21, CS22-CS41, CS42 ... VIA holes SC1, SC2, ..., SC4 SC11, SC12, SC21, SC22 to SC41, SC42 ... trench SE1, SE2, ..., SE4 ... source terminal electrode GE1, GE2, GE3 ... gate terminal electrode DE ... drain terminal electrode AA ... active region BE ... backside metal layer

Claims (20)

A substrate,
A nitride-based compound semiconductor layer disposed on the first surface of the substrate;
An active region disposed on the nitride-based compound semiconductor layer and made of an aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1);
A gate electrode, a source electrode and a drain electrode, each disposed on the active region, each having a plurality of fingers;
The gate electrode, the source electrode, and the drain electrode are disposed on the nitride compound semiconductor layer in a direction in which the gate electrode, the source electrode, and the drain electrode extend, and a plurality of fingers are bundled and formed for each of the gate electrode, the source electrode, and the drain electrode. A gate terminal electrode, a source terminal electrode and a drain terminal electrode;
A VIA hole disposed through the substrate below the source terminal electrode;
A back metal layer disposed on a second surface opposite to the first surface of the substrate and connected to the source terminal electrode via the VIA hole;
And a groove provided from the VIA hole on the second surface of the substrate to the end of the substrate.   The semiconductor device according to claim 1, wherein the groove provided on the second surface of the substrate is formed by removing the back metal layer.   The semiconductor device according to claim 1, wherein the groove provided on the second surface of the substrate is formed by removing the substrate from the second surface of the substrate.   The groove provided in the second surface of the substrate is formed by removing the back metal layer and a part of the substrate from the second surface of the substrate. The semiconductor device described.   The depth of the said groove | channel provided in the 2nd surface of the said board | substrate is 1 micrometer or more, The semiconductor device of any one of Claims 1-4 characterized by the above-mentioned.   The semiconductor device according to claim 1, wherein a width of the groove provided on the second surface of the substrate is 1 μm or more.   The back surface metal layer is any one of an Au layer, a Ti / Au layer, a Ti / W / Au layer, and a Ti / Pt / Au layer. The semiconductor device described.   The substrate includes a SiC substrate, a GaAs substrate, a GaN substrate, a substrate having a GaN epitaxial layer formed on the SiC substrate, a substrate having a GaN epitaxial layer formed on the Si substrate, and a heterojunction epitaxial layer made of GaN / AlGaN on the SiC substrate. 8. The semiconductor device according to claim 1, comprising: a substrate on which GaN is formed; a substrate in which a GaN epitaxial layer is formed on a sapphire substrate; a sapphire substrate; or a diamond substrate. A substrate,
A nitride-based compound semiconductor layer disposed on the first surface of the substrate;
An active region disposed on the nitride-based compound semiconductor layer and made of an aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1);
A gate electrode, a source electrode and a drain electrode, each disposed on the active region, each having a plurality of fingers;
The gate electrode, the source electrode, and the drain electrode are disposed on the nitride compound semiconductor layer in a direction in which the gate electrode, the source electrode, and the drain electrode extend, and a plurality of fingers are bundled and formed for each of the gate electrode, the source electrode, and the drain electrode. A gate terminal electrode, a source terminal electrode and a drain terminal electrode;
A VIA hole disposed under the source electrode and the source terminal electrode;
A back metal layer disposed on the second surface opposite to the first surface of the substrate and connected to the source electrode and the source terminal electrode via the VIA hole;
And a groove provided from the VIA hole on the second surface of the substrate to the end of the substrate.   The semiconductor device according to claim 9, wherein the groove provided on the second surface of the substrate is formed by removing the back metal layer.   The semiconductor device according to claim 9, wherein the groove provided on the second surface of the substrate is formed by removing a part of the substrate from the second surface of the substrate.   The depth of the said groove | channel provided in the 2nd surface of the said board | substrate is 1 micrometer or more, The semiconductor device of any one of Claims 9-11 characterized by the above-mentioned.   12. The semiconductor device according to claim 9, wherein a width of the groove provided on the second surface of the substrate is 1 μm or more.   The back surface metal layer is any one of an Au layer, a Ti / Au layer, a Ti / W / Au layer, and a Ti / Pt / Au layer. The semiconductor device described.   The substrate includes a SiC substrate, a GaAs substrate, a GaN substrate, a substrate having a GaN epitaxial layer formed on the SiC substrate, a substrate having a GaN epitaxial layer formed on the Si substrate, and a heterojunction epitaxial layer made of GaN / AlGaN on the SiC substrate. 15. The semiconductor device according to claim 9, comprising: a substrate on which GaN is formed, a substrate in which a GaN epitaxial layer is formed on a sapphire substrate, a sapphire substrate, or a diamond substrate. Forming a nitride compound semiconductor layer on the first surface of the substrate;
Forming an active region made of an aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) on the nitride-based compound semiconductor layer;
Forming a gate electrode, a source electrode and a drain electrode each having a plurality of fingers on the active region;
On the nitride compound semiconductor layer in a direction in which the gate electrode, the source electrode, and the drain electrode extend, a plurality of fingers are bundled for each of the gate electrode, the source electrode, and the drain electrode, and a gate terminal electrode, Forming a source terminal electrode and a drain terminal electrode;
Forming a VIA hole penetrating the substrate below the source terminal electrode;
Forming a back metal layer connected to the source terminal electrode via the VIA hole on a second surface opposite to the first surface of the substrate;
Forming a groove from the VIA hole on the second surface of the substrate to the end of the substrate.   17. The method of manufacturing a semiconductor device according to claim 16, wherein, in the step of forming the VIA hole, the VIA hole is formed under the source electrode so as to penetrate the substrate.   The method of manufacturing a semiconductor device according to claim 16, wherein the groove provided on the second surface of the substrate is formed by removing the back metal layer.   The semiconductor device according to claim 16, wherein the groove provided in the second surface of the substrate is formed by removing a part of the substrate from the second surface of the substrate. Production method.   The groove formed in the second surface of the substrate is formed by removing the back metal layer and a part of the substrate from the second surface of the substrate. The manufacturing method of the semiconductor device of description.

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