JP2010245350A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device of the microwave/millimeter wave/sub-millimeter band, which has a simple structure, and is easy to manufacture and is reducible in ground inductance. <P>SOLUTION: The semiconductor device includes a nitride-based compound semiconductor layer 12 arranged on a substrate 10, an active region AA arranged on the nitride-based compound semiconductor layer 12 and composed of aluminum gallium nitride layer 18, an element isolation region for mutual element isolation of the active area AA, a gate electrode 24, a source electrode 20 and a drain electrode 22 arranged on the active region AA, gate terminal electrodes GL1 to GL3 and drain terminal electrodes DL1 to DL3 connected to the gate electrode 24 and drain electrode 22 respectively, and arranged on the element isolation region in a direction wherein the gate electrode 24 and drain electrode 22 extend, and end face electrodes SG1 to SG4 arranged on the end face of the substrate 10 in a direction wherein the gate electrode 24, gate electrode 20 and drain electrode 22 are arranged, and connected to the source electrode 20. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device operating in a microwave / millimeter wave / submillimeter wave band capable of reducing ground inductance.

  Field effect transistors (FET) using compound semiconductors such as GaN (Gallium Nitride) have excellent high-frequency characteristics and are widely put into practical use as semiconductor devices that operate in the microwave / millimeter / submillimeter wave bands. Has been.

  A schematic planar pattern configuration of a conventional semiconductor device is expressed as shown in FIG. 7, and a schematic cross-sectional structure along the line II in FIG. 7 is expressed as shown in FIG.

  As shown in FIG. 7, a schematic planar pattern configuration of a conventional semiconductor device includes, for example, a substrate 10 made of SiC, and a gate electrode 24, a source electrode 20 and a drain which are arranged on the substrate 10 and each have a plurality of fingers. The electrode 22 and the gate terminal electrodes GE1, GE2, GE3, the source terminal electrodes SE1, SE2,... Arranged on the substrate 10 and formed by bundling a plurality of fingers for each of the gate electrode 24, the source electrode 20 and the drain electrode 22. , SE4 and drain terminal electrode DE, and end face electrodes SC1, SC2,..., SC4 connected to the source terminal electrodes SE1, SE2,.

  The portion where the gate electrode 24, the source electrode 20 and the drain electrode 22 have a plurality of finger shapes is an active region comprising an AlGaN layer 18 and a two-dimensional electron gas (2DEG) layer 16, as shown in FIG. AA is formed. The 2DEG layer 16 is formed at the interface between the AlGaN layer 18 and the GaN epitaxial growth layer 12. The source electrode 20 and the drain electrode 22 form an ohmic contact with the AlGaN layer 18, and the gate electrode 24 forms a Schottky contact with the AlGaN layer 18.

  In the example of FIG. 7, gate terminal electrodes GE1, GE2, GE3 and source terminal electrodes SE1, SE2,..., SE4 are arranged at one end of the substrate 10, and a drain terminal electrode DE is arranged at the other end.

  7 and 8, end face electrodes SC1, SC2,..., SC4 are formed on the source terminal electrodes SE1, SE2,..., SE4, respectively, and connected to the ground conductor formed on the back surface of the substrate 10. Has been. The end face electrodes SC1, SC2,..., SC4 are composed of, for example, a barrier metal layer 30 made of Ti and a ground metal layer 32 made of Au and formed on the barrier metal layer 30. The reason why such end face electrodes SC1, SC2,..., SC4 are formed on the source electrode 20 and the source terminal electrodes SE1, SE2,..., SE4 is that ground inductance that adversely affects the high frequency characteristics of the semiconductor device is reduced. Because.

  When the circuit element provided on the substrate 10 is grounded, the circuit element and the ground conductor formed on the back surface of the substrate 10 are connected via the end surface electrodes SC1, SC2,..., SC4 formed on the end surface of the substrate 10. Electrically connected.

  The gate terminal electrodes GE1, GE2, and GE3 are connected to the peripheral semiconductor chip by bonding wires, and the drain terminal electrode DE is also connected to the peripheral semiconductor chip by bonding wires.

  On the other hand, in a semiconductor chip having a side metallized portion, a semiconductor device characterized in that at least one of the four side surfaces of the chip is not perpendicular to the chip surface has already been disclosed (for example, Patent Documents). 1).

  The end surface electrodes SC1, SC2,..., SC4 are easy to process, but the gate terminal electrodes GE1, GE2, GE3 that serve as pad electrodes for supplying power to the gate electrode 24 are the same as the source terminal electrodes SE1, SE2,. Since the source electrode 20 and the source terminal electrodes SE1, SE2,..., SE4 are grounded because they are arranged on the ground side, there is a problem that ground inductance cannot be effectively reduced. In addition, instead of grounding by side metallization, a method of forming a ground electrode through a VIA hole from the back side is also disclosed. However, the VIA hole formation for GaN is difficult to manufacture because the hardness of the GaN crystal is high. Accompanied by.

Japanese Patent Laid-Open No. 02-291133

  An object of the present invention is to provide a microwave / millimeter-wave / submillimeter-wave band semiconductor device that has a simple structure and can reduce ground inductance.

According to one aspect of the present invention for achieving the above object, a substrate, a nitride compound semiconductor layer disposed on the substrate, an aluminum gallium nitride layer disposed on the nitride compound semiconductor layer, and An active region made of (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1), an element isolation region for isolating the active region from each other, and the active region surrounded by the element isolation region A gate electrode, a source electrode, and a drain electrode that are disposed, a gate terminal electrode that is connected to the gate electrode and the drain electrode, respectively, and is disposed on the element isolation region in a direction in which the gate electrode and the drain electrode extend; A drain terminal electrode, disposed on an end surface of the substrate in a direction in which the gate electrode, the source electrode, and the drain electrode are disposed; Semiconductor device and a connection end faces electrode.

According to another aspect of the present invention, a substrate, a nitride compound semiconductor layer disposed on the substrate, an aluminum gallium nitride layer (Al _x Ga ₁₋₎ disposed on the nitride compound semiconductor layer, and _x N) (0.1 ≦ x ≦ 1), an element isolation region that isolates the active region from each other, and the active region surrounded by the element isolation region, A gate electrode having a finger, a source electrode, and a drain electrode; and connected to the gate electrode and the drain electrode, respectively, and disposed on the element isolation region in a direction in which the gate electrode and the drain electrode extend; and A gate terminal electrode and a drain terminal electrode formed by bundling a plurality of fingers for each drain electrode, the source electrode and the source electrode A source lead electrode connected through a contact, and an end face electrode disposed on an end face of the substrate in a direction in which the gate electrode, the source electrode and the drain electrode are arranged, and connected to the source lead electrode. A semiconductor device is provided.

  According to the present invention, it is possible to provide a microwave / millimeter wave / submillimeter wave band semiconductor device having a simple structure and capable of reducing ground inductance.

1 is a schematic plan pattern configuration diagram of a semiconductor device according to a first embodiment of the present invention. FIG. FIG. 2 is a schematic cross-sectional structure diagram taken along line II-II in FIG. 1. FIG. 3 is a schematic sectional view taken along line III-III in FIG. 1. FIG. 3 is a schematic cross-sectional structure diagram of Configuration Example 1 of the semiconductor device according to the first embodiment of the invention. FIG. 5 is a schematic cross-sectional structure diagram of Configuration Example 2 of the semiconductor device according to the first embodiment of the invention. FIG. 5 is a schematic cross-sectional structure diagram of Configuration Example 3 of the semiconductor device according to the first embodiment of the invention. The typical plane pattern block diagram of the conventional semiconductor device. FIG. 8 is a schematic cross-sectional structure diagram taken along the line II in FIG. 7.

  Next, an embodiment of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. Further, the embodiments described below exemplify apparatuses and methods for embodying the technical idea of the present invention, and the embodiments of the present invention have the following structure and arrangement of components. It is not something specific. The embodiment of the present invention can be variously modified within the scope of the claims.

[First embodiment]
(Element structure)
A schematic planar pattern configuration of the semiconductor device according to the first embodiment of the present invention is expressed as shown in FIG. 1 is represented as shown in FIG. 2, and the schematic sectional structure along the line III-III in FIG. 1 is represented as shown in FIG. .

As shown in FIGS. 1 to 3, the semiconductor device according to the first embodiment includes a substrate 10, a nitride compound semiconductor layer 12 disposed on the substrate 10, and a nitride compound semiconductor layer 12. And an active region AA made of an aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 18, an element isolation region 34 that isolates the active region AA from each other, and an element isolation The gate electrode 24, the source electrode 20, and the drain electrode 22 disposed on the active area AA surrounded by the region 34, and connected to the gate electrode 24 and the drain electrode 22, respectively, and the direction in which the gate electrode 24 and the drain electrode 22 extend The gate terminal electrodes GL1 to GL3 and the drain terminal electrodes DL1 to DL3, the gate electrode 24, the source electrode 20, Is disposed on the end face direction of the substrate 10 in the electrode 22 is disposed, and a facet electrode SC1~SC4 connected to the source electrode 20.

In addition, as shown in FIGS. 1 to 3, the semiconductor device according to the first embodiment includes a substrate 10, a nitride compound semiconductor layer 12 disposed on the substrate 10, and a nitride compound semiconductor layer. 12, an active region AA made of an aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 18, and an element isolation region 34 that isolates the active region AA from each other, The gate electrode 24, the source electrode 20 and the drain electrode 22 are arranged on the active region AA surrounded by the element isolation region 34 and each have a plurality of fingers, and are connected to the gate electrode 24 and the drain electrode 22, respectively. And a plurality of fingers for each of the gate electrode 24 and the drain electrode 22. The gate terminal electrodes GL1 to GL3 and the drain terminal electrodes DL1 to DL3 that are formed, the source lead electrode SH connected to the source electrode 20 via the source contact CS, the gate electrode 24, the source electrode 20, and the drain electrode 22 End electrodes SC <b> 1 to SC <b> 4 arranged on the end face of the substrate 10 in the arrangement direction and connected to the source lead electrode SH are provided.

  As shown in FIG. 1, the schematic planar pattern configuration of the semiconductor device according to the first embodiment includes a substrate 10, a plurality of gate electrodes 24, a source electrode 20 and a drain electrode 22 disposed on the substrate 10. , Gate terminal electrodes GL1 to GL3 connected to the gate electrode 24, the source electrode 20 and the drain electrode 22, the source lead electrode SH and the drain terminal electrodes DL1 to DL3, respectively, and the plurality of gate electrodes 24, the source electrode 20 and the drain electrode 22 Are provided on the end face of the substrate 10 in the direction in which the electrodes are arranged.

  The gate terminal electrodes GL1 to GL3 and the drain terminal electrodes DL1 to DL3 are arranged in a direction in which the plurality of gate electrodes 24, the source electrode 20, and the drain electrode 22 extend.

  On the other hand, the end surface electrodes SC1 and SC2 are arranged on opposite side surfaces of the chip that do not include the gate terminal electrodes GL1 to GL3 and the drain terminal electrodes DL1 to DL3.

  Similarly, the end face electrodes SC3 and SC4 are arranged on opposite side surfaces of the chip not including the gate terminal electrodes GL1 to GL3 and the drain terminal electrodes DL1 to DL3.

  That is, the end surface electrodes SC1 to SC4 are disposed on both side surfaces of the chip in the direction in which the plurality of gate electrodes 24, the source electrode 20, and the drain electrode 22 are disposed.

  As shown in FIGS. 1 to 3, the end face electrodes SC <b> 1 to SC <b> 4 include a barrier metal layer 30 made of a Ti layer or a Ti / Pt layer, and a grounding metal layer made of an Au layer and disposed on the barrier metal layer 30. 32 and a laminated structure. End face electrodes SC <b> 1 to SC <b> 4 are connected to a ground conductor BE arranged on the back surface of substrate 10.

  As shown in FIGS. 1 and 3, the source lead electrode SH is disposed on the plurality of gate electrodes 24, the source electrode 20, and the drain electrode 22 via an interlayer insulating film 36. The interlayer insulating film 36 is, for example, a CVD oxide film, a tetraethoxysilane (TEOS) film, a silicon nitride film, an oxynitride film (SiON), or the like formed by a chemical vapor deposition (CVD) method. Can be used.

  The source lead electrode SH is connected to the source electrode 20 via the source contact CS as shown in FIGS.

  As shown in FIGS. 1 to 3, the end face electrode SC1 is connected to the source lead electrode SH and the source electrode 20 (S1), and the end face electrode SC2 is connected to the source lead electrode SH and the source electrode 20 (S5). Yes. Similarly, the end face electrode SC3 is connected to the source lead electrode SH and the source electrode 20 (S1), and the end face electrode SC4 is connected to the source lead electrode SH and the source electrode 20 (S5).

  Thus, since the source electrode 20 is directly connected to the ground metal layer 32 provided on both side surfaces of the opposing chip, the ground inductance can be effectively reduced, and negative feedback due to the ground inductance can be reduced. Can do.

  Further, in FIG. 1, an electrical short circuit is prevented at the intersection of the drain lead electrode (upper layer) and the gate lead electrode (lower layer) indicated by A by an air gap structure. Similarly, the intersection of the gate lead electrode (upper layer) and the drain lead electrode (lower layer) indicated by B prevents an electrical short circuit by the air gap structure. The gate terminal electrodes GL1 to GL3 are connected to the corresponding gate lead electrodes via the gate contacts CG.

1 to 3, an aluminum gallium nitride layer (Al _x Ga ₁₎ between the gate electrode 24 and the source electrode 20, between the gate electrode 24 and the drain electrode 22, and under the gate electrode 24, the source electrode 20 and the drain electrode 22. _-x N) (0.1 ≦ x ≦ 1) 18 constitutes the active area AA.

  In FIG. 1, the schematic cross-sectional structure taken along the line IV-IV corresponds to Configuration Example 1 to Configuration Example 3 of the semiconductor device according to the first embodiment shown in FIGS. 4 to 6.

(Configuration example 1)
As shown in FIG. 4, the semiconductor device according to the first embodiment includes a substrate 10, a GaN epitaxial growth layer 12 disposed on the substrate 10, and an aluminum gallium nitride layer (on the GaN epitaxial growth layer 12). Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 18 and a source electrode disposed on the aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 18 20, a gate electrode 24 and a drain electrode 22. A 2DEG layer 16 is formed at the interface with the aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 18 on the GaN epitaxial growth layer 12. In the semiconductor device shown in FIG. 4, a high electron mobility transistor (HEMT) is configured.

(Configuration example 2)
As shown in FIG. 5, another configuration example of the semiconductor device according to the first embodiment is disposed on the substrate 10, the GaN epitaxial growth layer 12 disposed on the substrate 10, and the GaN epitaxial growth layer 12. A source region 26 and a drain region 28; a source electrode 20 disposed on the source region 26; a gate electrode 24 disposed on the GaN epitaxial growth layer 12; and a drain electrode 22 disposed on the drain region 28.

  A Schottky contact is formed at the interface between the GaN epitaxial growth layer 12 and the gate electrode 24. In the semiconductor device of Configuration Example 2 shown in FIG. 4, a metal-semiconductor field effect transistor (MESFET) is configured.

(Configuration example 3)
As shown in FIG. 6, another configuration example of the semiconductor device according to the first embodiment is arranged on the substrate 10, the GaN epitaxial growth layer 12 disposed on the substrate 10, and the GaN epitaxial growth layer 12. On the aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 18 and the aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 18 A source electrode 20 and a drain electrode 22 disposed on the gate electrode 24; a gate electrode 24 disposed in a recess on the aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 18; And a gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 18. A 2DEG layer 16 is formed at the interface with the aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 18 on the GaN epitaxial growth layer 12. The semiconductor device illustrated in FIG. 6 corresponds to a HEMT.

As shown in FIGS. 1 to 3 and 4, the semiconductor device according to the first embodiment includes a substrate 10, a nitride compound semiconductor layer 12 disposed on the substrate 10, and a nitride compound semiconductor. An active region AA disposed on the layer 12 and made of an aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 18, and an element isolation region 34 that isolates the active region AA from each other; The gate electrode 24, the source electrode 20, and the drain electrode 22 disposed on the active region AA surrounded by the element isolation region 34, and the element isolation region 34, and connected to the gate electrode 24 and the drain electrode 22, respectively. Gate terminal electrodes GL1 to GL3 and drain terminal electrodes DL1 to DL3, a source lead electrode SH connected to the source electrode 20 via the source contact CS, It is connected to the over scan extraction electrode SH, comprising a plurality of gate electrodes 24 and an end face electrode SC1~SC4 disposed on the end face direction of the substrate 10 where the source electrode 20 and drain electrode 22 are disposed.

The element isolation region 34 is formed up to a part in the depth direction of the aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 18 and the nitride-based compound semiconductor layer 12.

The element isolation region 34 is formed by ion implantation. As the ion species, for example, nitrogen (N), argon (Ar), or the like can be applied. Further, the dose accompanying ion implantation is, for example, about 1 × 10 ¹⁴ (ions / cm ² ), and the acceleration energy is, for example, about 100 keV to 200 keV.

A passivation insulating layer (not shown) is formed on the element isolation region 34 and the device surface. As this insulating layer, for example, a nitride film, an alumina (Al ₂ O ₃ ) film, an oxide film (SiO ₂ ), an oxynitride film (SiON) or the like deposited by PECVD (Plasma Enhanced Chemical Vapor Deposition) method is formed. be able to.

  The source electrode 20 and the drain electrode 22 are made of, for example, Ti / Al.

  The gate electrode 24 can be formed of, for example, Ni / Au.

  The substrate 10 includes a SiC substrate, a GaAs substrate, a GaN substrate, a substrate having a GaN epitaxial layer formed on the SiC substrate, a substrate having a GaN epitaxial layer formed on the Si substrate, and a heterojunction made of GaN / AlGaN on the SiC substrate. Any of a substrate on which an epitaxial layer is formed, a substrate on which a GaN epitaxial layer is formed on a sapphire substrate, a sapphire substrate, or a diamond substrate may be provided.

  According to the semiconductor device according to the first embodiment, it is possible to provide a high-performance semiconductor device in which extra routing is not required when the source electrode 20 is grounded and the ground inductance is effectively reduced.

  The semiconductor device according to the first embodiment can provide a microwave / millimeter wave / submillimeter wave band semiconductor device that has a simple structure, is easy to manufacture, and can reduce ground inductance. .

[Other embodiments]
As described above, the present invention has been described according to the first embodiment. However, it should be understood that the descriptions and drawings constituting a part of this disclosure are illustrative and limit the present invention. Absent. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

  The semiconductor device of the present invention is not limited to an FET, HEMT, and MESFET, but an amplifying element such as an LDMOS (Lateral Doped Metal-Oxide-Semiconductor Field Effect Transistor) or a heterojunction bipolar transistor (HBT). Needless to say, the present invention can also be applied to MEMS (Micro Electro Mechanical Systems) elements.

  As described above, the present invention includes various embodiments that are not described herein.

  The semiconductor device of the present invention can be applied to a wide range of fields such as an internal matching power amplification element, a power MMIC (Monolithic Microwave Integrated Circuit), a microwave power amplifier, a millimeter wave power amplifier, and a high-frequency MEMS element.

10 ... Substrate 12 ... Nitride compound semiconductor layer (GaN epitaxial growth layer)
16: Two-dimensional electron gas (2DEG) layer 18: Aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1)
20, S1, S2, ..., S5 ... Source electrode 22, D1, D2, ..., D4 ... Drain electrode 24, G1, G2, ..., G8 ... Gate electrode 26 ... Source region 28 ... Drain region 30 ... Barrier metal layer 32 ... metal layer 34 for grounding ... element isolation region 36 ... interlayer insulating films SC1, SC2, ..., SC4 ... end face electrodes DL1, DL2, DL3 ... drain terminal electrodes GL1, GL2, GL3 ... gate terminal electrodes AA ... active region CS ... source Contact BE ... Grounding conductor

Claims (5)

A substrate,
A nitride compound semiconductor layer disposed on the substrate;
An active region disposed on the nitride-based compound semiconductor layer and made of an aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1);
An element isolation region for isolating the active regions from each other;
A gate electrode, a source electrode, and a drain electrode disposed on the active region surrounded by the element isolation region;
A gate terminal electrode and a drain terminal electrode connected to the gate electrode and the drain electrode, respectively, and disposed on the element isolation region in a direction in which the gate electrode and the drain electrode extend;
A semiconductor device comprising: an end face electrode disposed on an end face of the substrate in a direction in which the gate electrode, the source electrode, and the drain electrode are disposed, and connected to the source electrode. A substrate,
A nitride compound semiconductor layer disposed on the substrate;
An active region disposed on the nitride-based compound semiconductor layer and made of an aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1);
An element isolation region for isolating the active regions from each other;
A gate electrode, a source electrode and a drain electrode, each disposed on the active region surrounded by the element isolation region, each having a plurality of fingers;
Connected to the gate electrode and the drain electrode, respectively, disposed on the element isolation region in the extending direction of the gate electrode and the drain electrode, and formed by bundling a plurality of fingers for each of the gate electrode and the drain electrode Gate terminal electrode and drain terminal electrode,
A source extraction electrode connected to the source electrode via a source contact;
A semiconductor device comprising: an end face electrode disposed on an end face of the substrate in a direction in which the gate electrode, the source electrode, and the drain electrode are disposed, and connected to the source lead electrode.   The semiconductor device according to claim 1, wherein the end face electrode includes a barrier metal layer and a ground metal layer disposed on the barrier metal layer.   4. The semiconductor device according to claim 3, wherein the barrier metal layer is made of a Ti layer or a Ti / Pt layer, and the ground metal layer is made of an Au layer.   The substrate includes a SiC substrate, a GaAs substrate, a GaN substrate, a substrate having a GaN epitaxial layer formed on the SiC substrate, a substrate having a GaN epitaxial layer formed on the Si substrate, and a heterojunction epitaxial layer made of GaN / AlGaN on the SiC substrate. 5. The semiconductor device according to claim 1, further comprising: a substrate on which GaN is formed, a substrate on which a GaN epitaxial layer is formed on a sapphire substrate, a sapphire substrate, or a diamond substrate.

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