JP2010245351A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device of the microwave/millimeter wave/sub-millimeter band, which eliminates unnecessary routing when a source electrode is connected, has a simple structure, and is effectively reducible in ground inductance. <P>SOLUTION: The semiconductor device includes a nitride-based compound semiconductor layer 12 arranged on a substrate 10, an active region AA arranged on the nitride-based compound semiconductor layer 12 and composed of aluminum gallium nitride layer 18, a gate electrode 24, a source electrode 20 and a drain electrode 22 arranged on the active region AA, gate terminal electrodes GL1, GL2 and drain terminal electrodes DL1, DL2 connected to the gate electrode 24 and drain electrode 22 respectively, and arranged on the nitride-based compound semiconductor layer 12 in a direction wherein the gate electrode 24, source electrode 20 and drain electrode 22 extend, and an end face electrode SC arranged on the end face of the substrate 10 in the other direction wherein the gate electrode 24, gate electrode 20 and drain electrode 22 extend, and connected to the source electrode 20. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device operating in a microwave / millimeter wave / submillimeter wave band capable of reducing ground inductance.

  Field effect transistors (FET) using compound semiconductors such as GaN (Gallium Nitride) have excellent high-frequency characteristics and are widely put into practical use as semiconductor devices that operate in the microwave / millimeter / submillimeter wave bands. Has been.

  A schematic planar pattern configuration of a conventional semiconductor device is expressed as shown in FIG. 7, and a schematic cross-sectional structure along the line II in FIG. 7 is expressed as shown in FIG.

  As shown in FIGS. 7 and 8, a schematic planar pattern configuration of a conventional semiconductor device includes, for example, a substrate 10 made of SiC, a gate electrode 24 arranged on the substrate 10 and having a plurality of fingers, and a source electrode, respectively. 20 and the drain electrode 22, and the gate terminal electrode GE1, GE2, GE3, the source terminal electrode SE1, which are arranged on the substrate 10 and formed by bundling a plurality of fingers for each of the gate electrode 24, the source electrode 20 and the drain electrode 22. SE2 and drain terminal electrode DE, and end face electrodes SC1, SC2,..., SC4 connected to source terminal electrodes SE1, SE2,.

  The portion where the gate electrode 24, the source electrode 20 and the drain electrode 22 have a plurality of finger shapes is an active region comprising an AlGaN layer 18 and a two-dimensional electron gas (2DEG) layer 16, as shown in FIG. AA is formed. The 2DEG layer 16 is formed at the interface between the AlGaN layer 18 and the GaN epitaxial growth layer 12. The source electrode 20 and the drain electrode 22 form an ohmic contact with the AlGaN layer 18, and the gate electrode 24 forms a Schottky contact with the AlGaN layer 18.

  In the example of FIG. 7, gate terminal electrodes GE1, GE2, GE3 and source terminal electrodes SE1, SE2,..., SE4 are arranged at one end of the substrate 10, and a drain terminal electrode DE is arranged at the other end.

  7 and 8, end face electrodes SC1, SC2,..., SC4 are formed on the source terminal electrodes SE1, SE2,..., SE4, respectively, and the ground conductor BE formed on the back surface of the substrate 10 It is connected. The end face electrodes SC1, SC2,..., SC4 are composed of, for example, a barrier metal layer 30 made of Ti and a ground metal layer 32 made of Au and formed on the barrier metal layer 30. The reason why such end face electrodes SC1, SC2,..., SC4 are formed on the source electrode 20 and the source terminal electrodes SE1, SE2,..., SE4 is that ground inductance that adversely affects the high frequency characteristics of the semiconductor device is reduced. Because.

  When the circuit element provided on the substrate 10 is grounded, the circuit element and the ground conductor BE formed on the back surface of the substrate 10 via the end surface electrodes SC1, SC2,..., SC4 formed on the end surface of the substrate 10 Are electrically connected.

  The gate terminal electrodes GE1, GE2, and GE3 are connected to the peripheral semiconductor chip by bonding wires, and the drain terminal electrode DE is also connected to the peripheral semiconductor chip by bonding wires.

  On the other hand, in a semiconductor chip having a side metallized portion, a semiconductor device characterized in that at least one of the four side surfaces of the chip is not perpendicular to the chip surface has already been disclosed (for example, Patent Documents). 1).

  The end surface electrodes SC1, SC2,..., SC4 are easy to process, but the gate terminal electrodes GE1, GE2, GE3 that serve as pad electrodes for supplying power to the gate electrode 24 are the same as the source terminal electrodes SE1, SE2,. Since the source electrode 20 and the source terminal electrodes SE1, SE2,..., SE4 are grounded because they are arranged on the ground side, there is a problem that ground inductance cannot be effectively reduced. In addition, instead of grounding by side metallization, a method of forming a ground electrode through a VIA hole from the back side is also disclosed. However, the VIA hole formation for GaN is difficult to manufacture because the hardness of the GaN crystal is high. Accompanied by.

Japanese Patent Laid-Open No. 02-291133

  An object of the present invention is to provide a microwave / millimeter-wave / submillimeter-wave band semiconductor device that does not require extra routing when connecting source electrodes, has a simple structure, and can effectively reduce ground inductance. is there.

According to one aspect of the present invention for achieving the above object, a substrate, a nitride compound semiconductor layer disposed on the substrate, an aluminum gallium nitride layer disposed on the nitride compound semiconductor layer, and An active region made of (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1), a gate electrode, a source electrode, and a drain electrode disposed on the active region, and the gate electrode and the drain electrode, respectively. A gate terminal electrode and a drain terminal electrode disposed on the nitride-based compound semiconductor layer in one direction in which the gate electrode, the source electrode, and the drain electrode extend, and the gate electrode, the source electrode And an end face electrode disposed on the nitride-based compound semiconductor layer in the other direction in which the drain electrode extends and connected to the source electrode Conductor device is provided.

According to another aspect of the present invention, a substrate, a nitride compound semiconductor layer disposed on the substrate, an aluminum gallium nitride layer (Al _x Ga ₁₋₎ disposed on the nitride compound semiconductor layer, and _x N) (0.1 ≦ x ≦ 1), a gate electrode, a source electrode and a drain electrode which are arranged on the active region and each have a plurality of fingers, the gate electrode, the source electrode and A gate terminal electrode and a drain terminal electrode which are disposed on the nitride-based compound semiconductor layer in one direction in which the drain electrode extends, and a plurality of fingers are bundled and connected to each of the gate electrode and the drain electrode; The gate electrode, the source electrode, and the drain electrode are disposed on the end surface of the substrate in the other direction in which the gate electrode extends, and are connected to the source electrode. Semiconductor device comprising an end face electrode.

  According to the present invention, it is possible to provide a microwave / millimeter-wave / submillimeter-wave band semiconductor device that has no extra routing when connecting source electrodes, has a simple structure, and can reduce ground inductance.

1 is a schematic plan pattern configuration diagram of a semiconductor device according to a first embodiment of the present invention. FIG. FIG. 2 is a schematic cross-sectional structure diagram taken along line II-II in FIG. 1. FIG. 3 is a schematic cross-sectional structure diagram of Configuration Example 1 of the semiconductor device according to the first embodiment of the invention. FIG. 5 is a schematic cross-sectional structure diagram of Configuration Example 2 of the semiconductor device according to the first embodiment of the invention. FIG. 5 is a schematic cross-sectional structure diagram of Configuration Example 3 of the semiconductor device according to the first embodiment of the invention. The typical plane pattern block diagram of the semiconductor device which concerns on the 2nd Embodiment of this invention. The typical plane pattern block diagram of the conventional semiconductor device. FIG. 8 is a schematic cross-sectional structure diagram taken along the line II in FIG. 7.

  Next, an embodiment of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. Further, the embodiments described below exemplify apparatuses and methods for embodying the technical idea of the present invention, and the embodiments of the present invention have the following structure and arrangement of components. It is not something specific. The embodiment of the present invention can be variously modified within the scope of the claims.

[First embodiment]
(Element structure)
A schematic planar pattern configuration of the semiconductor device according to the first embodiment of the present invention is expressed as shown in FIG. Moreover, the schematic cross-sectional structure along the II-II line of FIG. 1 is represented as shown in FIG.

As shown in FIGS. 1 to 2, the semiconductor device according to the first embodiment includes a substrate 10, a nitride compound semiconductor layer 12 disposed on the substrate 10, and a nitride compound semiconductor layer 12. disposed, aluminum gallium nitride layer _{(Al x Ga 1-x N} ) (0.1 ≦ x ≦ 1) and the active region AA consisting 18, the gate electrode 24 disposed on the active region AA, a source electrode 20 and The drain electrode 22 is connected to the gate electrode 24 and the drain electrode 22, respectively, and the gate terminal electrode disposed on the nitride-based compound semiconductor layer 12 in one direction in which the gate electrode 24, the source electrode 20 and the drain electrode 22 extend. GL1, GL2 and drain terminal electrodes DL1, DL2 and the nitride compound half in the other direction in which gate electrode 24, source electrode 20 and drain electrode 22 extend Disposed on the body layer 12, and a end surface electrodes SC connected to the source electrode 20.

In addition, as shown in FIGS. 1 to 2, the semiconductor device according to the first embodiment includes a substrate 10, a nitride compound semiconductor layer 12 disposed on the substrate 10, and a nitride compound semiconductor layer. 12 and an active region AA composed of an aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 18 and a plurality of fingers each disposed on the active region AA The gate electrode 24, the source electrode 20 and the drain electrode 22, and the gate electrode 24, the source electrode 20 and the drain electrode 22 are disposed on the nitride-based compound semiconductor layer 12 in one direction in which the gate electrode 24, the source electrode 20 and the drain electrode 22 extend. A plurality of fingers are bundled and connected to each other, and the gate terminal electrodes GL1 and GL2 and the drain terminal electrodes DL1 and DL2, the gate electrode 24, and the source electrode 0 and the drain electrode 22 is disposed on the end surface of the other direction of the substrate 10 to be stretched, and a end surface electrodes SC connected to the source electrode 20.

  The gate terminal electrodes GL1 and GL2 and the drain terminal electrodes DL1 and DL2 are arranged in a direction in which the plurality of gate electrodes 24, the source electrode 20, and the drain electrode 22 extend.

  On the other hand, the end surface electrode SC is a side surface of one side of the substrate 10 that does not include the gate terminal electrodes GL1 and GL2 and the drain terminal electrodes DL1 and DL2, and the other end surface on which the gate electrode 24, the source electrode 20, and the drain electrode 22 extend. Arranged on the end face of the substrate 10 in the direction.

  The end face electrode SC is formed in common to the plurality of source electrodes 20 (S1) to 20 (S9) and is electrically connected in common. Since the semiconductor device according to the first embodiment does not include the gate terminal electrode GL and the drain terminal electrode DL on one side of the substrate 10 on which the end face electrode SC is disposed, as shown in FIGS. For example, the possibility that the source electrode 20 and the gate terminal electrode GL are short-circuited is reduced. Therefore, it is not necessary to separately form the end face electrodes as in the conventional example shown in FIG. 7, and the structure is simplified.

  As shown in FIG. 2, the end face electrode SC has a laminated structure of a barrier metal layer 30 made of a Ti layer or a Ti / Pt layer and a grounding metal layer 32 made of an Au layer and disposed on the barrier metal layer 30. Is formed by. The end face electrode SC is connected to the ground conductor BE arranged on the back surface of the substrate 10.

  Thus, the end face electrode SC is a side surface of one side of the substrate 10 not including the gate terminal electrodes GL1 and GL2 and the drain terminal electrodes DL1 and DL2, and the other side on which the gate electrode 24, the source electrode 20 and the drain electrode 22 extend. Therefore, when connecting to the source electrode 20, there is no extra routing, the ground inductance can be effectively reduced, and negative feedback associated with the ground inductance can be reduced. it can.

  Further, in FIG. 1, an electrical short circuit is prevented at the intersection of the drain lead electrode (upper layer) and the gate lead electrode (lower layer) indicated by A by an air gap structure. Similarly, the intersection of the gate lead electrode (upper layer) and the drain lead electrode (lower layer) indicated by B prevents an electrical short circuit by the air gap structure. The gate terminal electrodes GL1 and GL2 are connected to the corresponding gate lead electrodes via the gate contacts CG.

1 to 2, an aluminum gallium nitride layer (Al _x Ga ₁₎ between the gate electrode 24 and the source electrode 20, between the gate electrode 24 and the drain electrode 22, and under the gate electrode 24, the source electrode 20 and the drain electrode 22. _-x N) (0.1 ≦ x ≦ 1) 18 constitutes the active area AA.

  In FIG. 1, a schematic cross-sectional structure taken along line III-III corresponds to Configuration Example 1 to Configuration Example 3 of the semiconductor device according to the first embodiment shown in FIGS. 3 to 5.

(Configuration example 1)
As illustrated in FIG. 3, the semiconductor device according to the first embodiment includes a substrate 10, a GaN epitaxial growth layer 12 disposed on the substrate 10, and an aluminum gallium nitride layer (on the GaN epitaxial growth layer 12). Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 18 and a source electrode disposed on the aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 18 20, a gate electrode 24 and a drain electrode 22. A 2DEG layer 16 is formed at the interface with the aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 18 on the GaN epitaxial growth layer 12. In the semiconductor device shown in FIG. 3, a high electron mobility transistor (HEMT) is configured.

(Configuration example 2)
As shown in FIG. 4, another configuration example of the semiconductor device according to the first embodiment is disposed on the substrate 10, the GaN epitaxial growth layer 12 disposed on the substrate 10, and the GaN epitaxial growth layer 12. A source region 26 and a drain region 28; a source electrode 20 disposed on the source region 26; a gate electrode 24 disposed on the GaN epitaxial growth layer 12; and a drain electrode 22 disposed on the drain region 28.

  A Schottky contact is formed at the interface between the GaN epitaxial growth layer 12 and the gate electrode 24. In the semiconductor device of Configuration Example 2 shown in FIG. 4, a metal-semiconductor field effect transistor (MESFET) is configured.

(Configuration example 3)
Still another configuration example of the semiconductor device according to the first embodiment includes a substrate 10, a GaN epitaxial growth layer 12 disposed on the substrate 10, and a GaN epitaxial growth layer 12 as illustrated in FIG. On the aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 18 and the aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 18 A source electrode 20 and a drain electrode 22 disposed on the gate electrode 24; a gate electrode 24 disposed in a recess on the aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 18; And a gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 18. A 2DEG layer 16 is formed at the interface with the aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 18 on the GaN epitaxial growth layer 12. The semiconductor device illustrated in FIG. 5 corresponds to a HEMT.

  The source electrode 20 and the drain electrode 22 are made of, for example, Ti / Al.

  The gate electrode 24 can be formed of, for example, Ni / Au.

  The substrate 10 includes a SiC substrate, a GaAs substrate, a GaN substrate, a substrate having a GaN epitaxial layer formed on the SiC substrate, a substrate having a GaN epitaxial layer formed on the Si substrate, and a heterojunction made of GaN / AlGaN on the SiC substrate. Any of a substrate on which an epitaxial layer is formed, a substrate on which a GaN epitaxial layer is formed on a sapphire substrate, a sapphire substrate, or a diamond substrate may be provided.

In the above embodiment, the nitride-based compound semiconductor layer 12 other than the active area AA is used as an electrically inactive element isolation region. As another method for forming the element isolation region, aluminum nitride is used. The gallium layer (Al _x Ga ₁ -xN) (0.1 ≦ x ≦ 1) 18 and the nitride-based compound semiconductor layer 12 may be formed by ion implantation up to a part in the depth direction. As the ion species, for example, nitrogen (N), argon (Ar), or the like can be applied. The dose accompanying ion implantation is, for example, about 1 × 10 ¹⁴ (ions / cm ² ), and the acceleration energy is, for example, about 100 keV to 200 keV.

A passivation insulating layer (not shown) is formed on the element isolation region and the device surface. As this insulating layer, for example, a nitride film, an alumina (Al ₂ O ₃ ) film, an oxide film (SiO ₂ ), an oxynitride film (SiON) or the like deposited by PECVD (Plasma Enhanced Chemical Vapor Deposition) method is formed. be able to.

  According to the semiconductor device according to the first embodiment, it is possible to provide a high-performance semiconductor device in which extra routing is not required when the source electrode 20 is grounded and the ground inductance is effectively reduced.

  The semiconductor device according to the first embodiment can provide a microwave / millimeter wave / submillimeter wave band semiconductor device that has a simple structure, is easy to manufacture, and can reduce ground inductance. .

[Second Embodiment]
The schematic planar pattern configuration of the semiconductor device according to the second embodiment is such that the planar pattern of the semiconductor device according to the first embodiment is arranged at the center of the substrate 10 as shown in FIG. It has a configuration that is folded up and down around the pattern portions of the terminal electrodes DL1 and DL2 and the gate terminal electrodes GL1 and GL2.

  The semiconductor device according to the second embodiment is different from the semiconductor device according to the first embodiment only in the planar pattern configuration, and the cross-sectional structure in the vicinity of the end surface electrodes SC1 and SC2 corresponding to FIG. Since it is the same as that of 1st Embodiment, the overlapping description is abbreviate | omitted.

  6, as in FIG. 1, the schematic cross-sectional structure of the semiconductor device is the same as that of Configuration Example 1 to Configuration Example 3 of the semiconductor device according to the first embodiment shown in FIGS. 3 to 5. Therefore, explanation is omitted.

  The end face electrodes SC1 and SC2 are disposed on two opposing sides of the substrate 10, and the drain terminal electrodes DL1 and DL2 and the gate terminal electrodes GL1 and GL2 are disposed in the center of the substrate 10. The gate electrode 24 having a plurality of fingers, the source electrode 20 and the drain electrode 22 are arranged in parallel in two systems in a direction parallel to the two opposite sides of the substrate 10 on which the end face electrodes SC1 and SC2 are arranged. In addition, the drain terminal electrodes DL1 and DL2 and the gate terminal electrodes GL1 and GL2 are connected by bundling the gate electrode 24 and the drain electrode 22 each having a plurality of fingers in common in the two systems folded up and down.

  In the semiconductor device according to the second embodiment, the longitudinal pattern lengths of the gate electrode 24, the source electrode 20, and the drain electrode 22 may be the same as those in the first embodiment. Further, the pattern length is set shorter as the operating frequency becomes higher, such as microwave / millimeter wave / submillimeter wave. For example, in the millimeter wave band, the pattern length is about 25 μm to 50 μm.

  In the second embodiment, the gate electrode 24, the source electrode 20, and the drain electrode 22 having a plurality of fingers are 2 in a direction parallel to the two opposite sides of the substrate 10 on which the end face electrodes SC 1 and SC 2 are disposed. Although the example arrange | positioned in system | strain parallel is disclosed, it is not limited to 2 systems | systems, You may arrange | position in multiple systems and a matrix form via a common source electrode.

  According to the semiconductor device according to the second embodiment, it is possible to provide a high-performance semiconductor device in which extra routing is not required when the source electrode 20 is grounded and the ground inductance is effectively reduced.

  According to the semiconductor device of the second embodiment, it is possible to provide a microwave / millimeter wave / submillimeter wave band semiconductor device that has a simple structure, is easy to manufacture, and can reduce ground inductance. .

[Other embodiments]
As described above, the present invention has been described according to the first embodiment. However, it should be understood that the descriptions and drawings constituting a part of this disclosure are illustrative and limit the present invention. Absent. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

  The semiconductor device of the present invention is not limited to an FET, HEMT, and MESFET, but an amplifying element such as an LDMOS (Lateral Doped Metal-Oxide-Semiconductor Field Effect Transistor) or a heterojunction bipolar transistor (HBT). Needless to say, the present invention can also be applied to MEMS (Micro Electro Mechanical Systems) elements.

  As described above, the present invention includes various embodiments that are not described herein.

  The semiconductor device of the present invention can be applied to a wide range of fields such as an internal matching power amplification element, a power MMIC (Monolithic Microwave Integrated Circuit), a microwave power amplifier, a millimeter wave power amplifier, and a high-frequency MEMS element.

10 ... Substrate 12 ... Nitride compound semiconductor layer (GaN epitaxial growth layer)
16: Two-dimensional electron gas (2DEG) layer 18: Aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1)
20, S1, S2, ..., S9 ... Source electrodes 22, D1, D2, ..., D8 ... Drain electrodes 24, G1, G2, ..., G16 ... Gate electrodes 26 ... Source regions 28 ... Drain regions 30 ... Barrier metal layers 32 ... metal layer 34 for grounding ... element isolation region 36 ... interlayer insulating films SC, SC1, SC2 ... end face electrodes DL, DL1, DL2 ... drain terminal electrodes GL, GL1, GL2 ... gate terminal electrodes AA ... active region CG ... gate contact A , B ... Intersection

Claims (7)

A substrate,
A nitride compound semiconductor layer disposed on the substrate;
An active region disposed on the nitride-based compound semiconductor layer and made of an aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1);
A gate electrode, a source electrode and a drain electrode disposed on the active region;
A gate terminal electrode and a drain terminal electrode connected to the gate electrode and the drain electrode, respectively, and disposed on the nitride-based compound semiconductor layer in one direction in which the gate electrode, the source electrode, and the drain electrode extend; ,
A semiconductor device comprising: an end face electrode disposed on the nitride-based compound semiconductor layer in the other direction in which the gate electrode, the source electrode, and the drain electrode extend, and connected to the source electrode. A substrate,
A nitride compound semiconductor layer disposed on the substrate;
An active region disposed on the nitride-based compound semiconductor layer and made of an aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1);
A gate electrode, a source electrode and a drain electrode, each disposed on the active region, each having a plurality of fingers;
A gate terminal disposed on the nitride-based compound semiconductor layer in one direction in which the gate electrode, the source electrode, and the drain electrode extend, and a plurality of fingers being bundled and connected to each of the gate electrode and the drain electrode An electrode and a drain terminal electrode;
A semiconductor device comprising: an end face electrode disposed on an end face of the substrate in the other direction in which the gate electrode, the source electrode, and the drain electrode extend, and connected to the source electrode.   The end face electrode is disposed on two opposing sides of the substrate, the drain terminal electrode and the gate terminal electrode are disposed in a central portion of the substrate, and the gate electrode having a plurality of fingers, the source electrode, and the The semiconductor device according to claim 2, wherein the drain electrode is arranged in parallel in two systems in a direction parallel to the two sides.   4. The semiconductor according to claim 3, wherein the drain terminal electrode and the gate terminal electrode are connected together by bundling the gate electrode and the drain electrode each having a plurality of fingers in common in the two systems. apparatus.   5. The semiconductor device according to claim 1, wherein the end face electrode includes a barrier metal layer and a ground metal layer disposed on the barrier metal layer. 6.   6. The semiconductor device according to claim 5, wherein the barrier metal layer is made of a Ti layer or a Ti / Pt layer, and the grounding metal layer is made of an Au layer.   The substrate includes a SiC substrate, a GaAs substrate, a GaN substrate, a substrate having a GaN epitaxial layer formed on the SiC substrate, a substrate having a GaN epitaxial layer formed on the Si substrate, and a heterojunction epitaxial layer made of GaN / AlGaN on the SiC substrate. 7. The semiconductor device according to claim 1, comprising: a substrate on which GaN is formed, a substrate on which a GaN epitaxial layer is formed on a sapphire substrate, a sapphire substrate, or a diamond substrate.

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