JP2007128994A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device including a via hole structure easy to form, even if a semiconductor substrate difficult to work on such as SiC or sapphire is used. <P>SOLUTION: A first conductive semiconductor layer and a second highly resistive semiconductor layer are laminated on a conductive or non-conductive semiconductor substrate. A recess to the first semiconductor layer from the surface of the semiconductor substrate, and another recess to the first semiconductor layer from the backside of the semiconductor substrate, are formed. By forming lines in the recesses, an electrode on the surface of the semiconductor substrate is connected with an electrode on the backside via the first semiconductor layer. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a via hole structure semiconductor device that connects a surface electrode formed on a semiconductor substrate surface to a back electrode formed on a semiconductor substrate back surface.

A general formula of III-V nitride semiconductor, that is, gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), etc. is Al _x Ga _1-xy In _y N (where 0 ≦ x ≦ 1, 0 The mixed crystal represented by ≦ y ≦ 1) has a wide band gap and a direct transition type band structure, and its application to a short wavelength optical element has been put to practical use by taking advantage of the feature. On the other hand, taking advantage of the high breakdown electric field strength and saturation electron velocity of III-V nitride semiconductors, application to high-speed and high-power electronic devices has been energetically studied.

In particular, a two-dimensional electron gas (hereinafter, 2DEG) formed at the interface between an Al _x Ga _1-x N layer (where 0 <x ≦ 1) and a GaN layer epitaxially grown on a semi-insulating substrate. Hetero-junction field effect transistors (hereinafter referred to as “HFETs”) are being developed as high-power devices and high-frequency devices. This HFET has 10 ¹³ cm ⁻ due to large spontaneous polarization and piezoelectric polarization caused by the crystal structure (Wurz structure) of the III-V nitride semiconductor in addition to the supply of electrons from the carrier supply layer (N-type AlGaN layer). ^{A 2} DEG density greater than ² has been achieved. This is about an order of magnitude larger than conventional AlGaAs / GaAs HFETs. For this reason, the III-V nitride semiconductor HFET can be expected to have a higher drain current density than the GaAs HFET, and an element having a maximum drain current exceeding 1 A / mm has been reported (see Non-Patent Document 1). ).

  Further, since the group III-V nitride semiconductor has a high breakdown electric field strength, it exhibits high breakdown voltage characteristics, and it is easy to set the breakdown voltage between the source and drain electrodes to 100 V or more (see Non-Patent Document 1).

  As described above, since it is possible to expect electrical characteristics exhibiting a high breakdown voltage and a high current density, a semiconductor device made of a III-V nitride semiconductor centering on an HFET is used as a high-frequency element and with a smaller design dimension than the conventional one. Applications are being studied as devices that can handle high power.

  However, semiconductor devices made of III-V nitride semiconductors are promising as high-frequency, high-power or high-power devices, but their basic structure is horizontal, so various measures are required to bring out their features. It becomes. As one of the ideas for realizing an element having such a high frequency characteristic, a high output characteristic, and a large power characteristic, it is conceivable to apply a technique using a via hole structure.

  FIG. 8 is a cross-sectional view of a GaAs FET using a via hole structure. As shown in FIG. 8, a semiconductor including a channel layer (active layer) made of N-type GaAs on an insulating substrate 101 made of gallium arsenide (GaAs) thinned to a thickness of about 25 μm. Layer 102 is formed. On the semiconductor layer 102, a gate electrode 103 that is in Schottky contact with the semiconductor layer 102, and a source electrode 104 and a drain electrode 105 that are in ohmic contact with the semiconductor layer 102 are formed. A via hole 106 penetrating the insulating substrate 101 and the semiconductor layer 102 is formed immediately below the source electrode 104, and a back electrode 107 is formed on the back surface of the insulating substrate 101 so as to fill the via hole 106. Has been. The back electrode 107 is connected to the ground power source 108. In this way, the FET in which the source electrode 104 is grounded via the back electrode 107 and the via hole 106 can reduce the source inductance as compared with an FET in which the source electrode 104 is grounded by a wire, so that the linear gain is about 2 dB. It has been reported that the improvement is seen (see Non-Patent Document 2).

As another conventional example, Patent Document 1 discloses a structure in which a source electrode or an emitter electrode is connected to a conductive P ⁺ type substrate grounded via a via hole. Further, a structure and a manufacturing method in which a substrate made of silicon carbide (SiC) or sapphire is thinly polished and a via hole is formed by etching from the back surface of the polished substrate is also disclosed in Patent Document 2. A structure covering the side surface of the via hole and the back surface of the substrate is disclosed in Patent Document 3.

Furthermore, as a semiconductor device having a via hole structure made of a group III-V nitride semiconductor, Patent Document 4 discloses a semiconductor device having a structure shown in FIG. In this semiconductor device, a buffer layer 209 made of high-resistance gallium aluminum nitride (AlGaN) and an element formation layer 210 made up of two layers of an N-type AlGaN layer and an undoped GaN layer are formed on a conductive substrate 201. A gate electrode 203, a source electrode 204, and a drain electrode 205 are formed on the element formation layer 210. Further, the source electrode 204 is also filled in the via hole 206 and is connected to the back electrode 207 through the conductive substrate 201.
Japanese translation of PCT publication No. 2002-536847 JP 11-45892 A JP 05-21474 A JP 2004-363563 A Yuji Ando, Yasuhiro Okamoto, Hironobu Miyamoto, Tatsumine Nakayama, Takashi Inoue, Masaaki Kuzuhara, “Evaluation of High Voltage AlGaN / GaN Heterojunction FET”, IEICE Technical Report, ED2002-214, CPM2002-105 (2002-10), pp. . 29-34 Masumi Fukuda and Yasuhiro Hirachi, “Basics of GaAs Field Effect Transistor”, IEICE, 1992, p. 214

  However, when a conventional via hole structure is formed using a material normally used in a III-V nitride semiconductor device or the like, there are the following problems. First, SiC and sapphire, which are normally used as the insulating substrate 101, are extremely hard and have high chemical resistance. Therefore, in order to maintain the strength of the insulating substrate 101, the insulating substrate 101 is not thinned on the back surface. It was extremely difficult to form the via hole 106 having a structure that penetrates to the end. Conversely, when the via hole 106 is formed after the insulating substrate 101 made of SiC or sapphire is thinly polished, the thin insulating substrate 101 becomes brittle. Therefore, in the step of forming the via hole 106, the insulating substrate The problem that 101 will crack will arise. For this reason, when an insulating substrate is used from SiC or sapphire, the via hole structure shown in FIG. 8 cannot be adopted.

  In the via hole structure shown in FIG. 9, it is essential to use a conductive substrate 201, and a non-conductive substrate, particularly a III-V nitride semiconductor device, is generally used, and an inexpensive sapphire substrate is used. There was a problem that could not be done.

  An object of this invention is to provide the semiconductor device provided with the via-hole structure which can be formed easily even if it uses a difficult semiconductor substrate like SiC or sapphire.

  In order to achieve the above object, the invention according to claim 1 is directed to a back surface formed on the back surface of the semiconductor substrate through at least a through-hole penetrating the semiconductor layer. In a semiconductor device connected to an electrode, a conductive first semiconductor layer and a high-resistance second semiconductor layer stacked on a conductive or non-conductive semiconductor substrate, and at least the semiconductor substrate and the second semiconductor A first recess that penetrates the layer and reaches the first semiconductor layer from the surface of the semiconductor substrate; a second recess that reaches the first semiconductor layer from the back surface of the semiconductor substrate; and the surface electrode. The first wiring formed in the first recess connected to the first semiconductor layer and the second recess connected to the back electrode and connected to the first semiconductor layer Second And a wiring, the first wiring through the first semiconductor layer and the second wiring, characterized by connecting the back electrode and the surface electrode.

  According to a second aspect of the present invention, there is provided the semiconductor device according to the first aspect, wherein the group III element consisting of at least one of the group consisting of gallium, aluminum, boron and indium, nitrogen, phosphorus and arsenic is formed on the semiconductor substrate. A conductive first semiconductor layer comprising a group III-V nitride semiconductor layer composed of a group V element containing at least nitrogen in the group consisting of: a high resistance layer laminated on the first semiconductor layer; The second semiconductor layer made of aluminum nitride, the third semiconductor layer made of the group III-V semiconductor layer stacked on the second semiconductor layer, and the surface in ohmic contact with the third semiconductor layer An electrode, the first recess that reaches the first semiconductor layer from the surface of the semiconductor substrate through the third semiconductor layer and the second semiconductor layer, and the semiconductor substrate through the semiconductor substrate. back A second recess reaching from the first semiconductor layer to the first semiconductor layer; the first wiring connected to the surface electrode and in ohmic contact with the first semiconductor layer; and a back electrode formed on the back surface of the semiconductor substrate The second wiring is in ohmic contact with the first semiconductor layer.

  According to a third aspect of the present invention, in the semiconductor device according to the second aspect, the energy gap between the second semiconductor layer and the third semiconductor layer is smaller than the energy gap of the third semiconductor layer. A fourth semiconductor layer comprising the III-V nitride semiconductor layer is provided.

  According to a fourth aspect of the present invention, in the semiconductor device according to the second or third aspect, the control device includes a control electrode that is in Schottky contact with the third semiconductor layer, and a source electrode and a drain electrode that are in ohmic contact. 3, or a current flowing through a channel formed between the third semiconductor layer and the channel formed between the third semiconductor layer and the fourth semiconductor layer is controlled by a voltage applied to the control electrode.

  According to the semiconductor device of the present invention, the first recess formed from the front surface of the semiconductor device may be formed relatively shallow, and the second recess formed from the back surface of the semiconductor device is not necessarily finely processed or accurately aligned. Therefore, a semiconductor device can be easily formed, which is preferable. This is particularly effective when using a SiC substrate or a sapphire substrate that is difficult to process. Further, since the first concave portion only needs to be formed shallow, it has a relatively small area, and a semiconductor device with high area utilization efficiency can be realized by increasing the degree of freedom of arrangement of the surface electrode.

  Further, since the second recess has a structure penetrating at least the semiconductor substrate, there is an advantage that either the non-conductive substrate or the conductive substrate can be selected. Further, by forming the wiring in the second recess, it functions as a thermal via and the heat dissipation effect is enhanced.

  In the group III-V nitride semiconductor device according to the present invention, the structure including the high resistance layer made of aluminum nitride can prevent the leakage current of the semiconductor substrate, and the front electrode and the back electrode can be at the same potential. Therefore, the effect of reducing inductance and improving high frequency characteristics and high output characteristics is great.

  In an HFET using 2DEG formed at the interface between a gallium aluminum nitride layer and a gallium nitride layer epitaxially grown on a semi-insulating substrate, in addition to supplying electrons from the carrier supply layer (gallium aluminum nitride layer), III A semiconductor device having excellent characteristics can be formed by large spontaneous polarization and piezo polarization due to the crystal structure of the group V nitride semiconductor, and the front electrode and the back electrode can be made to have the same potential, thereby reducing inductance, The effect of improving high frequency characteristics and high output characteristics is great.

  Furthermore, the semiconductor device of the present invention can use a sapphire substrate which is an inexpensive semi-insulating substrate, which is preferable. Since the sapphire substrate is transparent to visible light, the sapphire substrate can be applied to a semiconductor device in which optical elements and the like are integrated, and there is an advantage that the application range is widened.

  In the semiconductor device of the present invention, at least a conductive first semiconductor layer and a high-resistance second semiconductor layer are stacked on a conductive or nonconductive semiconductor substrate. This semiconductor substrate has a structure penetrating by a second recess formed from the back surface side, and the high-resistance second semiconductor layer is formed by either the first recess or the second recess formed from either the front surface side or the back surface side. It has a structure that penetrates through the recess. The bottoms of the first recess and the second recess both have a structure that reaches the conductive first semiconductor layer.

  With such a structure, the front electrode and the back electrode of the semiconductor device are the first wiring formed in the first recess, the first semiconductor layer, and the second wiring formed in the second recess. As compared with the conventionally proposed via hole structure, the structure can be easily formed.

  Hereinafter, embodiments of the present invention will be described in detail according to a manufacturing process by taking a metal semiconductor field effect transistor (MESFET) and an HFET as examples.

  First, the MESFET according to the first embodiment of the present invention will be described as an example according to the manufacturing process. On a semiconductor substrate 1 made of silicon, a conductive gallium nitride layer 3 (corresponding to a first semiconductor layer) is formed in a stacked manner with a buffer layer 2 interposed therebetween. The semiconductor substrate 1 may be made of sapphire or silicon carbide (SiC) in addition to conductive or nonconductive silicon. The buffer layer 2 can be a gallium nitride layer, an aluminum nitride layer, a ternary compound of gallium / aluminum / nitrogen, or a multilayer laminated film thereof. The gallium nitride layer 3 can be made highly conductive by doping silicon with monosilane during epitaxial growth. Next, a high-resistance aluminum nitride layer 4 (corresponding to the second semiconductor layer) and a high-conductivity gallium nitride active layer 5 (corresponding to the third semiconductor layer) are sequentially stacked on the gallium nitride layer 3. (FIG. 1).

  Next, a silicon nitride film serving as an etching mask is patterned on the semiconductor substrate 1, and the exposed semiconductor substrate 1 is etched with a mixed solution of hydrofluoric acid, nitric acid, and acetic acid to select the semiconductor substrate 1 made of silicon. Etch. Next, a part of the exposed buffer layer 2 and gallium nitride layer 3 is removed by, for example, a reactive ion etching method using chlorine gas to expose a part of the gallium nitride layer 3, and the gallium nitride layer is exposed from the back side. A recess 6 reaching 3 (corresponding to a second recess) is formed. Thereafter, the silicon nitride film used as an etching mask is removed (FIG. 2). Note that etching methods of the semiconductor substrate, the first semiconductor layer, and the second semiconductor layer that are formed using materials other than those described above may be selected as appropriate depending on the material that forms each.

  Next, a silicon nitride film (not shown) serving as an etching mask is patterned on the surface of the gallium nitride active layer 5, and the exposed gallium nitride active layer 5, aluminum nitride layer 4 and part of the gallium nitride layer 3 are, for example, The reactive ion etching method using chlorine gas is sequentially removed by etching to expose a part of the gallium nitride layer 3 and form another recess 7 (corresponding to the first recess) reaching the gallium nitride layer 3 from the surface side. (FIG. 3).

  Thereafter, according to a normal manufacturing method, a source electrode 8 (corresponding to a surface electrode) and a drain electrode 9 made of, for example, a laminated film of titanium / aluminum / gold are brought into contact with a part of the gallium nitride active layer 5, and the source electrode The surface wiring electrode 10 is pattern-formed so as to be connected to 8. Similarly, the back surface electrode 11 and the back surface wiring electrode 12 are integrally formed on the back surface of the semiconductor substrate 1 so as to be connected to the back surface electrode 11. Thereafter, lamp annealing is performed at 850 ° C. for 30 seconds in a nitrogen atmosphere to form the ohmic contact source electrode 8, drain electrode 9, surface wiring electrode 10, back surface electrode 11, and back surface wiring electrode 12 (FIG. 4). ). The surface wiring electrode 10 and the back surface wiring electrode 12 do not need to be formed integrally with the source electrode 8 and the back surface electrode 11 to cover the inside of the recess as shown in FIG. In addition, it is preferable to form an ohmic contact on the surface of the gallium nitride layer 3 exposed in the other recess 7. This is for reducing the resistance between the source electrode 8 (front surface electrode) and the back electrode 11.

  Next, a gate electrode 13 made of, for example, a nickel / gold laminated film is formed between the source electrode 8 and the drain electrode 9 in Schottky contact with the gallium nitride active layer 5 in accordance with a normal manufacturing method.

  Thereafter, in order to reduce the wiring resistance, a wiring 14 (corresponding to the first wiring) made of a thick gold film is formed in the recess 7 by, for example, plating. Similarly, a wiring 15 (corresponding to the second wiring) made of a thick gold film is formed in another recess 6 (FIG. 5). When the source electrode 8 and the front surface wiring electrode 10 or the back surface electrode 11 and the back surface wiring electrode 12 are not integrally formed, or when there is a discontinuous portion in the concave portion 6 and the other concave portion 7, The source electrode 8 and the front surface wiring electrode 10 or the back surface electrode 11 and the back surface wiring electrode 12 may be connected by this wiring 14 and another wiring 15. Thereafter, the FET can be completed in accordance with a normal manufacturing process of a semiconductor device.

  Since the semiconductor device of the present invention formed as described above has a structure including the recess 6 penetrating the semiconductor substrate 1 and the buffer layer 2, a non-conductive substrate such as a semi-insulating substrate or a high-resistance substrate is used. Can be used. Further, since the recess 6 (second recess) reaching the gallium nitride layer 3 from the back surface of the semiconductor device does not require fine processing or accurate alignment, it can be formed at a low cost when a sapphire substrate is used. There is an advantage. In the case of using the SiC substrate, the improvement of the characteristics of the semiconductor device is expected by improving the heat dissipation effect.

  In addition, another recess 7 (first recess) that reaches the gallium nitride layer 3 (first semiconductor layer) from the surface of the semiconductor device may be formed shallow, so that it can be easily formed by a normal method for manufacturing a semiconductor device. It is possible to increase the degree of freedom of arrangement and is preferable. Further, by providing the high-resistance aluminum nitride layer 4, a reduction in leakage current is also expected.

  Next, the HFET according to the second embodiment of the present invention will be described as an example according to the manufacturing process. First, a conductive gallium nitride layer 3 (corresponding to a first semiconductor layer) is stacked on a semiconductor substrate 1 made of sapphire via a buffer layer 2. As the semiconductor substrate, conductive or nonconductive silicon or silicon carbide (SiC) can be used in addition to sapphire. The buffer layer 2 can be a gallium nitride layer, an aluminum nitride layer, a ternary compound of gallium / aluminum / nitrogen, or a multilayer laminated film thereof. The gallium nitride layer 3 can be made highly conductive by doping silicon with monosilane during epitaxial growth. Next, a high-resistance aluminum nitride layer 4 (corresponding to the second semiconductor layer), a non-doped gallium nitride layer 16 (corresponding to the fourth semiconductor layer) serving as a channel layer, and a carrier supply layer are formed on the gallium nitride layer 3. A gallium aluminum nitride layer 17 (corresponding to a third semiconductor layer) is formed by lamination (FIG. 7). In some cases, another schottky layer or cap layer may be provided on the gallium aluminum nitride layer 17.

  Next, a silicon oxide film or polyimide film serving as an etching mask is patterned on the semiconductor substrate 1, and the exposed semiconductor substrate 1 is etched with a high-temperature (for example, 280 degrees) mixed solution composed of phosphoric acid and sulfuric acid, and is composed of sapphire. The semiconductor substrate 1 is selectively etched. Next, a part of the exposed buffer layer 2 and gallium nitride layer 3 are sequentially removed by, for example, a reactive ion etching method using chlorine gas to expose a part of the gallium nitride layer 3 and gallium nitride from the back side. A recess 6 (corresponding to a second recess) reaching the layer 3 is formed. Thereafter, the silicon oxide film used as an etching mask is removed (corresponding to FIG. 2).

  Next, a silicon nitride film serving as an etching mask is patterned on the surface of the gallium aluminum nitride layer 18, and the exposed gallium aluminum nitride layer 17, the non-doped gallium nitride layer 16, the aluminum nitride layer 4 and a part of the gallium nitride layer 3 are formed. For example, the reactive ion etching method using chlorine gas is sequentially removed by etching to expose a part of the gallium nitride layer 3 and to form another recess 7 (corresponding to the first recess) reaching the gallium nitride layer 3 from the surface side. Formed (corresponding to FIG. 3).

  Thereafter, according to a normal manufacturing method, a source electrode 8 (corresponding to a surface electrode) and a drain electrode 9 made of, for example, a laminated film of titanium / aluminum / gold are brought into contact with a part of the gallium nitride layer 3, and the source electrode 8 The surface wiring electrode 10 is patterned so as to be connected to the wiring. Similarly, a back surface wiring electrode 12 is integrally formed on the semiconductor substrate 1 so as to be connected to the back surface electrode 11. Thereafter, lamp annealing is performed at 850 ° C. for 30 seconds in a nitrogen atmosphere to form the ohmic contact source electrode 8, drain electrode 9, surface wiring electrode 10, back surface electrode 11, and back surface wiring electrode 12 (FIG. 4). Equivalent). The surface wiring electrode 10 and the back surface wiring electrode 12 do not need to be formed integrally with the source electrode 8 and the back surface electrode 11 to cover the inside of the recess as shown in FIG. In addition, it is preferable to form an ohmic contact on the surface of the gallium nitride layer 3 exposed in the other recess 7. This is for reducing the resistance between the source electrode 8 (front surface electrode) and the back electrode 11.

  Next, a gate electrode 13 made of, for example, a nickel / gold laminated film is formed between the source electrode 8 and the drain electrode 9 in Schottky contact with the gallium nitride layer 3 according to a normal manufacturing method.

  Finally, in order to reduce the wiring resistance, a wiring 14 (corresponding to the first wiring) made of a thick gold film is formed in the recess 7 by, for example, plating. Similarly, a wiring 15 (corresponding to the second wiring) made of a thick gold film is formed in another recess 6 (FIG. 7). When the source electrode 8 and the front surface wiring electrode 10 or the back surface electrode 11 and the back surface wiring electrode 12 are not integrally formed, or when there is a discontinuous portion in the concave portion 6 and the other concave portion 7, The source electrode 8 and the front surface wiring electrode 10 or the back surface electrode 11 and the back surface wiring electrode 12 may be connected by this wiring 14 and another wiring 15. Thereafter, the HFET can be completed in accordance with a normal semiconductor device manufacturing process.

  Since the semiconductor device of the present invention formed as described above has a structure including the recess 6 penetrating the semiconductor substrate 1 and the buffer layer 2, a semi-insulating substrate or a high resistance substrate can be used. Further, the concave portion 6 (second concave portion) reaching the gallium nitride layer 3 from the back surface of the semiconductor device does not require fine processing or accurate alignment. As a result, an inexpensive sapphire substrate can be used, or an SiC substrate with excellent heat dissipation can be used, and an improvement in characteristics of the semiconductor device is expected.

  In addition, another recess 7 (first recess) that reaches the gallium nitride layer 3 (first semiconductor layer) from the surface of the semiconductor device may be formed shallow, so that it can be easily formed by a normal method for manufacturing a semiconductor device. It is possible to increase the degree of freedom of arrangement and is preferable. Further, by providing the high-resistance aluminum nitride layer 4, a reduction in leakage current is also expected.

  Although the embodiments of the present invention have been described above, the present invention is not limited to these embodiments and can be variously modified. For example, the semiconductor layer can be formed of a compound semiconductor such as silicon or GaAs, a nitride semiconductor made of GaN, InN, AlN, or a mixed crystal compound thereof. The composition of the electrode is appropriately selected according to the type of semiconductor layer used.

  Further, the via hole structure of the present invention can be adopted not only for FETs but also for semiconductor devices having front and back electrodes. Furthermore, the first semiconductor layer of the present invention does not need to be formed on the entire surface of the semiconductor substrate, and a selective region can be formed such that at least the front surface electrode and the back surface electrode are conductively connected through the first semiconductor layer. What is necessary is just a laminated structure. The method of selectively forming the first semiconductor layer is a normal semiconductor, such as a selective epitaxial growth method, a method of etching and removing unnecessary portions after epitaxial growth on the entire surface, a method of partially doping impurities using a mask, etc. This can be done by the method for manufacturing the device. When a high-power, high-frequency semiconductor element and an element such as a coil are mounted together, it may be preferable to remove the first semiconductor layer in the formation region of the coil or the like.

It is a figure explaining the manufacturing process of the 1st Example of this invention. It is a figure explaining the manufacturing process of the 1st Example of this invention. It is a figure explaining the manufacturing process of the 1st Example of this invention. It is a figure explaining the manufacturing process of the 1st Example of this invention. It is a figure explaining the manufacturing process of the 1st Example of this invention. It is a figure explaining the manufacturing process of the 2nd Example of this invention. It is a figure explaining the manufacturing process of the 2nd Example of this invention. It is explanatory drawing of this kind of conventional semiconductor device. It is explanatory drawing of another conventional semiconductor device of this kind.

Explanation of symbols

1: semiconductor substrate, 2: buffer layer, 3: gallium nitride layer,
4: aluminum nitride layer, 5: gallium nitride active layer, 6: recess, 7: another recess,
8: Source electrode, 9: Drain electrode, 10: Front wiring electrode, 11: Back electrode,
12: electrode for back surface wiring, 13: gate electrode, 14: first wiring, 15: second wiring,
16: Non-doped gallium nitride layer, 17: Gallium aluminum nitride layer

Claims (4)

In a semiconductor device in which a surface electrode formed on the surface of a semiconductor substrate on which a semiconductor layer is laminated is connected to a back electrode formed on the back surface of the semiconductor substrate through at least a through-hole penetrating the semiconductor layer.
A conductive first semiconductor layer and a high-resistance second semiconductor layer stacked on a conductive or non-conductive semiconductor substrate;
A first recess that penetrates at least the semiconductor substrate and the second semiconductor layer and reaches the first semiconductor layer from the surface of the semiconductor substrate; and a second recess that reaches the first semiconductor layer from the back surface of the semiconductor substrate. A recess of
A first wiring formed in the first recess connected to the surface electrode and connected to the first semiconductor layer;
A second wiring formed in the second recess connected to the back electrode and connected to the first semiconductor layer;
A semiconductor device, wherein the front electrode and the back electrode are connected through the first wiring, the first semiconductor layer, and the second wiring. The semiconductor device according to claim 1,
A group III element composed of at least one of the group consisting of gallium, aluminum, boron and indium and a group III element containing at least nitrogen among the group consisting of nitrogen, phosphorus and arsenic on the semiconductor substrate. A conductive first semiconductor layer comprising a group V nitride semiconductor layer;
The second semiconductor layer made of high-resistance aluminum nitride laminated on the first semiconductor layer;
A third semiconductor layer comprising the III-V group semiconductor layer stacked on the second semiconductor layer;
The surface electrode in ohmic contact with the third semiconductor layer;
The first recess that reaches the first semiconductor layer from the surface of the semiconductor substrate through the third semiconductor layer and the second semiconductor layer, and the back surface of the semiconductor substrate through the semiconductor substrate A second recess reaching the first semiconductor layer;
The first wiring connected to the surface electrode and in ohmic contact with the first semiconductor layer;
A semiconductor device comprising: the second wiring connected to a back electrode formed on the back surface of the semiconductor substrate and in ohmic contact with the first semiconductor layer. The semiconductor device according to claim 2,
A fourth semiconductor layer comprising the group III-V nitride semiconductor layer having an energy gap smaller than that of the third semiconductor layer between the second semiconductor layer and the third semiconductor layer; A semiconductor device comprising: The semiconductor device according to claim 2 or 3,
A control electrode in Schottky contact with the third semiconductor layer, a source electrode and a drain electrode in ohmic contact, and a channel made of the third semiconductor layer, or the third semiconductor layer and the fourth semiconductor A semiconductor device, wherein a current flowing through a channel formed between layers is controlled by a voltage applied to the control electrode.

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