JP4843651B2 - Semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device , and more particularly to a highly reliable high power semiconductor device made of gallium nitride (GaN) or the like.

  It is known that a field effect transistor (FET) using a gallium nitride (GaN) -based semiconductor has a large current collapse and leakage current. The cause is dislocations and crystal defects in the epitaxial crystal.

  Since crystal defects deteriorate basic performance such as increase of leakage current and occurrence of current collapse phenomenon, it is very important to obtain an epitaxial layer with few crystal defects.

  In order to reduce the dislocations and defects of this crystal, it is known to insert an aluminum gallium nitride (AlGaN) layer or an aluminum nitride (AlN) layer in the GaN layer.

  In addition, GaN and AlGaN or AlN have a large lattice constant difference, and electric charges are generated by piezo polarization between the GaN layer and the AlGaN layer. The electric charge generated in the GaN layer drastically reduces the high frequency characteristics of the semiconductor device. There is a problem of end.

  For example, there is a large difference in lattice constant between the GaN layer and the AlGaN layer, and charges due to piezoelectric polarization are generated between the GaN layer and the AlGaN layer, and the charges generated in the GaN layer drastically degrade the high-frequency characteristics of the semiconductor device. There is a problem.

  Such charges due to piezo polarization increase the conductivity of the GaN layer, increase the leakage current between the gate electrode and the source electrode or between the gate electrode and the drain electrode, and reduce the power amplification gain of the semiconductor device. .

  A field effect transistor using a GaN-based semiconductor that can be formed to a gate size of 0.1 μm and does not generate a leakage current between the gate electrode and the source or drain electrode and a method for manufacturing the same have already been disclosed. (For example, refer to Patent Document 1). In Patent Document 1, a gate leakage current is reduced by using a field effect transistor having a gate electrode having a T-shaped cross section.

In addition, a group III nitride semiconductor crystal, a group III nitride semiconductor substrate, a semiconductor device, and a method for manufacturing a group III nitride semiconductor crystal having a high resistance value have already been disclosed (for example, see Patent Document 2). In Patent Document 2, for example, a group III nitride semiconductor crystal to which Fe is added as a transition metal, and a Ga-doped GaN layer having a Ga atom vacancy density of 1 × 10 ¹⁶ cm ⁻³ or less is disclosed. . The Fe atom density of the Fe-doped GaN layer is 5 × 10 ¹⁷ cm ⁻³ to 10 ²⁰ cm ⁻³ . A semiconductor device having a semiconductor layer formed on a group III nitride semiconductor substrate made of the Fe-doped GaN layer is also disclosed.

  In addition, a semiconductor element that can form a plurality of nitride compound semiconductor layers having a lattice constant difference of a predetermined value or more in a multi-layered state with good crystallinity and can suppress propagation of threading dislocations in the epitaxial growth direction. It has already been disclosed (for example, see Patent Document 3).

  As shown in FIG. 11, the basic unit of a conventional high power semiconductor device composed of a gallium nitride layer and an aluminum gallium nitride (AlGaN) layer has a GaN layer disposed on a substrate 10 made of, for example, SiC. And an AlGaN layer 14 disposed on the GaN layer, and a gate electrode 24, a source electrode 20 and a drain electrode 22 disposed on the AlGaN layer 14.

  Furthermore, as shown in FIG. 11, in the conventional semiconductor device, an element isolation region that becomes the inactive region NA is formed in the periphery of the active region AA formed of the AlGaN layer 14 by mesa etching technology, ion implantation technology, or the like. ing.

  As shown in FIG. 11, the gate electrode 24, the source electrode 20, and the drain electrode 22 are respectively a gate terminal electrode 240, a source terminal electrode 200, and a drain terminal electrode 220 disposed on the element isolation region that becomes the inactive region NA. It is connected to the.

  In the conventional semiconductor device, as shown in FIG. 11, the gate and drain other than the active region AA are electrically insulated by an element isolation region that becomes the inactive region NA. Therefore, the surface leakage current does not flow between the gate and the drain on the element isolation region other than the active region AA.

However, when a large voltage is applied between the gate and the drain, the electric field concentrates on the gate electrode front end GP between the gate electrode 24 and the drain terminal electrode 220. For this reason, a surface leakage current flows between the gate electrode 24 and the drain terminal electrode 220, leading to deterioration of the characteristics of the semiconductor device. In some cases, there is a problem that the semiconductor device is destroyed.
JP 2002-141499 A (page 3-4, FIG. 1) JP 2007-184379 (page 6-7, FIGS. 4 and 5) JP 2007-22001 A (FIGS. 1, 7, and 10)

An object of the present invention is to provide a semiconductor device for high power that has high reliability and can be improved in performance.

According to an aspect for achieving the above object, a substrate, a nitride compound semiconductor layer disposed on the substrate, an aluminum gallium nitride layer (Al _X) disposed on the nitride compound semiconductor layer, and An active region composed of Ga _1-X N) (0.1 ≦ x ≦ 1), an element isolation region formed by ion implantation and isolating the active region from each other, and the active surrounded by the element isolation region A gate electrode, a source electrode, and a drain electrode disposed on the region; and a gate terminal electrode, a source terminal electrode, and a drain that are disposed on the element isolation region and connected to the gate electrode, the source electrode, and the drain electrode, respectively. There is provided a semiconductor device including a terminal electrode, wherein a tip end portion of the gate electrode and the drain terminal electrode are opposed to each other with a groove portion interposed therebetween .

According to the present invention, by forming a groove by etching a part between the gate electrode and the drain terminal electrode, the leakage current between the gate and the drain can be reduced, and the reliability is high and the performance is large. A power semiconductor device can be provided.

According to the present invention, a part between the gate electrode and the drain terminal electrode is etched to form a groove, thereby effectively increasing the distance between the gate electrode and the drain terminal electrode, thereby increasing the surface between the gate and the drain. A leakage current can be reduced, and a highly reliable and high performance semiconductor device for high power can be provided.

  Next, embodiments of the present invention will be described with reference to the drawings. In the following, the same reference numerals are assigned to the same blocks or elements to avoid duplication of explanation and simplify the explanation. It should be noted that the drawings are schematic and different from the actual ones. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

  The following embodiments exemplify apparatuses and methods for embodying the technical idea of the present invention. In the embodiments of the present invention, the arrangement of each component is as follows. Not specific. Various modifications can be made to the embodiment of the present invention within the scope of the claims.

[First embodiment]
(Element structure)
A schematic planar pattern configuration of the semiconductor device according to the first embodiment of the present invention is expressed as shown in FIG. Moreover, the schematic cross-sectional structure along the II-II line of FIG. 1 is represented as shown in FIG. 2 or FIG. The example of FIG. 2 has a cross-sectional structure in which an element isolation region 34 to be an inactive region NA is formed using an ion implantation technique, and the example of FIG. It is the cross-sectional structure formed using.

As shown in FIGS. 1 to 3, the semiconductor device according to the first embodiment includes a substrate 10, a nitride-based compound semiconductor layer 12 disposed on the substrate 10, and a nitride-based compound semiconductor layer 12. Active region AA made of aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 14 and element isolation region (34, 25) for isolating active region AA from each other And the gate electrode 24, the source electrode 20 and the drain electrode 22 disposed on the active region AA surrounded by the element isolation regions (34, 25) and the element isolation regions (34, 25). The gate terminal electrode 240 connected to the electrode 24, the source electrode 20 and the drain electrode 22, the source terminal electrode 200 and the drain terminal electrode 220, and the gate electrode 24 and the drain terminal electrode 220. And a the groove 28 formed between.

The element isolation regions (34, 25) are formed up to a part of the aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 14 and the nitride-based compound semiconductor layer 12 in the depth direction. Has been.

The element isolation region 34 is formed by ion implantation. As the ion species, for example, nitrogen (N), argon (Ar), or the like can be applied. Further, the dose accompanying ion implantation is, for example, about 1 × 10 ¹⁴ (ions / cm ² ), and the acceleration energy is, for example, about 100 keV to 200 keV.

A passivation insulating layer 30 is formed on the element isolation region 34 and the device surface. The insulating layer 30 is formed of, for example, a nitride film deposited by PECVD (Plasma Enhanced Chemical Vapor Deposition), an alumina (Al ₂ O ₃ ) film, an oxide film (SiO ₂ ), an oxynitride film (SiON), or the like. can do.

  A passivation insulating layer 30 may also be disposed in the groove 28.

A source contact 20a is formed at the interface between the source electrode 20 and the aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 14, and the drain electrode 22 and the aluminum gallium nitride layer (Al _A drain contact 22 a is formed at the interface with _x Ga _1-x N) (0.1 ≦ x ≦ 1) 14. The source electrode 20 and the drain electrode 22 are made of, for example, aluminum (Al), Ti / Au, or the like.

  The gate electrode 24 can be formed of, for example, Ni / Au.

  The source contact 20a and the drain contact 22a can be formed by a laminated structure made of, for example, Al / Ti or Ni / Al / Ti.

At the interface between the nitride-based compound semiconductor layer 12 and the aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 14 disposed on the nitride-based compound semiconductor layer 12, A two-dimensional electron gas layer is formed.

  The substrate 10 includes a SiC substrate, a GaAs substrate, a GaN substrate, a substrate in which a GaN epitaxial layer is formed on the SiC substrate, a substrate in which a GaN epitaxial layer is formed on the Si substrate, and a heterojunction made of GaN / GaAlN on the SiC substrate. Any of a substrate on which an epitaxial layer is formed, a substrate on which a GaN epitaxial layer is formed on a sapphire substrate, a sapphire substrate, or a diamond substrate may be provided.

  The nitride compound semiconductor layer 12 is formed of, for example, a GaN layer.

(Structural example of groove)
―Structure Example 1―
For example, as shown in FIG. 4, the groove 28 is formed including a part of the active region AA at the tip of the gate electrode 24. Further, as shown in FIG. 4, the trench 28 is formed so as to include a part of the element isolation region 34 between the gate electrode 24 and the drain terminal electrode 220. Further, as shown in FIG. 4, the end portion of the gate electrode 24 is extended and disposed in the groove portion 28.

-Structural example 2-
For example, as shown in FIG. 5, the side wall of the groove portion 28 has a step structure in the side wall portion of the element isolation region 34. The number of steps is not limited to two but may be two or more. Further, a step structure may be provided in the side wall portion on the semiconductor side.

―Structure Example 3―
Moreover, the groove part may be formed in multiple numbers, for example, as shown in FIG. In the example of FIG. 6, three groove portions 28a, 28b, and 28c are formed. The groove portions 28a, 28b, and 28c are formed so as to include a part of the element isolation region 34 between the gate electrode 24 and the drain terminal electrode 220, as shown in FIG. The insulating layers 30 are filled in the grooves 28a and 28b. On the other hand, the groove 28c is formed so as to include a part of the active region AA at the tip of the gate electrode 24. In addition, the end portion of the gate electrode 24 is extended and disposed in the groove portion 28c.

-Structural example 4-
In addition, as shown in FIG. 7, the groove 28 may have a structure in which the tip of the gate electrode 24 and the drain terminal electrode 220 are separated from each other. An insulating layer 30 is formed in the groove 28.

  Further, the two groove portions 28 shown in FIG. 1 may be coupled to each other to have a stripe structure in the arrangement direction of the source electrode 20, the gate electrode 24, and the drain electrode 22.

  Further, another groove portion having a structure substantially the same as that of the groove portion 28 may be formed between the gate electrode 24 and the gate terminal electrode 240. This is because the electric field is likely to be concentrated at the end portion as well as the leading end portion of the stripe of the gate electrode 24, but by forming another groove portion, it is possible to suppress the occurrence of leakage current between the gate and the drain. .

(Production method)
The method for manufacturing a semiconductor device according to the first embodiment includes a step of forming a nitride compound semiconductor layer 12 on a substrate 10 and an aluminum gallium nitride layer (Al _x Ga) on the nitride compound semiconductor layer 12. _1-x N) (0.1 ≦ x ≦ 1) 14 forming an active region AA, forming a device isolation region (34, 25) for isolating the active region AA from each other, device isolation Forming the gate electrode 24, the source electrode 20 and the drain electrode 22 on the active region AA surrounded by the regions (34, 25), and gate terminals connected to the gate electrode 24, the source electrode 20 and the drain electrode 22, respectively; Forming the electrode 240, the source terminal electrode 200, and the drain terminal electrode 220 on the element isolation region (34, 25), the gate electrode 24, and the drain terminal electrode; And a step of forming a groove 28 between the 20.

  The step of forming the groove portion 28 is preferably performed after the step of forming the element isolation regions (34, 25).

  Further, an ion implantation technique can be used for the step of forming the element isolation region 34.

  Further, mesa etching can be used for the step of forming the element isolation region 25.

In the step of forming the element isolation region 34, the element isolation region 34 has a depth of the aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 14 and the nitride-based compound semiconductor layer 12. Form up to part of the direction.

  The semiconductor device manufacturing method according to the first embodiment of the present invention will be described in detail below.

(A) TMG (trimethylgallium) and ammonia gas are flowed on the substrate 10 made of SiC, and the GaN layer 12 is formed to a thickness of, for example, about 1 μm to 2 μm by epitaxial growth.

(B) Next, an aluminum gallium nitride layer (Al _0.3 Ga _1-0.3 N) (0.1 ≦ x ≦ 1) 14 having an Al composition ratio of about 30% is formed by flowing TMAl (trimethylaluminum) and ammonia gas and epitaxially growing. Is formed to a thickness of about 20 nm to 100 nm, for example.

(C) Next, an element isolation region 34 for isolating the active areas AA from each other is formed by an ion implantation technique. As the ion species, for example, nitrogen (N), argon (Ar), or the like can be applied. Further, the dose accompanying ion implantation is, for example, about 1 × 10 ¹¹ (ions / cm ² ), and the acceleration energy is, for example, about 100 keV to 200 keV. The element isolation region 25 that isolates the active areas AA from each other may be formed by mesa etching technology. In the following description, an example of the element isolation region 34 formed by the ion implantation technique will be described.

(D) Next, the trench 28 is formed between the gate electrode 24 and the drain terminal electrode 220 by a dry etching technique. As the dry etching technique, a reactive ion etching (RIE) technique or the like can be applied. As the reaction gas, for example, a chlorine-based etching gas such as BCl ₃ can be used. Here, the depth of the groove 28 is deeper than the thickness of the aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 14 and is, for example, about 100 nm to 200 nm. Therefore, the bottom surface of the groove 28 is the nitride-based compound semiconductor layer (GaN layer) 12. In addition, the structure shown in FIGS. 4-7 is applicable to the structure of the groove part 28, for example.

(E) Next, the source contact 20 a and the drain contact 22 a are formed on the active region AA surrounded by the element isolation region 34. As the contact formation technique, a vacuum deposition technique, a sputtering technique, or the like can be applied. The source contact 20a and the drain contact 22a are formed as ohmic electrodes by a laminated structure made of Al / Ti or Ni / Al / Ti, for example.

(F) Next, the gate electrode 24 is formed. As an electrode forming technique, a vacuum deposition technique, a sputtering technique, or the like can be applied. The gate electrode 24 can be formed of, for example, Ni / Au. The gate electrode 24 forms a Schottky contact with the aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 14. The width of the gate electrode 24 is, for example, about 0.1 μm to 1 μm. In addition, the front-end | tip part of the gate electrode 24 may be extended | stretched and formed in the groove part 28, as shown in FIGS. Alternatively, as shown in FIG. 7, the groove portions 28 may be formed apart from each other.

(G) Next, the gate terminal electrode 240, the source terminal electrode 200, and the drain terminal electrode 220 connected to the gate electrode 24, the source contact 20a, and the drain contact 22a, respectively, are formed on the element isolation region 34.

(H) Next, a passivation insulating layer 30 is formed on the entire device surface. This insulating layer 30 can be formed of, for example, a nitride film, an Al ₂ O ₃ film, a SiO ₂ film, a SiON film, or the like deposited by PECVD.

(I) Next, the source electrode 20 and the drain electrode 22 are formed. As an electrode forming technique, a vacuum deposition technique, a sputtering technique, or the like can be applied. The source electrode 20 and the drain electrode 22 are made of, for example, aluminum (Al), Ti / Au, or the like.

  The semiconductor device according to the first embodiment is completed through the steps (a) to (i).

  According to the first embodiment, the trench 28 is formed by etching a part between the gate electrode 24 and the drain terminal electrode 220, whereby the gate-drain leakage current can be reduced, and the reliability is improved. And a high-performance semiconductor device and a method for manufacturing the same can be provided.

  According to the first embodiment, a portion between the gate electrode 24 and the drain terminal electrode 220 is etched to form the groove 28, so that the effective gap between the gate electrode 24 and the drain terminal electrode 220 can be obtained. By increasing the distance, the surface leakage current between the gate and the drain can be reduced, and a highly reliable and high performance semiconductor device and a manufacturing method thereof can be provided.

[Second Embodiment]
(Overall element structure)
A schematic planar pattern configuration of the semiconductor device according to the second embodiment is expressed as shown in FIG. An enlarged view of portion A in FIG. 8 is represented as shown in FIG.

  The semiconductor device according to the second embodiment shown in FIGS. 8 to 9 includes an electrode pattern arrangement for increasing power and a groove 28 formed between the gate electrode 24 and the drain terminal electrode 220. It has the characteristics.

As shown in FIGS. 8 to 9, the schematic planar pattern configuration of the semiconductor device according to the second embodiment includes a substrate 10, a nitride-based compound semiconductor layer 12 disposed on the substrate 10, and a nitride. An element isolation that is disposed on the system compound semiconductor layer 12 and includes the active region AA composed of an aluminum gallium nitride layer (Al _x Ga ₁ -xN) (0.1 ≦ x ≦ 1) 14 and the active region AA. The gate electrode 24, the source electrode 20, and the drain electrode 22 that are disposed on the active region AA surrounded by the region 34 and the element isolation region 34 and have a plurality of fingers, respectively, and the gate electrode 24, the source electrode 20, and the drain electrode 22. A gate terminal electrode 240, a source terminal electrode 200, a drain terminal electrode 220 formed by bundling a plurality of fingers for each, a gate electrode 24, And a groove portion 28 formed between the drain terminal electrode 220.

The element isolation region 34 is formed up to a part in the depth direction of the aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 14 and the nitride-based compound semiconductor layer 12.

  The element isolation region 34 is formed by, for example, an ion implantation technique.

  The groove 28 may be formed so as to include a part of the active region AA at the tip of the gate electrode 24 having a plurality of fingers.

  The groove 28 may be formed so as to include a part of the element isolation region 34 between the gate electrode 24 having a plurality of fingers and the drain terminal electrode 220.

  Similar to the structure shown in FIGS. 4 to 6, the tip of the gate electrode 24 having a plurality of fingers may be extended in the groove 28.

  Similar to the structure shown in FIG. 5, the side wall of the groove 28 may have a step structure.

  A plurality of groove portions 28 may be formed in the same manner as the structure shown in FIG.

  As shown in FIG. 7, the end portion of the gate electrode 24 having a plurality of fingers and the drain terminal electrode 220 are separated by the groove portion 28, and the passivation insulating layer 30 may be formed in the groove portion 28. .

  Furthermore, another groove portion having substantially the same structure as the groove portion 28 may be formed between the gate electrode 24 having a plurality of fingers and the gate terminal electrode 240. This is because the electric field is likely to be concentrated at the end portion as well as the leading end portion of the stripe of the gate electrode 24, but by forming another groove portion, it is possible to suppress the occurrence of leakage current between the gate and the drain. .

  The substrate 10 includes a SiC substrate, a GaAs substrate, a GaN substrate, a substrate in which a GaN epitaxial layer is formed on the SiC substrate, a substrate in which a GaN epitaxial layer is formed on the Si substrate, and a heterojunction made of GaN / GaAlN on the SiC substrate. Any of a substrate on which an epitaxial layer is formed, a substrate on which a GaN epitaxial layer is formed on a sapphire substrate, a sapphire substrate, or a diamond substrate may be provided.

  In the configuration example of FIG. 8, the dimensions of each part are, for example, a cell width W1 of about 120 μm, W2 of about 80 μm, a cell length W3 of about 100 μm, W4 of about 120 μm, and a gate width WG of 100 μm × 6 as a whole. × 4 cells = about 2.4 mm.

  In the example of FIG. 8, in the source terminal electrode 200, a VIA hole 260 is formed from the back surface of the substrate 10, and a ground conductor is formed on the back surface of the substrate 10. When the circuit element is grounded, the circuit element provided on the substrate 10 and the ground conductor formed on the back surface of the substrate 10 are electrically connected via the VIA hole 260 penetrating the substrate 10.

  The gate terminal electrode 240 is connected to the peripheral semiconductor chip with a bonding wire or the like, and the drain terminal electrode 220 is also connected to the peripheral semiconductor chip with a bonding wire or the like.

(Production method)
The method for manufacturing a semiconductor device according to the second embodiment includes a step of forming a nitride compound semiconductor layer 12 on a substrate 10 and an aluminum gallium nitride layer (Al _x Ga) on the nitride compound semiconductor layer 12. _1-x N) (0.1 ≦ x ≦ 1) 14 forming an active region AA, forming a device isolation region (34, 25) for isolating the active region AA from each other, device isolation Forming a gate electrode 24, a source electrode 20 and a drain electrode 22 each having a plurality of fingers on the first surface of the active region AA surrounded by the regions (34, 25); In addition, the gate terminal electrode 240, the source terminal electrode 200, and the drain terminal electrode 220 formed by bundling a plurality of fingers for each of the drain electrode 22 and the drain terminal electrode 22 are separated. And a step of forming on the band (34,25), and forming a groove 28 between the gate electrode 24 and the drain terminal electrode 220 having a plurality of fingers.

  The step of forming the groove portion 28 is preferably performed after the step of forming the element isolation regions (34, 25).

  Further, an ion implantation technique can be used for the step of forming the element isolation region 34.

  The step of forming the element isolation region 25 can use a mesa etching technique.

  The details of the method of manufacturing the semiconductor device according to the second embodiment are the same as those of the first embodiment, and thus the description thereof is omitted.

  Also in the semiconductor device according to the second embodiment, the detailed structure of the groove portion 28 is the same as that in the first embodiment, and thus the description thereof is omitted.

(Modification)
A schematic planar pattern configuration of a semiconductor device according to a modification of the second embodiment is expressed as shown in FIG.

  In the semiconductor device according to the modification of the second embodiment, as shown in FIG. 10, the groove 28 is formed between the gate electrode 24 having a plurality of fingers and the drain terminal electrode 220 with a plurality of finger electrodes. It is characterized in that it has a stripe structure parallel to the arrangement direction.

  Also in the semiconductor device according to the modified example of the second embodiment, the detailed structure of the groove 28 is the same as that of the first embodiment, and thus the description thereof is omitted.

  A method for manufacturing a semiconductor device according to a modification of the second embodiment is also the same as that of the second embodiment, and a description thereof will be omitted.

  Furthermore, another groove portion having substantially the same structure as the groove portion 28 may be formed between the gate electrode 24 having a plurality of fingers and the gate terminal electrode 240. This is because the electric field is likely to be concentrated at the end portion as well as the leading end portion of the stripe of the gate electrode 24, but by forming another groove portion, it is possible to suppress the occurrence of leakage current between the gate and the drain. .

  According to the second embodiment and the modification thereof, the gate-drain leakage current can be reduced by forming a groove by etching a part between the gate electrode and the drain terminal electrode, and the reliability. It is possible to provide a high-power, high-power, high-power semiconductor device and a method for manufacturing the same.

  According to the second embodiment and its modification, the distance between the gate electrode and the drain terminal electrode is effectively increased by etching the part between the gate electrode and the drain terminal electrode to form the groove. Thus, the surface leakage current between the gate and the drain can be reduced, and a highly reliable and high performance semiconductor device for high power and a manufacturing method thereof can be provided.

[Other embodiments]
As described above, the present invention has been described with reference to the first and second embodiments and the modifications thereof. However, the description and the drawings that constitute a part of this disclosure are exemplary and limit the present invention. Should not be understood. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

  The semiconductor device of the present invention is not limited to a field effect transistor (FET), but a high electron mobility transistor (HEMT), a lateral doped metal-oxide-semiconductor field effect transistor (LDMOS). Needless to say, the present invention can also be applied to an amplifying element such as a heterojunction bipolar transistor (HBT) or a micro electro mechanical systems (MEMS) element.

  As described above, the present invention includes various embodiments not described herein.

  The semiconductor device of the present invention can be applied to a wide range of fields such as an internal matching power amplification element, a power MMIC (Monolithic Microwave Integrated Circuit), a microwave power amplifier, a millimeter wave power amplifier, and a high-frequency MEMS element.

1 is a schematic plan pattern configuration diagram of a semiconductor device according to a first embodiment of the present invention. FIG. FIG. 2 is a schematic cross-sectional structure diagram taken along the line II-II in FIG. FIG. 2 is a schematic sectional view taken along the line II-II in FIG. 1 in which an element isolation region is formed by mesa etching. 1 is a schematic cross-sectional structure example 1 taken along the line II of FIG. 2 is a schematic cross-sectional structure example 2 taken along line II of FIG. 3 is a schematic cross-sectional structure example 3 taken along the line II of FIG. 4 is a schematic cross-sectional structure example 4 taken along the line II of FIG. The typical plane pattern block diagram of the semiconductor device which concerns on the 2nd Embodiment of this invention. The enlarged view of A part of FIG. The typical plane pattern block diagram of the semiconductor device which concerns on the modification of the 2nd Embodiment of this invention. The typical plane pattern block diagram of the semiconductor device which concerns on a prior art example.

Explanation of symbols

10 ... Substrate 12 ... Nitride compound semiconductor layer (GaN layer)
14: Aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1)
20 ... Source electrode 22a ... Source contact 24 ... Gate electrodes 25, 34 ... Element isolation region 22 ... Drain electrode 22a ... Drain contacts 28, 28a, 28b, 28c ... Groove 30 ... Insulating layer 200 ... Source terminal electrode 220 ... Drain terminal electrode 240 ... Gate terminal electrode 260 ... VIA hole AA ... Active region NA ... Inactive region

Claims (16)

A substrate,
A nitride compound semiconductor layer disposed on the substrate;
An active region disposed on the nitride-based compound semiconductor layer and made of an aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1);
An element isolation region formed by ion implantation and isolating the active regions from each other;
A gate electrode, a source electrode, and a drain electrode disposed on the active region surrounded by the element isolation region;
Wherein arranged on the isolation region, each of said gate electrode, said source electrode and a gate connected to terminal electrodes to said drain electrode, and a source terminal and drain terminal electrodes, the drain terminal and the leading end portion of the gate electrode A semiconductor device characterized by facing an electrode across a groove .   The semiconductor device according to claim 1, wherein the groove portion is formed to include a part of the element isolation region between the gate electrode and the drain terminal electrode.   2. The semiconductor device according to claim 1, wherein a tip end portion of the gate electrode extends in the groove portion.   The semiconductor device according to claim 1, wherein the side wall of the groove has a step structure.   The semiconductor device according to claim 1, wherein the groove is plural.   The semiconductor device according to claim 1, wherein the trench has a stripe structure in an arrangement direction of the source electrode and the drain electrode.   2. The semiconductor device according to claim 1, wherein a tip end portion of the gate electrode and the drain terminal electrode are separated by the groove portion. Each of the gate electrode, the source electrode, and the drain electrode includes a plurality of fingers,
A gate terminal electrode, a source terminal electrode and a drain terminal electrode, which are arranged on the element isolation region and formed by bundling a plurality of fingers for each of the gate electrode, the source electrode and the drain electrode,
The semiconductor device according to claim 1, wherein the groove is formed between the gate electrode and the drain terminal electrode. The semiconductor device according to claim 8 , wherein a front end portion of the gate electrode and the drain terminal electrode face each other with the groove portion interposed therebetween .   The semiconductor device according to claim 8, wherein the groove portion is formed to include a part of the element isolation region between the gate electrode having the plurality of fingers and the drain terminal electrode.   9. The semiconductor device according to claim 8, wherein a tip end portion of the gate electrode having the plurality of fingers is extended and disposed in the groove portion.   The semiconductor device according to claim 8, wherein a side wall of the groove has a step structure.   The semiconductor device according to claim 8, wherein the groove is plural.   The semiconductor device according to claim 8, wherein the groove has a stripe structure parallel to an arrangement direction of the plurality of finger electrodes.   The semiconductor device according to claim 8, wherein a tip end portion of the gate electrode and the drain terminal electrode are separated by the groove portion.   The substrate includes a SiC substrate, a GaAs substrate, a GaN substrate, a substrate having a GaN epitaxial layer formed on the SiC substrate, a substrate having a GaN epitaxial layer formed on the Si substrate, and a heterojunction epitaxial layer made of GaN / GaAlN on the SiC substrate. 9. The semiconductor device according to claim 1, comprising: a substrate on which GaN is formed, a substrate in which a GaN epitaxial layer is formed on a sapphire substrate, a sapphire substrate, or a diamond substrate.

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