CN118281062A - Semiconductor device - Google Patents

Abstract

The embodiment of the invention discloses a semiconductor device, which comprises an active area and a passive area surrounding the active area; a substrate; an epitaxial structure; the grid is positioned on one side of the epitaxial structure, far away from the substrate, and extends along a first direction, the grid comprises a first grid subsection and a second grid subsection which are connected with each other, the first grid subsection and the epitaxial structure form schottky contact, and the second grid subsection is positioned in the passive region; at least one gate connection structure comprising a first gate connection section and a second gate connection section connected to each other, the second gate connection section being located in the inactive region; the first gate electrode is not overlapped with the first gate electrode, and at least part of the second gate electrode is electrically connected with the second gate electrode. The semiconductor device can reduce the influence of gate resistance, improve gain and reduce electric leakage by arranging at least one gate connection structure.

Description

A semiconductor device

Technical Field

The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device.

Background technique

The semiconductor material gallium nitride has become a research hotspot due to its large bandgap, high electron saturation drift velocity, high breakdown field strength, and good thermal conductivity. In terms of electronic devices, gallium nitride materials are more suitable for manufacturing high-temperature, high-frequency, high-voltage and high-power devices than silicon and gallium arsenide. It has broad application prospects and has become a research hotspot in the semiconductor industry.

In the field of 5G communications, the bandwidth and high frequency requirements for semiconductor RF devices are very high, and the gate structure design and process flow are closely related to the frequency characteristics of semiconductor devices, which directly affect the operating frequency of semiconductor devices. Therefore, in the design and preparation of semiconductor devices, the design of the gate structure is particularly important, which plays a key role in the reliability of semiconductor devices and the stability of their working performance.

For GaN RF power amplifiers, achieving a balance between improving the power and gain characteristics of the device is required by the application circuit and is also pursued by GaN RF chips. Specifically, in the design of traditional integrated circuit GaN RF chips, the gate power supply is located on one side of the device, while the power supply on the other side of the gate will be affected by the gate resistance and reduced, which will cause the gain to be significantly reduced. Therefore, how to improve the gain of semiconductor devices while further improving the bandwidth and high-frequency performance of semiconductor devices and achieve a performance balance of power amplifiers has become an urgent problem to be solved.

Summary of the invention

The embodiment of the present invention provides a semiconductor device to reduce the influence of gate resistance and improve gain and reduce leakage.

An embodiment of the present invention provides a semiconductor device, comprising an active region and an inactive region surrounding the active region;

The semiconductor device further comprises:

substrate;

an epitaxial structure, located on one side of the substrate;

A gate is located at a side of the epitaxial structure away from the substrate, the gate extends along a first direction, and the first direction is parallel to the plane where the substrate is located; the gate includes a first gate subsection and a second gate subsection connected to each other, the first gate subsection forms a Schottky contact with the epitaxial structure, and the second gate subsection is located in the passive area;

At least one gate connection structure includes a first gate connection section and a second gate connection section connected to each other, wherein the second gate connection section is located in the passive area; along the thickness direction of the semiconductor device, the first gate section does not overlap with the first gate connection section, and at least part of the second gate section is electrically connected to the second gate connection section.

Optionally, the gate connection structure is electrically connected to the gate located on one side of the first gate connection sub-portion along the second direction through the second gate connection sub-portion;

Alternatively, the gate connection structure is electrically connected to the gates located on both sides of the first gate connection section along the second direction through the second gate connection section; the second direction intersects with the first direction and is parallel to the plane where the substrate is located.

Optionally, along a second direction, a size of the first gate connection portion is greater than a size of the first gate portion; and the second direction intersects with the first direction and is parallel to the plane where the substrate is located.

Optionally, along the first direction, a size of the second gate sub-portion is greater than a size of the second gate connecting sub-portion;

The second gate division includes a first sub-section and a second sub-section, the first sub-section is located on a side of the second sub-section away from the active area, and along the second direction, the size of the first sub-section is larger than the size of the second sub-section; the second gate connection division is electrically connected to the first sub-section; the second direction intersects with the first direction and is parallel to the plane where the substrate is located.

Optionally, a size of the second gate connection section in the first direction is smaller than a size of the first gate connection section in the second direction; the second direction intersects with the first direction and is parallel to the plane where the substrate is located.

Optionally, an angle between the second gate connection portion and the first gate connection portion is α, wherein 80°≤α≤100°.

Optionally, the first gate connection section and the second gate connection section are arranged in the same layer.

Optionally, the gate connection structure further includes a third gate connection section, wherein the third gate connection section is located in the active region and is electrically connected to the first gate connection section and the first gate section respectively.

Optionally, the semiconductor device further comprises a source and a source field plate;

The source field plate comprises a field plate body and a field plate branch, wherein the field plate branch is electrically connected to the field plate body and the source electrode respectively;

The field plate branch and the third gate connecting portion are staggered.

Optionally, the semiconductor device further comprises a source electrode, and the source electrode forms an ohmic contact with the epitaxial structure;

Along the thickness direction of the semiconductor device, the first gate connection portion overlaps with the source and is insulated.

Optionally, a dimension of the first gate connection portion in a second direction is smaller than a dimension of the source in the second direction; the second direction intersects with the first direction and is parallel to the plane where the substrate is located.

Optionally, the semiconductor device further comprises a gate pad, wherein along the first direction, the gate pad is located in the inactive area on the first side of the active area, and the first gate sub-portion and the first gate connection sub-portion are both electrically connected to the gate pad;

The semiconductor device further comprises a source field plate, wherein the source field plate is electrically connected to the source;

The first gate connection sub-portion is arranged at the same layer as the source field plate, or the first gate connection sub-portion is arranged at the same layer as the gate pad.

Optionally, the semiconductor device further comprises a source electrode, and the source electrode forms an ohmic contact with the epitaxial structure;

Along the second direction, the first gate connection section is located on the side of the source away from the gate, and the first gate connection section is located between two adjacent sources, and two adjacent transistor cells share the same first gate connection section; the second direction intersects with the first direction and is parallel to the plane where the substrate is located.

Optionally, along the second direction, a size L of the source electrode satisfies L≤60 μm.

Optionally, the semiconductor device further comprises a gate pad, wherein along the first direction, the gate pad is located in the inactive region on the first side of the active region, and the gate and the first gate connecting portion are both electrically connected to the gate pad;

The semiconductor device further comprises a source field plate, wherein the source field plate is electrically connected to the source;

The first gate connection section is arranged in the same layer as the gate; or, the first gate connection section is arranged in the same layer as the source; or, the first gate connection section is arranged in the same layer as the source field plate; or, the first gate connection section is arranged in the same layer as the gate pad.

The semiconductor device provided by the embodiment of the present invention can reduce gate resistance, improve gate gain, and reduce leakage by providing at least one gate connection structure in the semiconductor device and electrically connecting the gate connection structure to at least part of the gate. Furthermore, by electrically connecting the gate connection structure to the gate in the passive area, the setting freedom when the gate connection structure is electrically connected to the gate can be improved on the one hand, and on the other hand, it can avoid affecting the setting mode of the semiconductor device in the active area, thereby ensuring the stability of the semiconductor device in the active area.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present invention;

FIG2 is a schematic cross-sectional structure diagram of the semiconductor device provided in FIG1 along the section line A-A′;

FIG3 is a schematic cross-sectional structure diagram of the semiconductor device provided in FIG1 along the section line B-B′;

FIG4 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present invention;

FIG5 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present invention;

FIG6 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present invention;

7 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present invention;

FIG8 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present invention;

FIG. 9 is a schematic structural diagram of yet another semiconductor device provided by an embodiment of the present invention.

Detailed ways

The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

FIG1 is a schematic diagram of the structure of a semiconductor device provided by an embodiment of the present invention, and FIG2 is a schematic diagram of the cross-sectional structure of the semiconductor device provided in FIG1 along the section line A-A’. FIG3 is a schematic diagram of the cross-sectional structure of the semiconductor device provided in FIG1 along the section line B-B’. Referring to FIG1-FIG3, the semiconductor device 10 includes an active area aa and an inactive area bb surrounding the active area aa; the semiconductor device 10 also includes: a substrate 110; an epitaxial structure 120, located on one side of the substrate 110; a gate 130, located on a side of the epitaxial structure 120 away from the substrate 110, the gate 130 extends along a first direction (the Y direction as shown in FIG1), and the first direction Y is parallel to the plane where the substrate 110 is located; the gate 130 includes a first gate division 1301 and a second gate division 1302 connected to each other, the first gate division 1301 and the second gate division 1302 are connected to each other, and the first gate division 1301 is connected to the first gate division 1302. 301 forms a Schottky contact with the epitaxial structure 120, and the second gate division 1302 is located in the passive area bb; at least one gate connection structure 140 includes a first gate connection division 1401 and a second gate connection division 1402 connected to each other, and the second gate connection division 1402 is located in the passive area bb; along the thickness direction of the semiconductor device 10 (such as the Z direction as shown in Figure 2), the first gate division 1301 does not overlap with the first gate connection division 1401, and at least part of the second gate division 1302 is electrically connected to the second gate connection division 1402.

Specifically, referring to FIGS. 1 to 3 , the active region aa can be understood as a region where two-dimensional electron gas, electrons or holes exist below the active region aa, whose working state and characteristics are affected by the external circuit, and is the active working region of the semiconductor device 10. The passive region bb participates in the work of the semiconductor device 10, but its working state is not affected by the external circuit. For example, the lead-out structure of the electrode in the active region aa can be set in the passive region bb, and the passive region bb can be set around the active region aa.

For example, with continued reference to FIGS. 1 to 3 , the substrate 110 in the semiconductor device 10 may be formed of one of silicon, sapphire, silicon carbide, and gallium arsenide. The epitaxial structure 120 located on one side of the substrate 110 may be formed of one or more of III-V group nitrides such as gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum nitride, or indium aluminum gallium nitride.

Exemplarily, at least one gate connection structure 140 may be made of a conductive metal, for example, a low-resistance conductive material, to reduce the resistance of the gate 130. Specifically, referring to FIG. 1 and FIG. 2 , it should be noted that FIG. 1 is an example of a semiconductor device 10 including a plurality of gates 130. It can be understood that the semiconductor device 10 may also include only one gate 130, that is, a single cell structure having a cell structure of a source 150, a gate 130, and a drain 180. The gate 130 includes a first gate subsection 1301 and a second gate subsection 1302 connected to each other, and the gate connection structure 140 includes a first gate connection subsection 1401 and a second gate connection subsection 1402 connected to each other. The first gate subdivision 1301 includes a portion located in the active area aa and forming a Schottky contact with the epitaxial structure 120, and also includes a portion extending along the first direction Y to connect with the gate pad 170. The first gate subdivision 1301 serves as the gate 130 structure of the semiconductor device 10, controls the conduction and shutdown of the gate 130 in the semiconductor device 10, and further controls the working state of the semiconductor device 10. The first gate connection subdivision 1401 is located in the active area aa and has a large area. As the main adjustment structure of the gate gain, it can reduce the gate resistance and improve the gate gain. The second gate subdivision 1302 and the second gate connection subdivision 1402 are both located in the inactive area bb and serve as the connection subdivision between the gate 130 and the gate connection structure 140, ensuring the normal connection between the gate 130 and the gate connection structure 140, and ensuring that the gate 130 resistance can be reduced. Furthermore, the second gate sub-portion 1302 and the second gate connection sub-portion 1402 are electrically connected in the passive region bb, ensuring that the arrangement of the semiconductor device 10 in the active region aa will not be affected, and the normal operation and performance of the active region aa will not be affected, thereby ensuring the stable performance of the semiconductor device 10. In addition, since the passive region bb has a large arrangement space, the second gate sub-portion 1302 and the second gate connection sub-portion 1402 arranged in the passive region bb can have a large degree of design freedom, which facilitates improving the connection stability between the second gate sub-portion 1302 and the second gate connection sub-portion 1402.

It should be noted that along the thickness direction Z of the semiconductor device 10, the first gate division 1301 and the first gate connection division 1401 do not overlap, that is, along the second direction (the X direction as shown in FIG. 1), the first gate division 1301 and the first gate connection division 1401 do not overlap, that is, they are staggered.

In summary, the semiconductor device provided by the embodiment of the present invention can reduce gate resistance, increase gate gain, and reduce leakage by providing at least one gate connection structure in the semiconductor device and electrically connecting the gate connection structure to at least part of the gate. Furthermore, by electrically connecting the gate connection structure to the gate in the passive area, on the one hand, the degree of freedom of setting when the gate connection structure is electrically connected to the gate can be improved, and on the other hand, it can avoid affecting the setting mode of the semiconductor device in the active area, thereby ensuring the stability of the semiconductor device in the active area.

Optionally, continuing to refer to Figure 1, the gate connection structure 140 is electrically connected to the gate 130 located on one side of the first gate connection division 1401 along the second direction X through the second gate connection division 1402; or, Figure 4 is a structural schematic diagram of another semiconductor device provided by an embodiment of the present invention. As shown in Figure 4, the gate connection structure 140 is electrically connected to the gate 130 located on both sides of the first gate connection division 1401 along the second direction X through the second gate connection division 1402; the second direction X intersects with the first direction Y and is parallel to the plane where the substrate 110 is located.

As a feasible implementation mode, referring to FIG1 , the gate connection structure 140 and the gate 130 located on one side of the first gate connection section 1401 along the second direction X are electrically connected through the second gate connection section 1402 in the connection mode shown in FIG1 . For example, the shape of the gate connection structure 140 can be approximately “L”-shaped. In this way, while ensuring that the setting mode of the gate connection structure 140 is simple, the gate resistance can be reduced by electrically connecting the gate connection structure 140 to the gate 130 located on one side thereof.

As another feasible implementation, Fig. 5 is a schematic diagram of the structure of another semiconductor device provided by an embodiment of the present invention. As shown in Fig. 5, the gate connection structure 140 and the gate 130 located on one side of the first gate connection subsection 1401 along the second direction X can also be electrically connected through the second gate connection subsection 1402 in the connection manner shown in Fig. 5, for example, the shape of the gate connection structure 140 can be approximately "L"-shaped, and at this time, the two gate connection structures 140 can form an arrangement manner that is approximately "back to back", so that any gate 130 can be electrically connected to the gate connection structure 140, further reducing the gate resistance and reducing the gate leakage.

Specifically, referring to FIG. 4 , the gate connection 140 is electrically connected to the gates 130 located on both sides of the first gate connection section 1401 along the second direction X through the second gate connection section 1402. For example, the shape of the gate connection structure 140 can be approximately "T"-shaped, that is, one gate connection structure 140 is electrically connected to the gates 130 located on both sides thereof. On the one hand, it ensures that a large number of gates 130 are electrically connected to the gate connection structure 140, which fully reduces the gate resistance and reduces the gate leakage. On the other hand, it ensures that the setting method of the gate connection structure 140 is simple, reduces the impact on other devices in the active area aa of the semiconductor device 10, and ensures that the preparation process of the gate connection structure 140 is simple.

Optionally, with continued reference to FIG. 1 , along the second direction X, the size of the first gate connection portion 1401 is greater than the size of the first gate portion 1301 ; the second direction X intersects the first direction Y and is parallel to the plane where the substrate 110 is located.

Specifically, along the second direction X, the size of the first gate connection division 1401 is larger than the size of the first gate division 1301, which can be understood as the width of the first gate connection division 1401 in the second direction X is larger than the width of the first gate division 1301 in the second direction X. Since the size of the first gate connection division 1401 is larger, the resistance of the first gate connection division 1401 is smaller. By forming an electrical connection between the gate connection structure 140 and the gate 130, the gate resistance can be fully reduced, thereby improving the gain of the semiconductor device 10.

Exemplarily, along the second direction X, the size of the first gate connection subdivision 1401 is larger than the size of the first gate subdivision 1301. For example, the size of the first gate connection subdivision 1401 may be twice the size of the first gate subdivision 1301, or the size of the first gate connection subdivision 1401 may be 3 times, 3.2 times, etc., of the size of the first gate subdivision 1301. The embodiment of the present invention does not limit the specific relationship between the size of the first gate connection subdivision 1401 and the size of the first gate subdivision 1301. It is only necessary to ensure that the size of the first gate connection subdivision 1401 is larger than the size of the first gate subdivision 1301 to reduce the gate resistance. Further, on the basis of meeting the size requirements of the semiconductor device 10 and the design requirements of the active area aa device, the size of the first gate connection subdivision 1401 in the second direction Y can be designed to be as large as possible to ensure that the gate resistance can be reduced as much as possible.

Optionally, Figure 6 is a structural schematic diagram of another semiconductor device provided by an embodiment of the present invention. Referring to Figure 6, along the first direction Y, the size of the second gate division 1302 is larger than the size of the second gate connection division 1402; the second gate division 1302 includes a first sub-division 13021 and a second sub-division 13022, the first sub-division 13021 is located on the side of the second sub-division 13022 away from the active area aa, and along the second direction X, the size of the first sub-division 13021 is larger than the size of the second sub-division 13022; the second gate connection division 1402 is electrically connected to the first sub-division 13021; the second direction intersects with the first direction and is parallel to the plane where the substrate is located.

Specifically, the size of the second gate sub-portion 1302 in the first direction Y is greater than the size of the second gate connecting sub-portion 1402 in the first direction, so that the contact area between the second gate sub-portion 1302 and the second gate connecting sub-portion 1402 can be ensured.

Furthermore, the second gate division 1302 includes a first sub-division 13021 and a second sub-division 13022, the first sub-division 13021 is located on a side of the second sub-division 13022 away from the active area aa, and along the second direction X, the size of the first sub-division 13021 is larger than the size of the second sub-division 13022; the second gate connection division 1402 is electrically connected to the first sub-division 13021, that is, the connection position between the second gate connection division 1402 and the second gate division 1302 is set at a wider part of the second gate division 1302, which can improve the connection stability, facilitate a stronger connection and a more stable structure, and reduce the connection resistance and connection difficulty between the second gate division 1302 and the second gate connection division 1402 on the other hand.

Optionally, with continued reference to FIG. 6 , the size of the second gate connection sub-portion 1402 in the first direction Y is smaller than the size of the first gate connection sub-portion 1401 in the second direction X; the second direction X intersects the first direction Y and is parallel to the plane where the substrate 110 is located.

Specifically, the size of the second gate connection section 1402 in the first direction Y is smaller than the size of the first gate connection section 1401 in the second direction X, so that the arrangement space of the inactive region bb can be reduced, which is conducive to realizing the miniaturization of the semiconductor device 10 .

Optionally, with continued reference to FIG. 1 , the angle between the second gate connection portion 1402 and the first gate connection portion 1401 is α, and 80°≤α≤100°.

Specifically, the angle α between the second gate connection section 1402 and the first gate connection section 1401 determines the setting space of the passive region bb. Therefore, when the angle α is approximately vertical, the setting space of the passive region bb can be reduced, thereby achieving a miniaturized setting of the semiconductor device 10.

Exemplarily, the angle α between the second gate connection section 1402 and the first gate connection section 1401 can be 90°, that is, the second gate connection section 1402 is perpendicular to the first gate connection section 1401, or the second gate connection section 1402 is approximately perpendicular to the first gate connection section 1401, that is, the angle α between the second gate connection section 1402 and the first gate connection section 1401 satisfies 80°≤α≤100°, which is beneficial to reducing the setting space of the passive area bb and realizing the miniaturization setting of the semiconductor device 10.

Optionally, with continued reference to FIG. 1 , the first gate connection sub-portion 1401 and the second gate connection sub-portion 1402 are disposed in the same layer.

Specifically, referring to FIG. 1 , the first gate connection sub-portion 1401 and the second gate connection sub-portion 1402 can be arranged in the same layer, so that the film structure of the semiconductor device is simple, which can be conducive to realizing the thinness of the semiconductor device 10. In addition, the first gate connection sub-portion 1401 and the second gate connection sub-portion 1402 can be integrally formed in the same process, so that the manufacturing process of the semiconductor device 10 can be simple, the manufacturing difficulty can be reduced, and the manufacturing efficiency can be improved.

Optionally, Fig. 7 is a schematic diagram of the structure of another semiconductor device provided by an embodiment of the present invention. As shown in Fig. 7, the gate connection structure 140 further includes a third gate connection sub-portion 1403, which is located in the active area aa and is electrically connected to the first gate connection sub-portion 1401 and the first gate sub-portion 1301 respectively.

Specifically, the third gate connection sub-portion 1403 is located in the active area aa, and the connection stability between the gate connection structure 140 and the gate 130 can be improved and the connection resistance can be reduced by electrically connecting the third gate connection sub-portion 1403 to the first gate connection sub-portion 1401 and the first gate sub-portion 1301 .

Optionally, FIG8 is a schematic diagram of the structure of another semiconductor device provided by an embodiment of the present invention. As shown in FIG8, the semiconductor device 10 further includes a source 150 and a source field plate 160, the source field plate 160 includes a field plate body 1601 and a field plate branch 1602, the field plate branch 1602 is electrically connected to the field plate body 1601 and the source 150 respectively; the field plate branch 1602 is staggered with the third gate connection subdivision 1403.

Specifically, continuing to refer to Figure 8, the semiconductor device 10 may also include a source field plate 160, and the field plate body 1601 may at least partially overlap with the gate 130, for example, overlap with the side of the gate 130 close to the drain 180, so that the source field plate 160 is extended toward the side of the gate 130, further increasing the modulation effect of the source field plate 160 on the electric field, reducing the electric field accumulation on the side of the gate 130 close to the drain 180, reducing the probability of breakdown on the side of the gate 130 close to the drain 180, and increasing the reliability of the semiconductor device 10.

Further, the source field plate 160 includes a field plate body 1601 and a field plate branch 1602 connected to each other, one end of the field plate branch 1602 is electrically connected to the field plate body 1601, and the other end of the field plate branch 1602 is electrically connected to the source 150, for realizing the electrical connection between the source field plate 160 and the source 150. The field plate branch 1602 and the third gate connection subdivision 1403 are staggered, that is, the projections are not overlapped, and the overlap of the field plate branch 1602 and the third gate connection subdivision 1403 can be avoided, that is, mutual interference is avoided.

Optionally, continuing to refer to FIG. 1 and FIG. 2 , the semiconductor device 10 further includes a source 150 , which forms an ohmic contact with the epitaxial structure 120 ; along the thickness direction Z of the semiconductor device 10 , the first gate connection portion 1401 overlaps with the source 150 and is insulated.

For example, with continued reference to FIG. 1 and FIG. 2 , the first gate connection sub-portion 1401 may be located above the source 150 and overlap with the projection of the source 150. On the one hand, the overlap of the first gate connection sub-portion 1401 with the source 150 does not affect the extraction of the gate 130 signal. On the other hand, the overlap of the first gate connection sub-portion 1401 with the source 150 can reduce the area of the semiconductor device 10.

It should be noted that, with continued reference to FIG. 1 and FIG. 2 , the source 150 can be connected to the back side of the semiconductor device 10 through the source through hole C. Exemplarily, the source through hole C can penetrate the substrate 110 and the epitaxial structure 120, that is, through the source signal input electrode D located on the side of the substrate 110 away from the epitaxial structure 120, it is connected to the source 150, that is, the source 150 is electrically connected to the source signal input electrode D through the source through hole C. Further, the first gate connection subsection 1401 can be located above the source through hole C, that is, the stability of the source through hole C region can be ensured, so that the semiconductor device 10 can work normally.

Optionally, with continued reference to FIG. 1 , a dimension of the first gate connection portion 1401 in the second direction X is smaller than a dimension of the source 150 in the second direction X; the second direction X intersects the first direction Y and is parallel to the plane where the substrate 110 is located.

Specifically, the size of the first gate connection section 1401 in the second direction X is smaller than the size of the source 150 in the second direction X, which can reduce the parasitic capacitance between the gate connection structure 140 and the source 150, thereby reducing the impact on the performance of the semiconductor device 10 and ensuring normal operation of the device.

Optionally, continuing to refer to Figure 8, the semiconductor device 10 also includes a gate pad 170, and along the first direction Y, the gate pad 170 is located in the inactive area bb on the first side of the active area aa, and the first gate division 1301 and the first gate connection division 1401 are both electrically connected to the gate pad 170; the semiconductor device 10 also includes a source field plate 160, and the source field plate 160 is electrically connected to the source 150; the first gate connection division 1401 is arranged on the same layer as the source field plate 160, or the first gate connection division 1401 is arranged on the same layer as the gate pad 170.

Exemplarily, continuing to refer to Figure 8, along the first direction Y, the first gate division 1301 in the active area aa can be connected to the gate pad 170 of the passive area bb through the gate interconnection metal, and the gate 130 can receive the gate voltage signal through the gate pad 170 to ensure the normal operation of the semiconductor device 10.

Specifically, referring to FIG8 , the source field plate 160 is electrically connected to the source 150 to realize the function of the source field plate 160. The first gate connection subdivision 1401 is arranged on the same layer as the source field plate 160, or the first gate connection subdivision 1401 is arranged on the same layer as the gate pad 170, which can simplify the process flow, avoid the setting of redundant film layers, simplify the mask process, and facilitate the thin and light design of the semiconductor device 10.

Optionally, FIG9 is a schematic diagram of another semiconductor device structure provided by an embodiment of the present invention. As shown in FIG9, the semiconductor device 10 further includes a source 150, and the source 150 forms an ohmic contact with the epitaxial structure 120; along the second direction X, the first gate connection subdivision 1401 is located on the side of the source 150 away from the gate 130, and the first gate connection subdivision 1401 is located between two adjacent sources 150, and two adjacent transistor cells share the same first gate connection subdivision 1401; the second direction X intersects with the first direction Y and is parallel to the plane where the substrate 110 is located.

It should be noted that, with reference to FIG. 9 , along the second direction X, a certain distance is maintained between the first gate connecting portion 1401 and two adjacent source electrodes 150 , and the distances are equal.

Specifically, referring to FIG. 9 , along the second direction X, the first gate connection section 1401 is located on the side of the source 150 away from the gate 130, and the first gate connection section 1401 is located between two adjacent sources 150, and two adjacent transistor cells share the same first gate connection section 1401. In this way, the semiconductor device 10 is no longer arranged in which adjacent transistor cells share one source, but becomes an arrangement of a drain 180, a gate 130, a source 150, a gate connection structure 140, a source 150, a gate 130, and a drain 180. That is, adjacent transistor cells share one first gate connection section 1401, and each cell has a source 150, a gate 130, and a drain 180, which can reduce the influence of gate resistance, improve gain, and reduce leakage.

Optionally, with continued reference to FIG. 9 , along the second direction X, a size L of the source electrode 150 satisfies L≤60 μm.

Specifically, the size L of the source 150 satisfies L≤60μm, which is smaller than the size of the source in the existing semiconductor device. It can also be understood that the embodiment of the present invention divides the source in the prior art into two source parts and the two adjacent source parts are spaced a certain distance apart to accommodate the first gate connection part 1401, which can reduce the area of the semiconductor device 10 and reduce the cost.

Optionally, continuing to refer to Figure 9, the semiconductor device 10 also includes a gate pad 170, and along the first direction X, the gate pad 170 is located in the inactive area bb on the first side of the active area aa, and the gate 130 and the first gate connection division 1401 are both electrically connected to the gate pad 170; the semiconductor device 10 also includes a source field plate 160, and the source field plate 160 is electrically connected to the source 150; the first gate connection division 1401 is arranged on the same layer as the gate 130; or, the first gate connection division 1401 is arranged on the same layer as the source 150; or, the first gate connection division 1401 is arranged on the same layer as the source 150; or, the first gate connection division 1401 is arranged on the same layer as the source field plate 160; or, the first gate connection division 1401 is arranged on the same layer as the gate pad 170.

Specifically, referring to Figure 8, the first gate connection section 1401 is arranged on the same layer as the gate 130; or, the first gate connection section 1401 is arranged on the same layer as the source 150; or, the first gate connection section 1401 is arranged on the same layer as the source field plate 160; or, the first gate connection section 1401 is arranged on the same layer as the gate pad 170. This can simplify the process flow. On the one hand, it can avoid the setting of unnecessary film layers and simplify the mask process. On the other hand, it is conducive to realizing a lightweight design of the semiconductor device 10.

Optionally, continuing to refer to Figure 1, the semiconductor device 10 also includes a drain 180 and a drain pad 190 connected to each other; the drain 180 forms an ohmic contact with the epitaxial structure 120; along the first direction Y, the drain pad 190 is located on the second side of the active area aa; along the first direction Y, the second gate connection portion 1402 is located between the active area aa and the drain pad 190.

1, the drain 180 in the active area aa can be connected to the drain pad 190 of the passive area bb through the drain interconnect metal. Specifically, along the first direction Y, the drain pad 190 is located on the second side of the active area aa, that is, the drain 180 can receive the drain 180 voltage signal through the drain pad 190 to ensure the normal operation of the semiconductor device 10.

Furthermore, along the first direction Y, the second gate connection portion 1402 is located between the active region aa and the drain pad 190 , which can further reduce the area of the inactive region bb, thereby reducing the area of the semiconductor device 10 and achieving a miniaturized device configuration.

Optionally, with continued reference to FIG. 2 , the epitaxial structure 120 includes a stacked nucleation layer 1201 , a buffer layer 1202 , a channel layer 1203 , and a barrier layer 1204 ; the channel layer 1203 and the barrier layer 1204 form a heterojunction structure.

Exemplarily, with continued reference to FIG. 2 , the material of the nucleation layer 1201 may be aluminum nitride, which is located between the substrate 110 and the buffer layer 1202 to serve the purpose of bonding the semiconductor material layer to be grown next.

Exemplarily, continuing to refer to Figure 2, the buffer layer 1202 is located on one side of the substrate 110. The material of the buffer layer 1202 may be gallium nitride, and the buffer layer 1202 may include iron atoms, which is conducive to achieving high resistance performance of the buffer layer 1202, ensuring that vertical leakage can be blocked and improving the pinch-off performance of the semiconductor device.

Exemplarily, with continued reference to FIG. 2 , the channel layer 1203 may be a group III nitride, such as Al _x Ga _1-x N, where 0≤x<1, i.e., at the interface between the channel layer 1203 and the barrier layer 1204, that is, the energy of the conduction band edge of the channel layer 1203 is less than the energy of the conduction band edge of the barrier layer 1204. Exemplarily, x=0 indicates that the channel layer 1203 is GaN. The channel layer 1203 may also be other group III nitrides, such as InGaN or AlInGaN. The channel layer 1203 may be undoped or unintentionally doped. The channel layer 1203 may also be a multilayer structure, such as a combination of a superlattice, GaN, or AlGaN.

2 , the barrier layer 1204 may be AlN, AlInN, AlGaN or AlInGaN. The barrier layer 1204 has sufficient thickness and a high enough Al composition to form a significant carrier concentration at the interface between the channel layer 1203 and the barrier layer 1204 .

Exemplarily, with continued reference to FIG. 2 , the channel layer 1203 may include GaN, and the barrier layer 1204 may include AlGaN, that is, the material of the barrier layer 1204 has a higher band gap than the material of the channel layer 1203, and the channel layer 1203 may also have a greater electron affinity than the barrier layer 1204. Due to the band gap difference between the barrier layer 1204 and the channel layer 1203 and the piezoelectric effect at the interface between the barrier layer 1204 and the channel layer 1203, a two-dimensional electron gas (2DEG) is formed between the channel layer 1203 and the barrier layer 1204.

It is understandable that the epitaxial structure 120 may further include a cap layer, which is located on the surface of the barrier layer 1204 away from the substrate 110. The cap layer can reduce the surface state, reduce the surface leakage of the subsequent semiconductor device, and inhibit current collapse, thereby improving the performance and reliability of the epitaxial structure 120 and the semiconductor device 10.

It should be understood that, from the perspective of semiconductor device design, the embodiments of the present invention can reduce the influence of gate resistance, improve gain, and reduce leakage by providing at least one gate connection structure. The semiconductor devices include but are not limited to: high-power high electron mobility transistors (HEMT) operating in high voltage and high current environments, transistors with silicon-on-insulator (SOI) structures, transistors based on gallium arsenide (GaAs), and metal-oxide-semiconductor field-effect transistors (MOSFET), metal-insulator semiconductor field-effect transistors (MISFET), double heterojunction field-effect transistors (DHFET), junction field-effect transistors (JFET), metal-semiconductor field-effect transistors (MESFET), and metal-semiconductor heterojunction field-effect transistors (MESFET). Transistor, referred to as MISHFET) or other field effect transistors. The at least one gate connection structure provided in the semiconductor device provided by the embodiment of the present invention can be widely used in the semiconductor device manufacturing fields such as radio frequency microwave and power electronics. In particular, the advantages of gallium nitride electronic devices with large bandgap, high electron mobility, high breakdown field strength and good thermal conductivity are more obvious, and can better meet the high performance requirements of rapidly developing electronic communications and other fields.

Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims (15)

1. A semiconductor device comprising an active region and a non-active region surrounding the active region;

the semiconductor device further includes:

a substrate;

an epitaxial structure located on one side of the substrate;

The grid electrode is positioned on one side of the epitaxial structure, far away from the substrate, and extends along a first direction, and the first direction is parallel to the plane of the substrate; the grid comprises a first grid subsection and a second grid subsection which are connected with each other, the first grid subsection and the epitaxial structure form schottky contact, and the second grid subsection is positioned in the passive region;

At least one gate connection structure comprising a first gate connection section and a second gate connection section connected to each other, the second gate connection section being located in the inactive region; the first gate electrode subsection and the first gate electrode connection subsection are not overlapped in the thickness direction of the semiconductor device, and at least part of the second gate electrode subsection is electrically connected with the second gate electrode connection subsection.

2. The semiconductor device according to claim 1, wherein the gate connection structure is electrically connected to the gate electrode on a side of the first gate connection section in a second direction through the second gate connection section;

Or the grid connection structure is electrically connected with the grid positioned at two sides of the first grid connection subsection along the second direction through the second grid connection subsection; the second direction intersects the first direction and is parallel to the plane of the substrate.

3. The semiconductor device of claim 1, wherein a size of the first gate connection section is greater than a size of the first gate section in the second direction; the second direction intersects the first direction and is parallel to the plane of the substrate.

4. The semiconductor device of claim 1, wherein a size of the second gate segment is greater than a size of the second gate connection segment along the first direction;

the second grid subsection comprises a first sub-part and a second sub-part, the first sub-part is positioned on one side of the second sub-part far away from the active area, and the size of the first sub-part is larger than that of the second sub-part along the second direction; the second grid connection subsection is electrically connected with the first sub-section; the second direction intersects the first direction and is parallel to the plane of the substrate.

5. The semiconductor device of claim 1, wherein a dimension of the second gate connection section in the first direction is smaller than a dimension of the first gate connection section in a second direction; the second direction intersects the first direction and is parallel to the plane of the substrate.

6. The semiconductor device of claim 1, wherein an angle α between the second gate connection section and the first gate connection section is 80 ° or less and 100 °.

7. The semiconductor device of claim 1, wherein the first gate connection section is co-layer with the second gate connection section.

8. The semiconductor device of claim 1, wherein the gate connection structure further comprises a third gate connection segment located in the active region and electrically connected to the first gate connection segment and the first gate segment, respectively.

9. The semiconductor device of claim 8, further comprising a source and a source field plate;

The source electrode field plate comprises a field plate main body and a field plate branch, and the field plate branch is respectively and electrically connected with the field plate main body and the source electrode;

the field plate branches and the third grid connection parts are staggered.

10. The semiconductor device of claim 1, further comprising a source electrode forming an ohmic contact with the epitaxial structure;

The first gate connection part is overlapped with the source electrode and is arranged in an insulating manner along the thickness direction of the semiconductor device.

11. The semiconductor device of claim 10, wherein a dimension of the first gate connection section in a second direction is smaller than a dimension of the source electrode in the second direction; the second direction intersects the first direction and is parallel to the plane of the substrate.

12. The semiconductor device of claim 10, further comprising a gate pad located in the inactive region on a first side of the active region along the first direction, the first gate segment and the first gate connection segment each being electrically connected to the gate pad;

The semiconductor device further comprises a source field plate, wherein the source field plate is electrically connected with the source;

The first gate connection part is arranged on the same layer as the source electrode field plate, or the first gate connection part is arranged on the same layer as the gate electrode bonding pad.

13. The semiconductor device of claim 1, further comprising a source electrode forming an ohmic contact with the epitaxial structure;

the first grid connection subsection is positioned at one side of the source electrode far away from the grid electrode along the second direction, the first grid connection subsection is positioned between two adjacent source electrodes, and two adjacent transistor cells share the same first grid connection subsection; the second direction intersects the first direction and is parallel to the plane of the substrate.

14. The semiconductor device according to claim 13, wherein a dimension L of the source electrode in the second direction satisfies l+.60 μm.

15. The semiconductor device of claim 13, further comprising a gate pad located in the inactive region on a first side of the active region along the first direction, the gate and the first gate connection section each being electrically connected to the gate pad;

The semiconductor device further comprises a source field plate, wherein the source field plate is electrically connected with the source;

The first grid connection subsection and the grid are arranged on the same layer; or the first grid connection subsection and the source electrode are arranged in the same layer; or the first grid connection subsection and the source electrode field plate are arranged on the same layer; or the first grid connection subsection and the grid bonding pad are arranged in the same layer.