CN118281062A - Semiconductor device - Google Patents

Abstract

The embodiment of the invention discloses a semiconductor device, which comprises an active area and a passive area surrounding the active area; a substrate; an epitaxial structure; the grid is positioned on one side of the epitaxial structure, far away from the substrate, and extends along a first direction, the grid comprises a first grid subsection and a second grid subsection which are connected with each other, the first grid subsection and the epitaxial structure form schottky contact, and the second grid subsection is positioned in the passive region; at least one gate connection structure comprising a first gate connection section and a second gate connection section connected to each other, the second gate connection section being located in the inactive region; the first gate electrode is not overlapped with the first gate electrode, and at least part of the second gate electrode is electrically connected with the second gate electrode. The semiconductor device can reduce the influence of gate resistance, improve gain and reduce electric leakage by arranging at least one gate connection structure.

Description

Semiconductor device

Technical Field

The invention relates to the technical field of semiconductors, in particular to a semiconductor device.

Background

The semiconductor material gallium nitride has become a current research hot spot due to the characteristics of large forbidden bandwidth, high electron saturation drift speed, high breakdown field intensity, good heat conduction performance and the like. In the aspect of electronic devices, the gallium nitride material is more suitable for manufacturing high-temperature, high-frequency, high-voltage and high-power devices than silicon and gallium arsenide, has wide application prospect and becomes a hot spot for the current research of the semiconductor industry.

In the field of 5G communication, the bandwidth and high frequency requirements of a semiconductor radio frequency device are very high, and the design of a grid structure and the technological process are closely related to the frequency characteristic of the semiconductor device, so that the working frequency of the semiconductor device is directly influenced. Therefore, in the design and fabrication of semiconductor devices, the design of the gate structure is particularly important, playing a key role in the reliability and stability of the operation performance of the semiconductor devices.

For gallium nitride radio frequency power amplifiers, achieving a balance that improves the power and gain characteristics of the device is a requirement for application circuitry, and is also sought after for gallium nitride radio frequency chips. Specifically, in the conventional integrated circuit gallium nitride radio frequency chip design, the gate power supply is located at a single side of the device, and the power supply at the other side of the gate is reduced due to the influence of the gate resistance, which causes a problem of significantly reduced gain. Therefore, how to further improve the bandwidth and high frequency performance of the semiconductor device while improving the gain of the semiconductor device, and to achieve the performance balance of the power amplifier are the problems that are urgently needed to be solved at present.

Disclosure of Invention

The embodiment of the invention provides a semiconductor device, which is used for reducing the influence of grid resistance, improving gain and reducing electric leakage.

The embodiment of the invention provides a semiconductor device, which comprises an active area and a passive area surrounding the active area;

the semiconductor device further includes:

a substrate;

an epitaxial structure located on one side of the substrate;

The grid electrode is positioned on one side of the epitaxial structure, far away from the substrate, and extends along a first direction, and the first direction is parallel to the plane of the substrate; the grid comprises a first grid subsection and a second grid subsection which are connected with each other, the first grid subsection and the epitaxial structure form schottky contact, and the second grid subsection is positioned in the passive region;

At least one gate connection structure comprising a first gate connection section and a second gate connection section connected to each other, the second gate connection section being located in the inactive region; the first gate electrode subsection and the first gate electrode connection subsection are not overlapped in the thickness direction of the semiconductor device, and at least part of the second gate electrode subsection is electrically connected with the second gate electrode connection subsection.

Optionally, the gate connection structure is electrically connected to the gate located on one side of the first gate connection section along the second direction through the second gate connection section;

Or the grid connection structure is electrically connected with the grid positioned at two sides of the first grid connection subsection along the second direction through the second grid connection subsection; the second direction intersects the first direction and is parallel to the plane of the substrate.

Optionally, in the second direction, the size of the first gate connection part is larger than the size of the first gate part; the second direction intersects the first direction and is parallel to the plane of the substrate.

Optionally, the size of the second gate segment is greater than the size of the second gate connection segment along the first direction;

the second grid subsection comprises a first sub-part and a second sub-part, the first sub-part is positioned on one side of the second sub-part far away from the active area, and the size of the first sub-part is larger than that of the second sub-part along the second direction; the second grid connection subsection is electrically connected with the first sub-section; the second direction intersects the first direction and is parallel to the plane of the substrate.

Optionally, the second gate connection part has a smaller dimension in the first direction than the first gate connection part; the second direction intersects the first direction and is parallel to the plane of the substrate.

Optionally, an included angle between the second gate connection part and the first gate connection part is alpha, wherein alpha is more than or equal to 80 degrees and less than or equal to 100 degrees.

Optionally, the first gate connection part and the second gate connection part are arranged in the same layer.

Optionally, the gate connection structure further includes a third gate connection portion, where the third gate connection portion is located in the active area and is electrically connected to the first gate connection portion and the first gate portion, respectively.

Optionally, the semiconductor device further comprises a source and a source field plate;

The source electrode field plate comprises a field plate main body and a field plate branch, and the field plate branch is respectively and electrically connected with the field plate main body and the source electrode;

the field plate branches and the third grid connection parts are staggered.

Optionally, the semiconductor device further includes a source, and the source forms ohmic contact with the epitaxial structure;

The first gate connection part is overlapped with the source electrode and is arranged in an insulating manner along the thickness direction of the semiconductor device.

Optionally, the dimension of the first gate connection part in the second direction is smaller than the dimension of the source electrode in the second direction; the second direction intersects the first direction and is parallel to the plane of the substrate.

Optionally, the semiconductor device further includes a gate pad, and along the first direction, the gate pad is located in a non-active region on a first side of the active region, and the first gate segment and the first gate connection segment are electrically connected to the gate pad;

The semiconductor device further comprises a source field plate, wherein the source field plate is electrically connected with the source;

The first gate connection part is arranged on the same layer as the source electrode field plate, or the first gate connection part is arranged on the same layer as the gate electrode bonding pad.

Optionally, the semiconductor device further includes a source, and the source forms ohmic contact with the epitaxial structure;

the first grid connection subsection is positioned at one side of the source electrode far away from the grid electrode along the second direction, the first grid connection subsection is positioned between two adjacent source electrodes, and two adjacent transistor cells share the same first grid connection subsection; the second direction intersects the first direction and is parallel to the plane of the substrate.

Optionally, along the second direction, the dimension L of the source satisfies l.ltoreq.60 μm.

Optionally, the semiconductor device further includes a gate pad, and along the first direction, the gate pad is located in a passive region on a first side of the active region, and the gate and the first gate connection part are electrically connected to the gate pad;

The semiconductor device further comprises a source field plate, wherein the source field plate is electrically connected with the source;

The first grid connection subsection and the grid are arranged on the same layer; or the first grid connection subsection and the source electrode are arranged in the same layer; or the first grid connection subsection and the source electrode field plate are arranged on the same layer; or the first grid connection subsection and the grid bonding pad are arranged in the same layer.

According to the semiconductor device provided by the embodiment of the invention, at least one gate connecting structure is arranged in the semiconductor device, and the at least part of the gate is electrically connected through the gate connecting structure, so that the gate resistance can be reduced, the gate gain can be improved, and the electric leakage can be reduced. Furthermore, the grid connection structure and the grid are electrically connected in the passive region, so that on one hand, the setting freedom degree of the grid connection structure and the grid during electrical connection can be improved, on the other hand, the setting mode of the semiconductor device in the active region can be prevented from being influenced, and the stability of the semiconductor device in the active region is ensured.

Drawings

Fig. 1 is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention;

FIG. 2 is a schematic cross-sectional structure of the semiconductor device provided in FIG. 1 along section line A-A';

FIG. 3 is a schematic cross-sectional structure of the semiconductor device provided in FIG. 1 along section line B-B';

fig. 4 is a schematic structural diagram of another semiconductor device according to an embodiment of the present invention;

Fig. 5 is a schematic structural diagram of another semiconductor device according to an embodiment of the present invention;

Fig. 6 is a schematic structural diagram of another semiconductor device according to an embodiment of the present invention;

fig. 7 is a schematic structural diagram of another semiconductor device according to an embodiment of the present invention;

fig. 8 is a schematic structural diagram of another semiconductor device according to an embodiment of the present invention;

Fig. 9 is a schematic structural diagram of another semiconductor device according to an embodiment of the present invention.

Detailed Description

The invention is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting thereof. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present invention are shown in the drawings.

Fig. 1 is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention, and fig. 2 is a schematic structural diagram of a cross-section of the semiconductor device along a line A-A' shown in fig. 1. Fig. 3 is a schematic cross-sectional structure of the semiconductor device provided in fig. 1 along a section line B-B'. Referring to fig. 1-3, the semiconductor device 10 includes an active region aa and a inactive region bb surrounding the active region aa; the semiconductor device 10 further includes: a substrate 110; an epitaxial structure 120 located on one side of the substrate 110; a gate 130, located on a side of the epitaxial structure 120 away from the substrate 110, the gate 130 extending along a first direction (Y direction as shown in fig. 1), the first direction Y being parallel to a plane of the substrate 110; gate 130 includes a first gate segment 1301 and a second gate segment 1302 connected to each other, first gate segment 1301 forming a schottky contact with epitaxial structure 120, second gate segment 1302 being located in inactive region bb; at least one gate connection structure 140 comprising a first gate connection part 1401 and a second gate connection part 1402 connected to each other, the second gate connection part 1402 being located in the inactive region bb; in the thickness direction (Z direction as shown in fig. 2) of the semiconductor device 10, the first gate electrode section 1301 does not overlap with the first gate electrode connection section 1401, and at least part of the second gate electrode section 1302 is electrically connected with the second gate electrode connection section 1402.

Specifically, with continued reference to fig. 1-3, the active region aa may be understood as a region under which two-dimensional electron gas, electrons or holes exist, and its operating state and characteristics are affected by external circuitry, which is an active operating region of the semiconductor device 10. The inactive region bb participates in the operation of the semiconductor device 10, but its operation state is not affected by an external circuit, for example, an extraction structure of an electrode in the active region aa may be provided in the inactive region bb, and the inactive region bb may be provided around the active region aa.

1-3, The substrate 110 in the semiconductor device 10 may be formed of one of silicon, sapphire, silicon carbide, gallium arsenide. The epitaxial structure 120 on one side of the substrate 110 may be formed of one or more of gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum nitride, or indium aluminum gallium nitride.

Illustratively, the at least one gate connection structure 140 may be composed of a conductive metal, such as a low resistance conductive material, to facilitate reducing the resistance of the gate 130. Specifically, with continued reference to fig. 1 and 2, fig. 1 illustrates that semiconductor device 10 includes a plurality of gates 130, and it is understood that semiconductor device 10 may also include only one gate 130, i.e., a single cell structure with a unit cell structure including a source 150, a gate 130, and a drain 180. Gate 130 includes a first gate segment 1301 and a second gate segment 1302 that are connected to each other, and gate connection structure 140 includes a first gate connection segment 1401 and a second gate connection segment 1402 that are connected to each other. The first gate portion 1301 includes a portion located in the active area aa and forming schottky contact with the epitaxial structure 120, and further includes a portion extending along the first direction Y to connect with the gate pad 170, where the first gate portion 1301 is used as a gate 130 structure of the semiconductor device 10, and controls on and off of the gate 130 in the semiconductor device 10, so as to control an operating state of the semiconductor device 10. The first gate connection portion 1401 is located in the active area aa and has a larger area, and is used as a main adjusting structure of the gate gain, so as to reduce the gate resistance and improve the gate gain. The second gate subsection 1302 and the second gate connection subsection 1402 are both located in the inactive area bb and serve as connection subsections between the gate 130 and the gate connection structure 140, so that normal connection between the gate 130 and the gate connection structure 140 is ensured, and the resistance of the gate 130 can be reduced. Further, the second gate subsection 1302 and the second gate connection subsection 1402 are electrically connected in the inactive area bb, so that the arrangement mode of the semiconductor device 10 in the active area aa is not affected, the normal operation and performance of the active area aa are not affected, and the performance stability of the semiconductor device 10 is ensured. In addition, since the inactive area bb has a larger installation space, the second gate subsection 1302 and the second gate connection subsection 1402 provided in the inactive area bb may have a larger degree of freedom in design, so as to facilitate the improvement of the connection stability between the second gate subsection 1302 and the second gate connection subsection 1402.

Note that, in the thickness direction Z of the semiconductor device 10, the first gate portion 1301 and the first gate connection portion 1401 do not overlap, that is, are disposed offset, in the second direction (X direction as shown in fig. 1).

In summary, in the semiconductor device provided by the embodiment of the invention, at least one gate connection structure is arranged in the semiconductor device, and the semiconductor device is electrically connected with at least part of the gates through the gate connection structure, so that the gate resistance can be reduced, the gate gain can be improved, and the electric leakage can be reduced. Furthermore, the grid connection structure and the grid are electrically connected in the passive region, so that on one hand, the setting freedom degree of the grid connection structure and the grid during electrical connection can be improved, on the other hand, the setting mode of the semiconductor device in the active region can be prevented from being influenced, and the stability of the semiconductor device in the active region is ensured.

Optionally, with continued reference to fig. 1, the gate connection structure 140 is electrically connected to the gate 130 located on one side of the first gate connection part 1401 along the second direction X through the second gate connection part 1402; or fig. 4 is a schematic structural diagram of another semiconductor device according to an embodiment of the present invention, as shown in fig. 4, the gate connection structure 140 is electrically connected to the gates 130 located on two sides of the first gate connection portion 1401 along the second direction X through the second gate connection portion 1402; the second direction X intersects the first direction Y and is parallel to the plane of the substrate 110.

As a possible embodiment, with continued reference to fig. 1, the gate connection structure 140 may be electrically connected to the gate 130 located on one side of the first gate connection part 1401 along the second direction X through the second gate connection part 1402 in a connection manner as shown in fig. 1, for example, the shape of the gate connection structure 140 may be approximately L-shaped, so that the gate resistance may be reduced by electrically connecting the gate connection structure 140 to the gate 130 located on one side thereof on the basis of ensuring that the arrangement manner of the gate connection structure 140 is simple.

As another possible implementation manner, fig. 5 is a schematic structural diagram of another semiconductor device provided in an embodiment of the present invention. As shown in fig. 5, the gate connection structure 140 is electrically connected to the gate 130 located on the side of the first gate connection portion 1401 along the second direction X through the second gate connection portion 1402, and may be in a connection manner as shown in fig. 5, for example, the shape of the gate connection structure 140 may be approximately "L", and at this time, the two gate connection structures 140 may be arranged approximately "back-to-back", so as to ensure that any gate 130 may be electrically connected to the gate connection structure 140, thereby further reducing the gate resistance and reducing the gate leakage current.

Specifically, with continued reference to fig. 4, the gate connection 140 is electrically connected to the gates 130 located at two sides of the first gate connection portion 1401 along the second direction X through the second gate connection portion 1402, for example, the shape of the gate connection structure 140 may be approximately "T", that is, one gate connection structure 140 is electrically connected to the gates 130 located at two sides thereof, so that on one hand, the number of the gates 130 electrically connected to the gate connection structure 140 is ensured to be large, the gate resistance is sufficiently reduced, and the gate leakage current is reduced, on the other hand, the arrangement mode of the gate connection structure 140 is ensured to be simple, the influence caused by other devices in the active area aa of the semiconductor device 10 is reduced, and the manufacturing process of the gate connection structure 140 is ensured to be simple.

Optionally, with continued reference to fig. 1, in the second direction X, the size of the first gate connection section 1401 is greater than the size of the first gate section 1301; the second direction X intersects the first direction Y and is parallel to the plane of the substrate 110.

Specifically, the size of the first gate connection part 1401 is greater than the size of the first gate part 1301 along the second direction X, which may be understood as that the width of the first gate connection part 1401 in the second direction X is greater than the width of the first gate part 1301 in the second direction X, and thus the resistance of the first gate connection part 1401 is small due to the large size of the first gate connection part 1401, the gate resistance may be sufficiently reduced by forming an electrical connection between the gate connection structure 140 and the gate 130, and the gain of the semiconductor device 10 may be improved.

For example, along the second direction X, the size of the first gate connection portion 1401 is greater than the size of the first gate portion 1301, for example, the size of the first gate connection portion 1401 may be 2 times the size of the first gate portion 1301, or the size of the first gate connection portion 1401 may be 3 times, 3.2 times, or the like, which is greater than the size of the first gate portion 1301, and the specific relationship between the size of the first gate connection portion 1401 and the size of the first gate portion 1301 is not limited, so long as the size of the first gate connection portion 1401 is ensured to be greater than the size of the first gate portion 1301, and the gate resistance may be reduced. Further, on the basis of meeting the size requirement of the semiconductor device 10 and the design requirement of the active area aa device, the size of the first gate connection portion 1401 in the second direction Y may be designed to be as large as possible, so as to ensure that the gate resistance may be reduced as much as possible.

Optionally, fig. 6 is a schematic structural diagram of still another semiconductor device according to an embodiment of the present invention, and referring to fig. 6, a size of the second gate subsection 1302 is larger than a size of the second gate connection subsection 1402 along the first direction Y; the second gate subsection 1302 includes a first sub-portion 13021 and a second sub-portion 13022, the first sub-portion 13021 being located at a side of the second sub-portion 13022 away from the active area aa, and a size of the first sub-portion 13021 being larger than a size of the second sub-portion 13022 along the second direction X; the second gate connection section 1402 is electrically connected to the first sub-section 13021; the second direction intersects the first direction and is parallel to the plane of the substrate.

Specifically, the size of the second gate subsection 1302 in the first direction Y is greater than the size of the second gate connection subsection 1402 in the first direction, so that the contact area between the second gate subsection 1302 and the second gate connection subsection 1402 can be ensured.

Further, the second gate subsection 1302 includes a first sub-portion 13021 and a second sub-portion 13022, the first sub-portion 13021 is located at a side of the second sub-portion 13022 away from the active area aa, and a size of the first sub-portion 13021 is larger than a size of the second sub-portion 13022 along the second direction X; the second gate connection part 1402 is electrically connected with the first sub-part 13021, that is, the connection position of the second gate connection part 1402 and the second gate connection part 1302 is set at a wider part in the second gate part 1302, so that on one hand, the connection stability can be improved, the connection is more firm, the structure is more stable, and on the other hand, the connection resistance and the connection difficulty between the second gate part 1302 and the second gate connection part 1402 can be reduced.

Alternatively, with continued reference to fig. 6, the second gate connection section 1402 has a smaller dimension in the first direction Y than the first gate connection section 1401; the second direction X intersects the first direction Y and is parallel to the plane of the substrate 110.

Specifically, the size of the second gate connection part 1402 in the first direction Y is smaller than the size of the first gate connection part 1401 in the second direction X, so that the arrangement space of the inactive region bb can be reduced, which is advantageous for realizing the miniaturized arrangement of the semiconductor device 10.

Optionally, with continued reference to FIG. 1, the angle between the second gate connection section 1402 and the first gate connection section 1401 is α,80 α.ltoreq.α.ltoreq.100 °.

Specifically, the included angle α between the second gate connection portion 1402 and the first gate connection portion 1401 determines the installation space of the inactive area bb, so that when the included angle α is approximately vertical, the installation space of the inactive area bb can be reduced, and thus the miniaturized installation of the semiconductor device 10 can be realized.

Illustratively, the included angle α between the second gate connection part 1402 and the first gate connection part 1401 may be 90 °, i.e., the second gate connection part 1402 is perpendicular to the first gate connection part 1401, or the second gate connection part 1402 is approximately perpendicular to the first gate connection part 1401, i.e., the included angle α between the second gate connection part 1402 and the first gate connection part 1401 satisfies 80 ° or more and α or less than 100 °, which is advantageous in reducing the installation space of the inactive region bb and achieving the miniaturized installation of the semiconductor device 10.

Optionally, with continued reference to fig. 1, the first gate connection section 1401 is arranged in the same layer as the second gate connection section 1402.

Specifically, with continued reference to fig. 1, the first gate connection portion 1401 and the second gate connection portion 1402 may be disposed in the same layer, so that the film structure of the semiconductor device is simple, which is beneficial to realizing the light and thin structure of the semiconductor device 10. And the first gate connection part 1401 and the second gate connection part 1402 can be integrally formed in the same process, so that the manufacturing process of the semiconductor device 10 can be ensured to be simple, the manufacturing difficulty is reduced, and the manufacturing efficiency is further improved.

Optionally, fig. 7 is a schematic structural diagram of another semiconductor device according to an embodiment of the present invention. As shown in fig. 7, the gate connection structure 140 further includes a third gate connection part 1403, and the third gate connection part 1403 is located in the active area aa and is electrically connected to the first gate connection part 1401 and the first gate part 1301, respectively.

Specifically, the third gate connection part 1403 is located in the active region aa, and the connection stability between the gate connection structure 140 and the gate 130 can be improved and the connection resistance can be reduced by electrically connecting the third gate connection part 1403 with the first gate connection part 1401 and the first gate part 1301.

Optionally, fig. 8 is a schematic structural diagram of another semiconductor device according to an embodiment of the present invention. As shown in fig. 8, the semiconductor device 10 further includes a source 150 and a source field plate 160, the source field plate 160 including a field plate body 1601 and a field plate branch 1602, the field plate branch 1602 being electrically connected to the field plate body 1601 and the source 150, respectively; the field plate branch 1602 is offset from the third gate connection section 1403.

Specifically, with continued reference to fig. 8, semiconductor device 10 may further include a source field plate 160, and field plate body 1601 may at least partially overlap gate 130, e.g., overlap a side of gate 130 adjacent drain 180, such that source field plate 160 extends toward gate 130, further increasing the modulation of the electric field by source field plate 160, reducing the accumulation of the electric field on the side of gate 130 adjacent drain 180, reducing the probability of breakdown of gate 130 adjacent drain 180, and increasing the reliability of semiconductor device 10.

Further, the source field plate 160 comprises a field plate body 1601 and a field plate branch 1602 connected to each other, one end of the field plate branch 1602 is electrically connected to the field plate body 1601, and the other end of the field plate branch 1602 is electrically connected to the source 150 for electrically connecting the source field plate 160 to the source 150. The offset arrangement of the field plate branch 1602 with respect to the third gate connection portion 1403, i.e. the projection is not overlapped, prevents the field plate branch 1602 from overlapping the third gate connection portion 1403, i.e. from interfering with one another.

Optionally, with continued reference to fig. 1 and 2, the semiconductor device 10 further includes a source 150, the source 150 forming an ohmic contact with the epitaxial structure 120; the first gate connection part 1401 is overlapped with and insulated from the source electrode 150 in the thickness direction Z of the semiconductor device 10.

For example, with continued reference to fig. 1 and 2, the first gate connection portion 1401 may be located at a position above the source 150, overlapping the source 150 projection, on the one hand, overlapping the source 150 by the first gate connection portion 1401 does not affect the extraction of the gate 130 signal. On the other hand, overlapping the first gate connection part 1401 with the source electrode 150 may reduce the area of the semiconductor device 10.

It should be noted that, with continued reference to fig. 1 and 2, the source 150 may be connected to the back surface of the semiconductor device 10 through a source via C, and the source via C may extend through the substrate 110 and the epitaxial structure 120, i.e., be connected to the source 150 through a source signal input electrode D located on a side of the substrate 110 away from the epitaxial structure 120, that is, the source 150 is electrically connected to the source signal input electrode D through the source via C. Further, the first gate connection portion 1401 may be located above the source via C, i.e. the stability of the source via C region may be ensured, so that the semiconductor device 10 may work normally.

Optionally, with continued reference to fig. 1, the first gate connection portion 1401 has a smaller dimension in the second direction X than the source 150; the second direction X intersects the first direction Y and is parallel to the plane of the substrate 110.

Specifically, the size of the first gate connection portion 1401 in the second direction X is smaller than the size of the source 150 in the second direction X, so that parasitic capacitance between the gate connection structure 140 and the source 150 can be reduced, further, the influence on the performance of the semiconductor device 10 can be reduced, and normal operation of the device can be ensured.

Optionally, with continued reference to fig. 8, the semiconductor device 10 further includes a gate pad 170, the gate pad 170 being located in the inactive region bb on a first side of the active region aa along the first direction Y, the first gate segment 1301 and the first gate connection segment 1401 being electrically connected to the gate pad 170; the semiconductor device 10 further includes a source field plate 160, the source field plate 160 being electrically connected to the source 150; the first gate connection part 1401 is provided in the same layer as the source field plate 160, or the first gate connection part 1401 is provided in the same layer as the gate pad 170.

Illustratively, with continued reference to fig. 8, in the first direction Y, a first gate subsection 1301 within the active region aa may be connected to the gate pad 170 of the inactive region bb through a gate interconnect metal, and the gate 130 may receive a gate voltage signal through the gate pad 170, ensuring proper operation of the semiconductor device 10.

Specifically, with continued reference to fig. 8, the source field plate 160 is electrically connected to the source 150, implementing the source field plate 160 function. The first gate connection part 1401 and the source field plate 160 are arranged in the same layer, or the first gate connection part 1401 and the gate pad 170 are arranged in the same layer, so that the process flow can be simplified, on one hand, the arrangement of redundant film layers can be avoided, the mask process is simplified, and on the other hand, the light and thin design of the semiconductor device 10 is facilitated.

Optionally, fig. 9 is a schematic structural diagram of another semiconductor device according to an embodiment of the present invention. As shown in fig. 9, the semiconductor device 10 further includes a source 150, the source 150 forming an ohmic contact with the epitaxial structure 120; along the second direction X, the first gate connection part 1401 is located at a side of the source 150 away from the gate 130, and the first gate connection part 1401 is located between two adjacent source 150, and two adjacent transistor cells share the same first gate connection part 1401; the second direction X intersects the first direction Y and is parallel to the plane of the substrate 110.

With continued reference to fig. 9, a distance is maintained between the first gate connection portion 1401 and the adjacent two sources 150 in the second direction X, and the distance is equal.

Specifically, with continued reference to fig. 9, along the second direction X, the first gate connection portion 1401 is located on a side of the source 150 away from the gate 130, and the first gate connection portion 1401 is located between two adjacent sources 150, and two adjacent transistor cells share the same first gate connection portion 1401, so that the semiconductor device 10 no longer shares 1 source arrangement between adjacent transistor cells, but becomes the drain 180, the gate 130, the source 150, the gate connection structure 140, the source 150, the gate 130, and the drain 180 so arranged, that is, 1 first gate connection portion 1401 is shared between adjacent transistor cells, and the source 150, the gate 130, and the drain 180 are respectively located in each cell, which can reduce the influence of the gate resistance and can improve the gain, and reduce the leakage.

Alternatively, with continued reference to FIG. 9, the dimension L of the source 150 along the second direction X satisfies L.ltoreq.60 μm.

Specifically, the dimension L of the source 150 satisfies L being less than or equal to 60 μm and smaller than the dimension of the source in the conventional semiconductor device, and it can be understood that the embodiment of the present invention divides the source in the prior art into two source sections and the two adjacent source sections are spaced apart by a certain distance to accommodate the first gate connection section 1401, so that the area of the semiconductor device 10 can be reduced and the cost can be reduced.

Optionally, with continued reference to fig. 9, the semiconductor device 10 further includes a gate pad 170, the gate pad 170 being located in the inactive region bb on a first side of the active region aa along the first direction X, the gate 130 and the first gate connection portion 1401 being electrically connected to the gate pad 170; the semiconductor device 10 further includes a source field plate 160, the source field plate 160 being electrically connected to the source 150; the first gate connection part 1401 is arranged at the same layer as the gate 130; or the first gate connection part 1401 is arranged in the same layer as the source 150; or the first gate connection part 1401 is arranged in the same layer as the source field plate 160; or the first gate connection part 1401 is provided in the same layer as the gate pad 170.

Specifically, with continued reference to fig. 8, a first gate connection section 1401 is provided in the same layer as the gate 130; or the first gate connection part 1401 is arranged in the same layer as the source 150; or the first gate connection part 1401 is arranged in the same layer as the source field plate 160; or the first gate connection part 1401 and the gate pad 170 are arranged on the same layer, so that the process flow can be simplified, on one hand, the arrangement of redundant film layers can be avoided, the mask process can be simplified, and on the other hand, the light and thin design of the semiconductor device 10 can be realized.

Optionally, with continued reference to fig. 1, semiconductor device 10 further includes an interconnected drain 180 and drain pad 190; the drain 180 forms an ohmic contact with the epitaxial structure 120; the drain pad 190 is located on the second side of the active area aa along the first direction Y; along the first direction Y, the second gate connection section 1402 is located between the active region aa and the drain pad 190.

Illustratively, with continued reference to FIG. 1, the drain 180 within the active region aa may be connected to the drain pad 190 of the inactive region bb by a drain interconnect metal. Specifically, along the first direction Y, the drain pad 190 is located at the second side of the active area aa, that is, the drain 180 may receive the drain 180 voltage signal through the drain pad 190, so as to ensure the normal operation of the semiconductor device 10.

Further, along the first direction Y, the second gate connection portion 1402 is located between the active area aa and the drain pad 190, so that the area of the inactive area bb can be further reduced, and the area of the semiconductor device 10 can be further reduced, so that the device can be miniaturized.

Optionally, with continued reference to fig. 2, the epitaxial structure 120 includes a nucleation layer 1201, a buffer layer 1202, a channel layer 1203, and a barrier layer 1204, arranged in a stack; the channel layer 1203 and the barrier layer 1204 form a heterojunction structure.

Illustratively, with continued reference to fig. 2, the material of nucleation layer 1201 may be aluminum nitride, located between substrate 110 and buffer layer 1202, which serves to adhere the next layer of semiconductor material that needs to be grown.

Illustratively, with continued reference to fig. 2, the buffer layer 1202 is located on one side of the substrate 110, the material of the buffer layer 1202 may be gallium nitride, and iron atoms may be included in the buffer layer 1202, which is beneficial to achieving high resistance of the buffer layer 1202, ensuring that vertical leakage can be blocked, and improving pinch-off performance of the semiconductor device.

By way of example, with continued reference to FIG. 2, the channel layer 1203 may be a group III nitride, such as Al _xGa_1－x N, where 0.ltoreq.x <1, i.e., the energy at the interface between the channel layer 1203 and the barrier layer 1204, i.e., the conduction band edge of the channel layer 1203 is less than the conduction band edge of the barrier layer 1204. Illustratively, x=0 indicates that channel layer 1203 is GaN. The channel layer 1203 may also be other group III nitrides, for example InGaN, alInGaN. Channel layer 1203 may be undoped or unintentionally doped. The channel layer 1203 may also be a multilayer structure, for example, a combination of superlattice, gaN, or AlGaN.

Illustratively, with continued reference to fig. 2, the barrier layer 1204 may be AlN, alInN, alGaN or AlInGaN. The barrier layer 1204 has a sufficient thickness and has a high enough Al composition to cause doping to form a significant carrier concentration at the interface between the channel layer 1203 and the barrier layer 1204.

Illustratively, with continued reference to fig. 2, the channel layer 1203 may include GaN, while the barrier layer 1204 may include AlGaN, i.e., the material of the barrier layer 1204 has a higher bandgap than the material of the channel layer 1203, and the channel layer 1203 may also have a greater electron affinity than the barrier layer 1204. Due to the difference in band gap between the barrier layer 1204 and the channel layer 1203 and the piezoelectric effect at the interface between the barrier layer 1204 and the channel layer 1203, two-dimensional electron gas (Two-DimensionalElectron Gas,2 DEG) is formed at the channel layer 1203 and the barrier layer 1204.

It is appreciated that epitaxial structure 120 may also include a cap layer located on a surface of barrier layer 1204 that is remote from substrate 110. The cap layer may reduce surface states, reduce surface leakage of subsequent semiconductor devices, and inhibit current collapse, thereby improving performance and reliability of epitaxial structure 120 and semiconductor device 10.

It should be appreciated that the embodiments of the present invention are capable of reducing the influence of gate resistance and improving gain and reducing leakage by providing at least one gate connection structure from the viewpoint of semiconductor device design. The semiconductor device includes, but is not limited to: high power high electron mobility transistor (High Electron Mobility Transistor, HEMT), silicon-On-Insulator (SOI) structure transistor, gallium arsenide (GaAs) based transistor, and Metal-Oxide-semiconductor Field effect transistor (MOSFET), metal-Insulator-semiconductor Field effect transistor (Metal-Semiconductor Field-Effect Transistor, MISFET), double heterojunction Field effect transistor (Double Heterojunction Field-Effect Transistor, DHFET), junction Field effect transistor (Junction-Effect Transistor, JFET), metal-semiconductor Field effect transistor (Metal-Semiconductor Field-Effect Transistor, MESFET), metal-Insulator-semiconductor heterojunction Field effect transistor (Metal-Semiconductor HeterojunctionField-Effect Transistor, MESFET), or other Field effect transistor operating in a high voltage high current environment. The at least one grid connection structure arranged in the semiconductor device provided by the embodiment of the invention can be widely applied to the field of manufacturing of semiconductor devices such as radio frequency microwaves, power electronics and the like. The gallium nitride electronic device has more obvious advantages on the gallium nitride electronic device with large forbidden bandwidth, high electron mobility, high breakdown field intensity and good heat conduction performance, and can better meet the high-performance requirements of the fields of fast development of electronic communication and the like.

Note that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.

Claims (15)

1. A semiconductor device comprising an active region and a non-active region surrounding the active region;

the semiconductor device further includes:

a substrate;

an epitaxial structure located on one side of the substrate;

The grid electrode is positioned on one side of the epitaxial structure, far away from the substrate, and extends along a first direction, and the first direction is parallel to the plane of the substrate; the grid comprises a first grid subsection and a second grid subsection which are connected with each other, the first grid subsection and the epitaxial structure form schottky contact, and the second grid subsection is positioned in the passive region;

At least one gate connection structure comprising a first gate connection section and a second gate connection section connected to each other, the second gate connection section being located in the inactive region; the first gate electrode subsection and the first gate electrode connection subsection are not overlapped in the thickness direction of the semiconductor device, and at least part of the second gate electrode subsection is electrically connected with the second gate electrode connection subsection.

2. The semiconductor device according to claim 1, wherein the gate connection structure is electrically connected to the gate electrode on a side of the first gate connection section in a second direction through the second gate connection section;

Or the grid connection structure is electrically connected with the grid positioned at two sides of the first grid connection subsection along the second direction through the second grid connection subsection; the second direction intersects the first direction and is parallel to the plane of the substrate.

3. The semiconductor device of claim 1, wherein a size of the first gate connection section is greater than a size of the first gate section in the second direction; the second direction intersects the first direction and is parallel to the plane of the substrate.

4. The semiconductor device of claim 1, wherein a size of the second gate segment is greater than a size of the second gate connection segment along the first direction;

the second grid subsection comprises a first sub-part and a second sub-part, the first sub-part is positioned on one side of the second sub-part far away from the active area, and the size of the first sub-part is larger than that of the second sub-part along the second direction; the second grid connection subsection is electrically connected with the first sub-section; the second direction intersects the first direction and is parallel to the plane of the substrate.

5. The semiconductor device of claim 1, wherein a dimension of the second gate connection section in the first direction is smaller than a dimension of the first gate connection section in a second direction; the second direction intersects the first direction and is parallel to the plane of the substrate.

6. The semiconductor device of claim 1, wherein an angle α between the second gate connection section and the first gate connection section is 80 ° or less and 100 °.

7. The semiconductor device of claim 1, wherein the first gate connection section is co-layer with the second gate connection section.

8. The semiconductor device of claim 1, wherein the gate connection structure further comprises a third gate connection segment located in the active region and electrically connected to the first gate connection segment and the first gate segment, respectively.

9. The semiconductor device of claim 8, further comprising a source and a source field plate;

The source electrode field plate comprises a field plate main body and a field plate branch, and the field plate branch is respectively and electrically connected with the field plate main body and the source electrode;

the field plate branches and the third grid connection parts are staggered.

10. The semiconductor device of claim 1, further comprising a source electrode forming an ohmic contact with the epitaxial structure;

The first gate connection part is overlapped with the source electrode and is arranged in an insulating manner along the thickness direction of the semiconductor device.

11. The semiconductor device of claim 10, wherein a dimension of the first gate connection section in a second direction is smaller than a dimension of the source electrode in the second direction; the second direction intersects the first direction and is parallel to the plane of the substrate.

12. The semiconductor device of claim 10, further comprising a gate pad located in the inactive region on a first side of the active region along the first direction, the first gate segment and the first gate connection segment each being electrically connected to the gate pad;

The semiconductor device further comprises a source field plate, wherein the source field plate is electrically connected with the source;

The first gate connection part is arranged on the same layer as the source electrode field plate, or the first gate connection part is arranged on the same layer as the gate electrode bonding pad.

13. The semiconductor device of claim 1, further comprising a source electrode forming an ohmic contact with the epitaxial structure;

the first grid connection subsection is positioned at one side of the source electrode far away from the grid electrode along the second direction, the first grid connection subsection is positioned between two adjacent source electrodes, and two adjacent transistor cells share the same first grid connection subsection; the second direction intersects the first direction and is parallel to the plane of the substrate.

14. The semiconductor device according to claim 13, wherein a dimension L of the source electrode in the second direction satisfies l+.60 μm.

15. The semiconductor device of claim 13, further comprising a gate pad located in the inactive region on a first side of the active region along the first direction, the gate and the first gate connection section each being electrically connected to the gate pad;

The semiconductor device further comprises a source field plate, wherein the source field plate is electrically connected with the source;

The first grid connection subsection and the grid are arranged on the same layer; or the first grid connection subsection and the source electrode are arranged in the same layer; or the first grid connection subsection and the source electrode field plate are arranged on the same layer; or the first grid connection subsection and the grid bonding pad are arranged in the same layer.