JPH05308082A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To enable a mesa-shaped part to be an element region by etching a buffer layer, a channel layer, and a carrier supply layer in the mesa shape, at the same time prevent contact between a Schottky gate electrode and the channel region by contacting the Schottky gate only to the top surface of the mesa-shaped part. CONSTITUTION:A buffer layer 2, a channel layer 3, and a carrier supply layer 4 are laminated on a substrate 1 in sequence and then an ohmic source electrode and a drain electrode as well as a Schottky gate electrode 11 are formed on the carrier supply layer 4 in the title semiconductor device. In this device, the buffer layer 2, the channel layer 3, and the carrier supply layer 4 are etched in mesa shape so that they surround the source electrode, the drain electrode, and the Schottky gate electrode for forming the mesa-shaped part as an element region and at the same time the Schottky gate electrode 11 is extended for formation to the other part of the edge on the top surface from one part of the edge of the top surface so that it contacts only the top surface of the mesa- shaped part.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device such as HEMT (High Electron Mobility Transistor) and its manufacturing method.

[0002]

2. Description of the Related Art Conventionally, a HEMT (high electron mobility transistor) in which a GaInAs layer is used as a channel layer, an AlInAs layer is laminated as a carrier supply layer on the channel layer, and a gate electrode is formed on the carrier supply layer is known. Being developed. In such a HEMT, element isolation is performed by ion implantation so that the gate electrode does not contact GaInAs,
An air bridge is formed at the GaInAs layer.
This is because the Schottky contact with the GaInAs layer has a very low barrier height and a large leak current. That is, when the element is separated by etching the element region into a mesa shape, the gate electrode comes into contact with GaInAs on the inclined surface of the mesa shape portion and the FET characteristics are deteriorated. Ingenuity is needed.

[0003]

However, when the element isolation is performed by ion implantation, a region once having a high resistance due to the ion implantation may have a low resistance in the subsequent thermal process, resulting in poor element isolation. There was a problem that became. Further, if the lead-out portion of the gate electrode is an air bridge, not only the gate electrode forming process becomes complicated, but also the reliability of the device may be deteriorated depending on the strength of the air bridge.

Therefore, an object of the present invention is to solve the above-mentioned technical problems, to achieve good isolation between elements, to simplify the manufacturing process, to provide good element reliability, and to provide good element characteristics. A semiconductor device and a method for manufacturing the same are provided.

[0005]

According to another aspect of the present invention, there is provided a semiconductor device comprising: a buffer layer, a channel layer, and a carrier supply layer, which are sequentially stacked on a substrate; and the carrier supply layer. In a semiconductor device having an ohmic source electrode and drain electrode and a Schottky gate electrode formed thereon, the buffer layer, the channel layer and the carrier supply layer are etched in a mesa shape so as to surround the source electrode, the drain electrode and the Schottky gate electrode. The mesa-shaped portion is used as an element region, and the Schottky gate electrode is contacted only with the top surface of the mesa-shaped portion from a certain portion of the edge of the top surface to the top surface of the top surface. It is characterized in that it is formed so as to extend to other portions of the edge.

According to this structure, since the element regions are separated by etching the buffer layer, the channel layer and the carrier supply layer in a mesa shape, the element separation is not incomplete. On the other hand, the Schottky gate electrode is
It is formed so as to contact only the top surface of the mesa-shaped portion. Therefore, since the gate electrode does not come into contact with the inclined surface of the mesa-shaped portion, the device characteristics are not deteriorated due to the contact between the gate electrode and the channel layer. Moreover, since the Schottky gate electrode is formed on the top surface of the mesa-shaped portion so as to extend from a certain portion of the edge to another portion of the edge of the top surface, it is possible to improve the current between the source and the drain. Can be controlled.

Further, since the air bridge is not formed to prevent the contact between the inclined surface of the mesa-shaped portion and the Schottky gate electrode, the manufacturing process of the element is complicated and the reliability of the element is lowered. Not even. 3. The semiconductor device according to claim 2, wherein in the mesa-shaped portion, the buffer layer and the channel layer are provided in the vicinity of both ends of the Schottky gate electrode so as to interrupt a current path that flows around both ends of the Schottky gate electrode. And a removed region formed by removing the carrier supply layer by etching.

With such a structure, even if the Schottky gate electrode is patterned so as to stop slightly inside the edge of the top surface of the mesa-shaped portion, the function of the removal region causes
The current path between the source and drain that goes around the Schottky gate electrode can be blocked. Therefore, even if the Schottky gate electrode cannot be accurately aligned with the edge of the top surface of the mesa-shaped portion due to the limitation of the accuracy of mask alignment or the like, the device characteristics will not be deteriorated.

That is, if the Schottky gate electrode is formed to be long, the end of the Schottky gate electrode may come into contact with the channel layer at the inclined surface of the mesa-shaped portion. Therefore, it is preferable that the Schottky gate electrode is formed to be short in consideration of the accuracy of mask alignment. However, when the Schottky gate electrode is formed to be short, a region where current control by the Schottky gate electrode does not appear appears in the channel region near both ends of the Schottky gate electrode. By interrupting the current flowing in such a region by the above-mentioned removal region, it is possible to form the Schottky gate electrode with a short length while maintaining good device characteristics.

The semiconductor device according to claim 1 can be manufactured by the method according to claim 3. That is, in the method of manufacturing a semiconductor device according to claim 3, a step of sequentially stacking a buffer layer, a channel layer and a carrier supply layer on a substrate, and etching and removing the buffer layer, the channel layer and the carrier supply layer around the element region. A step of forming a mesa-shaped portion, and a step of patterning an ohmic electrode serving as a source / drain electrode on the top surface of the mesa-shaped portion,
A Schottky gate electrode that extends from a portion of the edge of the mesa-shaped portion to another portion of the edge of the top surface of the mesa-shaped portion so as to contact only the top surface of the mesa-shaped portion. And a pattern forming step are included.

The semiconductor device according to the second aspect can be manufactured by the manufacturing method according to the fourth aspect. That is, in the method for manufacturing a semiconductor device according to claim 4, after the step of forming the Schottky gate electrode, both end portions of the Schottky gate electrode are etched by etching the mesa-shaped portions near both end portions of the Schottky gate electrode. It is characterized by further including a step of forming a removal region that cuts off a current path that flows around.

The semiconductor device according to claim 2 can be further manufactured by the method according to claim 5. That is, in the method for manufacturing a semiconductor device according to claim 5, a step of sequentially stacking a buffer layer, a channel layer, and a carrier supply layer on a substrate, and an ohmic electrode to be a source / drain electrode on the carrier supply layer. A step of forming, a step of forming a Schottky gate electrode having a predetermined pattern on the carrier supply layer, a buffer layer around a region surrounding the Schottky gate electrode, the source electrode and the drain electrode, a channel layer and a carrier supply layer By etching away the separated element region into a mesa shape, and in the step of forming the element region into a mesa shape, in the vicinity of both ends of the Schottky gate electrode, the Schottky gate electrode A special feature is to simultaneously form the removal region that wraps around both ends and blocks the current path. To.

[0013]

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. FIG. 1 (a) is a cross-sectional view showing the structure of a HEMT (high electron mobility transistor) which is an embodiment of the semiconductor device of the present invention, and FIG. 1 (b) is a sectional line of FIG. 1 (a). It is sectional drawing seen from II. On the surface of the InP substrate 1, an InP buffer layer 2, a GaInAs channel layer 3, and an AlInAs carrier supply layer 4, which form a mesa-shaped portion 5 as a whole, are laminated.

The mesa-shaped portion 5 is covered with an insulating film 6 made of SiN or the like. Contact holes 7, 8 and 9 for forming source, gate and drain electrodes are formed in the insulating film 6. In the contact holes 7 and 9, ohmic electrodes 10A and 10B which make ohmic contact with the AlInAs carrier supply layer 4 are formed. further,
Contact hole 8 between the ohmic electrodes 10A and 10B
A Schottky gate electrode 11 is formed on the.

Lead wires 12A and 12B are formed so as to come into contact with the ohmic electrodes 10A and 10B. Further, as shown in FIG. 1B, a gate lead wiring 13 is connected to one end of the Schottky gate electrode 11.
FIG. 1 (c) is a plan view of the structure shown in FIGS. 1 (a) and 1 (b), and shows the structure excluding the lead wirings 12A, 12B, 13 and the insulating film 6. As can be seen from FIG. 1C, the Schottky gate electrode 11 has the mesa-shaped portion 5
Is formed only on the top surface 5a. In other words, the Schottky gate electrode 11 is not formed on the inclined surface 5b of the mesa-shaped portion 5, and the gate lead wiring 13 is formed on the inclined surface 5b with the insulating film 6 interposed. Only.

On the other hand, both ends 11a, 1 of the gate electrode 11 are
In the vicinity of 1b, the mesa-shaped portion 5 extends from the both ends 11a and 11b to the edge of the mesa-shaped portion 5.
Removal regions 14a, 14b, 14
c and 14d (collectively referred to as "removed region 14") are formed. The removal region 14 is formed to cut off the current flowing between the source and the drain by wrapping around the regions 15a and 15b where the gate electrode 11 is not formed.

That is, the gate electrode 11 is formed into the mesa-shaped portion 5
If it can be formed so as to be accurately aligned from one edge to the other edge of the top surface 5a, the above-mentioned current sneak does not occur. However, due to the accuracy of mask alignment, etc. In the vicinity of both ends 11a and 11b of the electrode 11, regions 15a and 15b where electrodes are not formed are inevitably formed between the ends of the top surface 5a of the mesa-shaped portion 5. In order to prevent such regions 15a and 15b from being formed, it is conceivable to form the gate electrode 11 long. However, when the gate electrode 11 is formed long, the gate electrode 11 reaches the inclined surface 5b of the mesa-shaped portion 5. 11
May be formed. In this case, the end of the gate electrode 11 may come into contact with the GaInAs channel layer 3 on the inclined surface 5b. As described above, since good Schottky contact cannot be obtained between the metal and GaInAs, the contact between the GaInAs channel layer 3 and the gate electrode 11 on the inclined surface 5b increases the gate leakage current and deteriorates the device characteristics. It will be.

As described above, the problem is that the gate electrode 11 is formed to be slightly shorter than the length of the top surface 5a of the mesa-shaped portion 5, and both end portions 11a of the gate electrode 11 are formed.
This is solved by forming the removal region 14 in the vicinity of 11b so as to wrap around the gate electrode 11 and block the current path flowing through the GaInAs channel layer 3. When etching the removal region 14, the gate electrode 11 functions as a mask. Therefore, the removal region 14 that is well aligned with the gate electrode 11 is formed.

FIG. 2 (a) is a diagram showing the gate Schottky characteristics of the HEMT of this embodiment, and shows the relationship between the voltage applied to the gate electrode 11 and the current flowing through this gate electrode 11. .. FIG. 2B shows a similar gate Schottky characteristic in the conventional HEMT in which elements are isolated by mesa etching. From the comparison between FIGS. 2A and 2B, it is understood that the HEMT of the present embodiment effectively reduces the gate leakage current and the Schottky characteristic is remarkably improved.

Further, FIG. 3 shows the drain current-voltage characteristics of the HEMT of this embodiment. In addition, each curve L
The correspondence between 1, L2, L3, L4, L5, L6 and the gate voltage V _G is as follows. _{L1 ···· V G = -1.0V L2 ····} V G = -0.8V L3 ···· V G = -0.6V L4 ···· V G = -0.4V L5 · from _{··· V G = -0.2V L6 ···· V} G = 0.0V FIG 3, the HEMT of this embodiment, that a good pinch-off characteristics can be obtained is understood. This is because the current path that goes around the gate electrode 11 is removed by the removal region 14 as described above.
Because it is blocked by.

4 and 5 show the HEMT having the above-mentioned structure.
FIG. 6 is a cross-sectional view showing the method of manufacturing in the order of steps. First, FIG.
As shown in (a), metalorganic vapor phase epitaxy (OMVPE
Method, etc., the InP buffer layer 2, the GaInAs channel layer 3, and the AlInAs carrier supply layer 4 are sequentially stacked and grown on the surface of the InP substrate 1. Next, FIG.
As shown in (b), the elements are separated by mesa etching. As a result, the mesa-shaped portion 5 separated for each element is formed on the InP substrate 1.

Subsequently, as shown in FIG. 4C, an insulating film 6 such as a SiN film is formed. Furthermore, as shown in FIG. 4 (d), ohmic electrodes 10A and 10B made of AuGe / Ni are used.
Are patterned in the contact holes 7 and 9 by the lift-off method, and alloying treatment is further performed at a temperature of 400 ° C. for 1 minute. Next, in the contact hole 8, Ti / P
The Schottky gate electrode 11 made of t / Au is patterned by the lift-off method. The length of the Schottky gate electrode 11 is set so as to be formed only on the top surface 5a of the mesa-shaped portion 5 in consideration of mask alignment accuracy and the like. The contact holes 7, 8 and 9 are opened immediately before the electrodes are formed.

Further, as shown in FIG. 5 (e), the vicinity of both ends 11a and 11b (see FIG. 1 (c)) of the gate electrode 11 is removed by etching to form a removed region 14.
Subsequent to this, as shown in FIGS. 5F and 5G, the lead-out wirings 12A and 12B and the gate lead-out wiring 13 are formed. In this way, the HEM shown in FIGS.
T is completed. However, FIG. 5 (g) is a sectional view taken along the line V-V in FIG. 5 (f).

FIG. 6 is a cross-sectional view showing a part of the steps of another method for manufacturing the HEMT described above. In this manufacturing method, as shown in FIG. 6A, the InP buffer layer 2 is formed on the InP substrate 1,
After the GaInAs channel layer 3 and the AlInAs carrier supply layer 4 are successively grown, the ohmic electrodes 10A and 10B and the Schottky gate electrode 11 are patterned respectively, as shown in FIG. 6 (b).

Next, as shown in FIG. 6 (c), mesa etching for element isolation is performed, and the removal region 14 is formed at the same time during the mesa etching. After this, as shown in FIG. 6D, the insulating film 6 is formed on the entire surface, and contact holes 17, 18, 19 are formed on the electrodes 10A, 10B, 11 respectively. Subsequent steps are similar to those of the first manufacturing method shown in FIGS. 4 and 5.

The present invention is not limited to the above embodiment. For example, in the above-described embodiment, each pair of removal regions 14a and 14 is sandwiched in the vicinity of both ends 11a and 11b of the gate electrode 11 so as to sandwich the gate electrode 11.
b; 14c and 14d are formed respectively, but in order to cut off the current flowing into the regions 15a and 15b where the gate electrode 11 is not formed, the removal regions 14a and 14b are formed.
One of the removal regions 14c and 14d may not be formed in the same manner.

Further, as shown in FIG. 7, by removing the regions 15a and 15b by etching to form the removed region 24, the current path that goes around both ends of the gate electrode 11 can be cut off. .. However, in this case, since it is necessary to form the removal region 24 that is accurately aligned with the end portions 11a and 11b of the gate electrode 11, FIG.
It becomes difficult to form the removal region 24 as compared with the above case. That is, if the edge of the gate electrode 11 and the removal region 24 are separated from each other, it is impossible to block the current flowing around the gate electrode 11, and if the etching for forming the removal region 24 is excessively performed, The crystal part under the gate electrode 11 may be undercut, which may lead to deterioration of device characteristics.

Further, in the above embodiment, the InP buffer layer 2, the GaInAs channel layer 3 and the Al are formed on the InP substrate 1.
Although the HEMT in which the InAs carrier supply layer 4 is formed has been described, the present invention can be widely applied to the HEMT using a material that may deteriorate device characteristics due to contact between the channel layer and the gate electrode. .. Specifically, GaAs is used for the substrate, GaAs is used for the buffer layer, GaInAs is used for the channel layer, and AlGa is used for the carrier supply layer.
The present invention is also applicable to HEMTs using As.

Furthermore, in the configuration shown in FIG.
Instead of the InP buffer layer 2, an AlInAs buffer layer may be used. A GaInAs contact layer may be provided on the surface of the AlInAs carrier supply layer 4. Other,
Various changes can be made without changing the gist of the present invention.

[0030]

As described above, according to the present invention, the element regions are separated by etching the buffer layer, the channel layer and the carrier supply layer in a mesa shape, so that the elements can be completely separated. On the other hand, the Schottky gate electrode is formed so as to contact only the top surface of the mesa-shaped portion, and the Schottky gate electrode does not contact the inclined surface of the mesa-shaped portion. Therefore, it is possible to prevent deterioration of device characteristics due to contact between the Schottky gate electrode and the channel layer.

Moreover, since the Schottky gate electrode is formed on the top surface of the mesa-shaped portion so as to extend from a certain portion of the edge to another portion of the edge of the top surface,
The current flowing between the drains can be well controlled. Further, since the air bridge is not formed to prevent the contact between the inclined surface of the mesa-shaped portion and the Schottky gate electrode, the manufacturing process of the element is not complicated and the reliability of the element is not deteriorated. ..

Further, in the above mesa-shaped portion, when a removal region for cutting off a current path flowing around the Schottky gate electrode is formed near both ends of the Schottky gate electrode, the Schottky gate electrode is provided on the top surface of the mesa-shaped portion. Even if a pattern is formed so as to stop slightly inside the edge of the Schottky gate electrode, the removal region can wrap around both ends of the Schottky gate electrode and interrupt the current flowing between the source and drain. Therefore, even if the Schottky gate electrode cannot be accurately aligned with the edge of the top surface of the mesa-shaped portion due to a limitation due to the accuracy of mask alignment, the device characteristics can be maintained well.

[Brief description of drawings]

FIG. 1 is a HEMT that is an embodiment of a semiconductor device of the present invention.
2A is a cross-sectional view, FIG. 1B is a cross-sectional view taken along the section line I-I of FIG. 2A, and FIG.

FIG. 2 is a diagram showing a comparison of the Schottky characteristics of the HEMT of the above-mentioned embodiment and the conventional HEMT, (a) corresponding to the above-mentioned embodiment, and (b) corresponding to the conventional HEMT.

FIG. 3 is a diagram showing drain current-voltage characteristics of the HEMT of the above-mentioned embodiment.

FIG. 4 is a cross-sectional view showing the method of manufacturing the HEMT of the above-described embodiment in the order of steps.

FIG. 5 is a cross-sectional view showing the method of manufacturing the HEMT of the above-described embodiment in the order of steps.

FIG. 6 is a cross-sectional view showing another method of manufacturing the HEMT of the above-described embodiment in the order of steps.

FIG. 7 is a plan view showing the configuration of a HEMT according to another embodiment of the present invention.

[Explanation of symbols]

 1 InP Substrate 2 InP Buffer Layer 3 GaInAs Channel Layer 4 AlInAs Carrier Supply Layer 5 Mesa Shaped Part 6 Insulating Film 10A, 10B Ohmic Electrode 11 Schottky Gate Electrode 12A, 12B Lead-out Wiring 13 Gate Lead-out Wiring 14 Removal Area 24 Removal Area 24

Claims (5)

[Claims] 1. A semiconductor device in which a buffer layer, a channel layer, and a carrier supply layer are sequentially stacked on a substrate, and an ohmic source electrode and drain electrode and a Schottky gate electrode are formed on the carrier supply layer. The buffer layer, the channel layer, and the carrier supply layer are etched in a mesa shape so as to surround the drain electrode and the Schottky gate electrode, and the mesa-shaped portion is used as an element region. From some point of the edge of this top surface so that it only contacts the top surface of the part,
A semiconductor device, which is formed so as to extend to another portion of the edge of the top surface. 2. The buffer layer, the channel layer, and the carrier supply layer in the mesa-shaped portion near the both ends of the Schottky gate electrode so as to interrupt a current path flowing around the both ends of the Schottky gate electrode. 2. The semiconductor device according to claim 1, wherein a removed region is formed by etching away. 3. A step of sequentially laminating a buffer layer, a channel layer and a carrier supply layer on a substrate, and a step of etching and removing the buffer layer, the channel layer and the carrier supply layer around the element region to form a mesa-shaped portion. And a step of forming an ohmic electrode serving as a source / drain electrode on the top surface of the mesa-shaped portion, and a step of contacting only the top surface of the mesa-shaped portion with the top surface of the mesa-shaped portion, And a step of patterning a Schottky gate electrode extending from a certain position on the edge of the top surface to another position on the edge of the top surface. 4. After the step of forming the Schottky gate electrode, a mesa-shaped portion near both ends of the Schottky gate electrode is removed by etching, so that a current path flowing around both ends of the Schottky gate electrode is formed. 4. The method of manufacturing a semiconductor device according to claim 3, further comprising the step of forming a removal region for blocking. 5. A step of sequentially laminating a buffer layer, a channel layer and a carrier supply layer on a substrate, a step of forming ohmic electrodes to be source / drain electrodes on the carrier supply layer, and the carrier supply layer. A Schottky gate electrode having a predetermined pattern is formed thereon, and the buffer layer, the channel layer and the carrier supply layer around the region surrounding the Schottky gate electrode, the source electrode and the drain electrode are removed by etching. A step of forming the element region in a mesa shape, and in the step of forming the element area in a mesa shape, a current path flowing around both ends of the Schottky gate electrode in the vicinity of both ends of the Schottky gate electrode. A method of manufacturing a semiconductor device, which comprises simultaneously forming a removal region for blocking the above.