JP2894801B2 - Semiconductor transistor and method of manufacturing the same - Google Patents

Description

The present invention relates to a semiconductor device, and more particularly, to an ultra-high-speed semiconductor device comprising an In-containing compound semiconductor operating layer such as InP and InGaAs.
The present invention relates to a field effect transistor for an ultrahigh frequency band or a heterojunction bipolar transistor.

[Conventional technology]

Compound semiconductor crystals containing In such as InP or InGaAs have attracted attention as ultrahigh frequency band device materials because of their high electron saturation speed and electron mobility.

Good characteristics have been obtained with Schottky barrier field-effect transistors (MESFETs) and modulation-doped field-effect transistors.

A conventional field effect transistor using InP as an operation layer will be described with reference to FIG.

An undoped AlInAs buffer layer 2, a Si-doped InGaAs active layer 4, and an undoped AlInAs insulating layer 5 are stacked on a semi-insulating InP substrate 1 to form a mesa portion for element isolation.

A gate electrode 6 is formed on the surface across the mesa portion, and a source electrode 7 and a drain electrode 8 are formed with the gate electrode 6 interposed therebetween.

[Problems to be solved by the invention]

In a conventional field effect transistor, the gate electrode is in direct contact with the high-concentration operating layer across the mesa.

There is a problem that the Schottky barrier is lowered in that portion, and a gate leak current is generated, thereby deteriorating element characteristics.

[Means for solving the problem]

A semiconductor transistor according to the present invention includes a mesa-type element region formed on a compound semiconductor substrate, a gate electrode formed on the substrate so as to cross a side wall and an upper surface of a mesa portion of the element region, and a mesa type element region. In a semiconductor transistor having a source electrode and a drain electrode formed on the upper surface of a portion with a gate electrode interposed therebetween, the element region is In.
Having at least an operation layer made of a compound semiconductor containing
At least the side wall of the mesa portion of the element region is covered with an amorphous III-V compound semiconductor layer, and the gate electrode crossing the side wall of the mesa portion of the element region is formed on the amorphous III-V compound semiconductor layer. It is characterized by being formed.

Further, the method for manufacturing a semiconductor transistor according to the present invention includes the steps of:
A mesa-type element region formed on a compound semiconductor substrate, a gate electrode formed on the substrate so as to cross the side walls and upper surface of the mesa portion of the element region, and a gate on the upper surface of the mesa portion of the element region. In a method for manufacturing a semiconductor transistor having a source electrode and a drain electrode formed with an electrode interposed therebetween, a stacked body including at least an active layer made of a compound semiconductor containing In is formed on one main surface of a compound semiconductor substrate containing In. Performing a step of forming a mask material on the laminate, performing etching after forming a mask material, and forming a mesa portion to be an element region, and removing the mask material after depositing an amorphous group III-V compound semiconductor. Removing the amorphous group III-V compound semiconductor layer on the mask material to form an amorphous group III-V compound on the side wall of the mesa portion and its periphery. Covering with a semiconductor layer, and forming the amorphous III-V on the side wall of the mesa portion on the substrate.
Forming a gate electrode crossing over the group III compound semiconductor layer and the upper surface of the mesa portion; and forming the source electrode and the drain electrode on the upper surface of the mesa portion.

[Action]

It is well known that a compound semiconductor containing In such as InP or InGaAs has a lower metal / semiconductor barrier than GaAs and has poor insulation properties.

Since the high-concentration semiconductor operation layer is exposed on the mesa side wall, a leak current occurs at a portion in contact with the gate electrode metal.

By covering the mesa side wall with amorphous GaAs or amorphous AlInAs in order to avoid this leakage current, the vicinity of the interface of the operation layer is depleted, and a semiconductor junction with high withstand voltage can be obtained.

Further, since the insulating film and the operating layer are the same III-V semiconductor layer, the constituent elements of the operating layer are prevented from diffusing into the insulating film, and the difference in thermal expansion coefficient is small, thereby improving the reliability of element characteristics. Has also contributed.

Amorphous II over the entire surface using SiO ₂ as a mask material
The method of depositing the IV group compound semiconductor layer and then removing the unnecessary amorphous group III-V compound semiconductor layer together with the mask material not only facilitates the manufacturing process, but also
Since dry etching such as RIE is not performed, surface damage due to plasma can be avoided. Furthermore, since the process is a low-temperature process, fluctuations in device characteristics are small.

〔Example〕

Regarding one embodiment of the field effect transistor of the present invention,
This will be described with reference to FIG.

1 μm thick undoped AlI on semi-insulating InP substrate 1
An nAs buffer layer 2, a Si-doped InGaAs active layer 4 having a thickness of 20 nm, and an undoped AlInAs insulating layer 5 having a thickness of 20 nm are sequentially epitaxially grown to form a mesa portion serving as an element region.

The side wall and the periphery of the mesa portion are covered with an amorphous AlInAs insulating layer or an amorphous GaAs insulating layer 3, and a gate electrode 6 made of Ti / Pt / Au and a source electrode 7 made of AuGe / Ni and a drain electrode 8 are formed. I have.

Although amorphous AlInAs or amorphous GaAs is used here as the insulating layer, it can be replaced with another amorphous group III-V compound semiconductor such as amorphous AlGaAs which has large insulation resistance and good interface characteristics with the operation layer.

FIG. 4A shows the source-gate current-voltage characteristics of the field-effect transistor of this embodiment, and FIG. 4B shows the source-gate current-voltage characteristics of the conventional field-effect transistor.

In this embodiment, the side wall of the mesa portion in contact with the gate electrode metal has an amorphous AlInAs insulating layer or an amorphous AlInAs insulating layer.
It can be seen that the gate leakage current is reduced and the withstand voltage is improved because it is covered with the GaAs insulating layer.

Next, an embodiment of a method for manufacturing a field effect transistor according to the present invention will be described with reference to FIGS. 2 (a) to 2 (d).

First, as shown in FIG. 2A, an undoped AlInAs buffer layer 2 having a thickness of 1 μm, a Si-doped InGaAs working layer 4 having a thickness of 20 nm, and an undoped AlInAs insulating layer having a thickness of 20 nm are formed on a semi-insulating InP substrate 1. After epitaxially growing 5, a mask material 9 made of SiO ₂ or Si ₃ N ₄ is formed on the entire surface, and the mask material 9 is selectively etched by photolithography.

Next, as shown in FIG. 2 (b), undoped AlInAs
By performing wet etching until the buffer layer 2 is exposed, a mesa portion serving as an element region is formed.

Next, as shown in FIG. 2C, an amorphous AlInAs insulating layer or an amorphous GaAs insulating layer 3 is deposited by, for example, MOCVD or MBE.

Next, as shown in FIG. 2 (d), undoped AlInAs
The unnecessary amorphous GaAs insulating layer 3 on the insulating layer 5 is removed together with the mask material 9 by etching.

Next, a gate electrode 6 made of Ti-Pt-Au is formed.
Ge-Ni source-drain electrodes 7, 8 (not shown)
Is formed to complete the element portion.

Conventionally, to form an insulating film on the side wall and periphery of the mesa,
A method of performing selective etching by RIE after depositing on the entire surface and a method of performing selective epitaxial growth at a high temperature have been used.

According to the present invention, a simple process with much less surface damage compared to the conventional manufacturing method is realized.

〔The invention's effect〕

According to the present invention, it has been possible to solve the problem that the gate leakage current increases in the portion where the gate electrode metal covers the side wall of the mesa portion and the gate breakdown voltage is deteriorated.

InP or I with low leakage current and sufficient withstand voltage
An nGaAs field effect transistor has been realized.

Further, the field effect transistor can be manufactured by a simple manufacturing process with less surface damage by a low temperature process.

[Brief description of the drawings]

FIG. 1 is a perspective view showing one embodiment of a field-effect transistor of the present invention, and FIGS. 2A to 2D are cross-sectional views showing one embodiment of a method of manufacturing a semiconductor device of the present invention in the order of steps. 3 is a perspective view showing a conventional field effect transistor, FIG. 4 (a) is a graph showing the source-gate current-voltage characteristics of the field effect transistor of this embodiment, and FIG. 4 (b) is a prior art. 5 is a graph showing current-voltage characteristics between a source and a gate of a field-effect transistor. 1 ... Semi-insulating InP substrate, 2 ... Undoped AlInAs buffer layer, 3 ... Amorphous GaAs insulating layer, 4 ... Si doped InGaAs channel layer, 5 ... Undoped AlInAs insulating layer,
6 ... Ti / Pt / Au gate electrode, 7 ... AuGe / Ni source electrode, 8 ... AuGe / Ni drain electrode, 9 ... Mask material.

Claims (4)

(57) [Claims] A mesa-type element region formed on a compound semiconductor substrate; a gate electrode formed on the substrate so as to cross a sidewall and an upper surface of a mesa portion of the element region; In a semiconductor transistor having a source electrode and a drain electrode formed with a gate electrode interposed therebetween on an upper surface, the element region has at least an operation layer made of a compound semiconductor containing In, and at least a side wall of a mesa portion of the element region is A semiconductor covered with an amorphous III-V compound semiconductor layer, wherein a gate electrode crossing a side wall of a mesa portion of the element region is formed on the amorphous III-V compound semiconductor layer; Transistor. 2. The amorphous III-V compound semiconductor layer covers a surface of the compound semiconductor substrate around a mesa portion in addition to a side wall of the mesa portion, and the gate electrode surrounds the periphery of the mesa portion. 2. The semiconductor transistor according to claim 1, wherein the semiconductor transistor is extended to a position above the substrate, and the extended portion is formed on the amorphous group III-V compound semiconductor layer covering the periphery of the mesa. 3. The semiconductor transistor according to claim 1, wherein said substrate is a compound semiconductor substrate containing In. 4. A mesa-type element region formed on a compound semiconductor substrate containing In; a gate electrode formed on the substrate so as to cross a sidewall and an upper surface of a mesa portion of the element region;
A method of manufacturing a semiconductor transistor having a source electrode and a drain electrode formed with a gate electrode interposed therebetween on an upper surface of a mesa portion of an element region, comprising a compound semiconductor containing In on one main surface of a compound semiconductor substrate containing In. A step of forming a laminate including at least an operation layer; a step of forming a mask material on the laminate and performing etching to form a mesa portion serving as an element region; and depositing an amorphous group III-V compound semiconductor. After removing the mask material, the amorphous III-V compound semiconductor layer on the mask material is removed, and the side walls of the mesa portion and the periphery thereof are formed of amorphous III-V.
Covering with a group III compound semiconductor layer;
-Forming a gate electrode on the group V compound semiconductor layer and crossing over the top surface of the mesa portion; and forming the source electrode and the drain electrode on the top surface of the mesa portion. Production method.