JPH06302625A - Field effect transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To enhance threshold uniformity by installing In0.49Ga0.51P layer directly under a GaAs cap layer and inserting an AlGaAs layer between both layers in construction as well. CONSTITUTION:A non-dope GaAs buffer layer 2, a non-dope Al0.27Ga0.73As spacer layer 3, an n-Al0.27Ga0.73As carrier supply layer 4, an n-In0.49Ga0.51P etching stopper layer 5, an n-Al0.15Ga0.85As layer 6 and a GaAs cap layer 7 are formed one after another on a semi-insulation GaAs substrate 1 based on a molecular beam epitaxy. After setting a device active area based on a device-to- device isolation process and forming a silicon dioxide insulation film 8 based on a CVD process, there are formed a Ga/Au-made source electrode 9 and a drain electrode 10. Then, after the GaAs cap layer 7 is exposed, a Ti/Pt/ Au-made electrode 11 is formed on the n-In0.49Ga0.51P layer 5 obtained by etching based on deposition and lift-off, thereby preparing a field-effect transistor.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor such as a high electron mobility transistor and a method for manufacturing the same.

[0002]

2. Description of the Related Art Today, due to progress in manufacturing technology for semi-insulating substrates, ion implantation technology, and crystal growth technology, MESF
Electronic devices such as ET, HEMT, and HBT have come to be realized. For example, n on an undoped GaAs layer
HEMTs, which control the concentration of high mobility two-dimensional electron gas generated at the heterojunction interface when a p-type AlGaAs layer is formed, are promising as a high-speed switching element and a microwave element. In order to improve the structure, research is actively conducted from the viewpoint of structure and material.

First, in terms of structure, GaAs and Al _x Ga are used.
N-AlGaAs / InGaAs / GaAs having a heterostructure in which In _y Ga _1-y As is inserted between _1-x As and
There is a system Pseudo morphic HEMT. In the conventional HEMT, a large amount of DX centers are present because x = 0.3 is used, which adversely affects the device characteristics. However, in this HEMT, x = 0.15 and y = 0.15 are used. DX center is less affected and Al
Since there is a sufficiently large conduction band offset between GaAs and InGaAs, carriers necessary for device operation are secured. Also, InG that becomes a channel
aAs has a lattice mismatch with GaAs, but since its thickness is set to the critical film thickness or less, it is strained without dislocations.
It becomes a layer (strained layer), and the electron transport characteristics are improved as compared with the conventional HEMT having a channel of GaAs.

Next, in terms of materials, an InP substrate was used instead of the GaAs substrate, and InGa lattice-matched to InP was used.
There is an n-InAlAs / InGaAs HEMT having a heterostructure composed of As and n-type InAlAs. Since this system exhibits higher electron mobility, electron saturation velocity and two-dimensional electron gas concentration, respectively, than the conventional HEMT, it is attracting attention because it can realize a higher performance HEMT.

By the way, the ratio of the drain current change to the gate voltage change when the drain voltage is kept constant is called the transconductance (g _m ), which is used as one parameter representing the performance of the FET. At this time, the gate
Effective g when parasitic resistance R _S exists between sources
_msat is given by g _m0 / (1 + g _m0 R _S ). Where g _mo is the intrinsic transconductance. Therefore, in order to obtain a large effective g _msat and to improve the high frequency characteristics, the smaller the parasitic resistance R _{S, the} better.

Further, the control of the threshold voltage, which is another important parameter representing the performance of the FET, is determined by the removal film thickness of the n-GaAs layer immediately below the gate in manufacturing the device. FIG. 5 shows the structure of a conventional HEMT. 1 is a semi-insulating GaAs substrate, 2 is a 500 nm-thick undoped Ga substrate
As buffer layer, 3 is undoped Al having a thickness of 2 nm _{0. 27}
Ga _0.73 As spacer layer, 4 is n-A with a thickness of 40 nm
l _0.27 Ga _{0. 73} As the carrier supply layer 12 has a thickness of 10
nm GaAs undoped layer, 7 is 100 nm thick G
It is an aAs cap layer. Further, 9 and 10 are source and drain electrodes which are ohmic electrodes, 11 is a gate electrode, and 8 is an insulating film.

According to this structure, from the carrier supply layer 4 to the undoped GaAs buffer layer 2 and the undoped Al _0.27 Ga
As a result of supplying carriers to the channel layer formed at the heterojunction interface with the _0.73 As spacer layer 3, a high mobility two-dimensional electron gas is formed in the channel layer.

[0008]

However, in the structure as described above, Ga is used to form the gate electrode 11.
Although it is necessary to remove the As cap layer 7 by etching to expose the GaAs non-doped layer 12, there are in-plane variations in the etching rate and in-plane variations in the film thickness.
The undoped layer 12 cannot be uniformly exposed within the wafer surface. As a result, for example, it becomes impossible to fabricate an FET having a low logic amplitude voltage that requires uniformity of threshold voltage, and there is a problem in mass production.

An object of the present invention is to provide a field effect transistor capable of improving the uniformity of threshold and a method for manufacturing the same.

[0010]

The present invention is a GaAs key.
In under the cap layer_0.49Ga_0.51A P layer is provided. See you
In order to reduce the source resistance, AlG is placed between both layers.
The structure has an aAs layer inserted. Where the shape of the gate electrode
In the inventions of claim 2 and claim 4,_0.49Ga
_0.51It is formed on the P layer, and in the inventions of claims 3 and 5,
Is In_0.49Ga_0.51Undoped GaA formed under P layer
formed on s.

[0011]

[Action] _{GaAs / Al x Ga 1-x} As material and an In _0.49 Ga _0.51 P material this lattice matched can be selectively etched with high selectivity relative to each other. For example,
GaAs / Al _x Ga for In _0.49 Ga _0.51 P material
_When etching _1-x As based material, a selection ratio of 60 or more can be obtained by using a phosphoric acid / hydrogen peroxide based etching solution. On the contrary, when the In _0.49 Ga _0.51 P material is etched, the GaAs / Al _x Ga _1-x As based material is hardly etched when an etching solution containing a mixed solution of hydrochloric acid and phosphoric acid is used. Therefore, both materials act as etching stopper layers.

Next, n-type GaAs and Al _x Ga _1-x
Consider the case where As and In _0.49 Ga _0.51 P are joined. FIG. 3 shows a band diagram in the case where n-GaAs and n-In _0.49 Ga _0.51 P are directly bonded, and FIG. 4 shows n-A.
shows a band diagram in the case of bonding via a l _x Ga _1-x As. As can be seen from the figure, in the case of FIG. 3, the electron injected from the electrode is about 30 mV generated at the interface.
It will be injected into the operating layer mainly by diffusion over the barrier.

On the other hand, in the case of FIG. 4, electrons are injected into the operating layer by the electric field generated by the difference in diffusion and electron affinity. Therefore, the latter structure can improve the electron injection efficiency and reduce the resistance. In the case of the present invention, since this junction corresponds to the source region of the FET, the source resistance is ultimately reduced. As the value of x increases, the electric field increases, but the resistance of Al _x Ga _{1 -x} As increases, so 0.15 to 0.2 is appropriate.

When the Schottky electrode is formed on n-In _0.49 Ga _0.51 P which forms a high barrier height, the breakdown voltage is improved and it can be applied to a power FET. However, in this case, P loss occurs when the n-In _0.49 Ga _0.51 P layer is exposed, resulting in conductive In ₂ O ₃ and Ga ₂ O.
It is expected that ₃ will be formed and the Schottky characteristics will be slightly leaky. Therefore, when applied to a small signal FET, it is preferable to provide undoped GaAs under the n-In _0.49 Ga _0.51 P layer and form a Schottky electrode thereon.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure of a field effect transistor according to an embodiment of the present invention and its manufacturing method will be described below with reference to the drawings. FIG. 1 shows the structure of a field effect transistor and its manufacturing process in a first embodiment of the present invention. In FIG. 1, 1 is a semi-insulating GaAs substrate, 2 is an undoped GaAs buffer layer, 3 is undoped Al _0.27 G
a _0.73 As spacer layer, 4 is n-Al _0.27 Ga _0.73 As
The carrier supply layer, 5 is an n-In _0.49 Ga _0.51 P etching stopper layer, 6 is an n-Al _0.15 Ga _0.85 As layer, and 7 is a GaAs cap layer. 8 is an insulating film,
9, 10, 11 are the source electrode, the drain electrode,
It is a gate electrode.

In order to manufacture this field effect transistor, as shown in FIG. 1 (a), a semi-insulating GaAs substrate 1 is used.
First, using the molecular beam epitaxy method, a film thickness of 500 is obtained.
nm undoped GaAs buffer layer 2, thickness 20 nm
Undoped Al _0.27 Ga _0.73 As spacer layer 3, an n-Al _0.27 Ga _0.73 As carrier supply layer 4 having a film thickness of 40 nm and doped with n-type impurities of about 2 × 10 ¹⁸ cm ⁻³ , an n-film having a film thickness of 2 nm. In _0.49 Ga _0.51 P etching stopper layer 5, n-Al _0.15 Ga _0.85 As layer 6 having a film thickness of 10 nm,
The GaAs cap layer 7 having a film thickness of 100 nm is sequentially formed.

After that, a device active region is set by mesa etching for element isolation. Then, using a CVD method, a silicon oxide (SiO ₂ ) film having a thickness of about 60 nm is formed.
The insulating film 8 made of is formed, and G is formed by photolithography technology and removal of the insulating film, vapor deposition and lift-off, and alloying.
Source electrode 9 and drain electrode 10 made of e / Au
To form the structure shown in FIG.

Next, the photolithography technique and the removal of the insulating film are performed using a mask corresponding to the gate region,
The GaAs cap layer 7 is exposed. Then, the GaAs cap layer 7 and the GaAs cap layer 7 are selectively etched and removed by using a phosphoric acid / hydrogen peroxide aqueous etching solution, and n-In _0.49
The Ga _0.51 P layer 5 is exposed to form the structure of FIG.

Finally, as shown in FIG. 1D, a gate electrode 11 made of Ti / Pt / Au is formed on the n-In _0.49 Ga _0.51 P layer 5 by vapor deposition and lift-off to produce a field effect transistor. To do. FIG. 2 shows the structure of the field effect transistor and the manufacturing process thereof in the second embodiment of the present invention. In FIG. 2, 1 is a semi-insulating Ga
As substrate, 2 undoped GaAs buffer layer, 3 undoped Al _0.27 Ga _0.73 As spacer layer, 4 n-Al
_0.27 Ga _0.73 As carrier supply layer, 12 GaAs undoped layer, 5 n-In _0.49 Ga _0.51 P etching stopper layer, 6 n-Al _0.15 Ga _0.85 As layer, 7 GaAs
It is a cap layer. Further, 8 is an insulating film, and 9 and 1
Reference numerals 0 and 11 denote a source electrode, a drain electrode and a gate electrode, respectively.

In order to fabricate this electric field transistor, a Ga film having a film thickness of 10 nm in the first embodiment was formed.
Only the As non-doped layer 12 is inserted, and the process is the same as in FIG. 1C. After that, n-In _0.49
After exposing the Ga _0.51 P layer 5, the n-In _0.49 Ga _0.51 P layer 5 is removed by etching using a hydrochloric acid / phosphoric acid-based etching solution to expose the GaAs non-doped layer 12 to expose the GaAs non-doped layer 12 shown in FIG. ) Form the structure.

Finally, as shown in FIG. 2B, a gate electrode 11 made of Ti / Pt / Au is formed on the GaAs non-doped layer 12 by vapor deposition and lift-off to manufacture a transistor. Although the HEMT is used as the transistor in the above embodiment, any field effect transistor can be used. In addition, the n-Al _0.15 Ga _0.85 As layer 6
The AlAs composition ratio was set to 0.15, but is not limited to this.

[0022]

According to the field effect transistor of the present invention, the In _0.49 Ga _0.51 P layer and the Al _x Ga layer are formed immediately below the cap layer.
_{A structure in which a 1-x} As layer is sequentially provided and a gate electrode is provided on the In _0.49 Ga _0.51 P layer, or a GaAs layer, an In _0.49 Ga _0.51 P layer, and an Al _x Ga layer are formed immediately below the cap layer.
By sequentially providing the _1-x As layer and having the gate electrode on the GaAs layer, the uniformity of the threshold value can be improved, and the source resistance is not increased.

[Brief description of drawings]

1A to 1D are cross-sectional views in order of manufacturing steps of a field effect transistor according to a first embodiment of the present invention.

2A and 2B are cross-sectional views in order of the manufacturing steps of the field effect transistor according to the second embodiment of the present invention.

FIG. 3 is a band diagram of n-GaAs / n-In _0.49 Ga _0.51 P.

FIG. 4 n-Al _x Ga _1-x As / n-In _0.49 Ga
It is a band diagram of _0.51P .

FIG. 5 is a cross-sectional view of a field effect transistor in a conventional example.

[Explanation of symbols]

1 semi-insulating GaAs substrate 2 undoped GaAs buffer layer 3 undoped Al _0.27 Ga _0.73 As spacer layer 4 n-Al _0.27 Ga _0.73 As carrier supply layer 5 n-In _0.49 Ga _0.51 P etching stopper layer 6 n-Al _0.15 Ga _0.85 As layer 7 GaAs cap layer 8 Insulating film made of SiO ₂ 9 Source electrode 10 Drain electrode 11 Gate electrode 12 GaAs undoped layer

Claims (5)

[Claims] 1. A field-effect transistor having at least an operating layer and a cap layer on a GaAs substrate, wherein an n-type In _0.49 Ga _0.51 P layer and an n-type Al _x Ga _1-x As are provided immediately below the cap layer. A field effect transistor characterized in that layers are sequentially provided. 2. The gate electrode is an n-type In _0.49 Ga _0.51 P
The field effect transistor according to claim 1, which is formed on a layer. 3. An undoped GaAs layer is formed immediately below an n-type In _0.49 Ga _0.51 P layer, and the undoped GaAs layer is formed.
The field effect transistor according to claim 1, wherein a gate electrode is formed on the layer. 4. A GaAs substrate, at least an operating layer, an n-type In _0.49 Ga _0.51 P layer, and an n-type Al _x Ga layer on a GaAs substrate.
_The step of sequentially forming a _1-x As layer and a cap layer made of high-concentration n-type GaAs, and using the mask made of an insulating film for forming a gate, the high-concentration n-type layer is formed by wet etching. GaAs
The n-type Al _x Ga _{1 -x} As layer and the n-type In
A step of selectively removing the _0.49 Ga _0.51 P layer and the n-type In _0.49 Ga exposed by the etching.
Forming a gate electrode on the _0.51 P layer. 5. A GaAs substrate, at least an operating layer, an undoped GaAs layer, and an n-type In _0.49 Ga _0.51.
A step of sequentially forming a P layer, an n-type Al _x Ga _1-x As layer, and a cap layer made of a high-concentration n-type GaAs layer, and using a mask made of an insulating film for forming a gate Then, by the first wet etching, the high-concentration n-type G
a step of selectively removing the aAs layer and the n-type Al _x Ga _1-x As layer with respect to the n-type In _0.49 Ga _0.51 P layer; and the n-type In _0.49 Ga by a second wet etching.
A field effect transistor comprising: selectively removing a _0.51 P layer with respect to the undoped GaAs layer; and forming a gate electrode on the undoped GaAs exposed by the second wet etching. Production method.