JP3077653B2 - Field effect transistor and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a field effect transistor and a method of manufacturing the same, and more particularly, to a vertical field effect transistor in which a drain current flows along a thickness direction of a channel layer and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, a field effect transistor (hereinafter referred to as F
A vertical FET in which a drain current flows along the thickness direction of a channel layer and a lateral FET in which a drain current flows perpendicularly to the thickness direction of the channel layer are known.

FIG. 5 shows, for example, JP-A-56-50142.
7 is a cross-sectional view showing a vertical FET of Conventional Example 1 disclosed in Japanese Patent Application Laid-Open No. 7-1995, and the vertical FET is an n-type GaAs substrate 1.
An n-type GaAs drain layer 2 and an n-type AlGaAs channel layer 3 are sequentially stacked on the n-type GaAs drain layer 2, and a mesa-stripe n-type GaAs source layer 4 is formed on the n-type AlGaAs channel layer 3.
Are formed. A source electrode 5 is formed on the n-type GaAs source layer 4, and gate electrodes 6 and 6 are formed on the n-type AlGaAs channel layer 3 on both sides of the n-type GaAs source layer 4. . On the other hand, n-type GaAs
On the lower surface of the substrate 1, a drain electrode 7 is formed.

In this vertical FET, when a voltage is applied to the gate electrodes 6 and 6, a depletion region extends laterally in the n-type AlGaAs channel layer 3 under the n-type GaAs source layer 4 having a mesa stripe shape. And the channel resistance changes. In this vertical FET, when the n-type GaAs source layer 4 is processed into a mesa stripe shape, the n-type AlGaAs channel layer 3 plays a role of an etching stopper layer, and an effective gate electrode is formed.
The characteristic is that the gate length can be determined by the thickness of the n-type AlGaAs channel layer 3.

FIG. 6 is a cross-sectional view showing a vertical FET of Conventional Example 2 proposed by, for example, Misha et al. This vertical FET is described in Mishra et.
al., Electronics Letters, Vol. 20, pp. 145-146, 1984
In more detail. This vertical FET has an n-type Ga
An n-type GaAs drain layer 2 and an n-type Ga
As channel layer 11, n-type AlGaAs source layer 12,
An n-type GaAs contact layer 13 is sequentially formed,
A mesa stripe is formed from the surface of the aAs contact layer 13 to the inside of the n-type GaAs channel layer 11.

Gate electrodes 6 and 6 are formed on both sides of the mesa stripe and on both sides of the n-type GaAs channel layer 11 exposed by the mesa stripe.
The source electrode 5 is formed on the aAs contact layer 13. On the other hand, a drain electrode 7 is formed on the lower surface of the n-type GaAs substrate 1. In this vertical FET, the gate length is determined by the thickness of the gate electrodes 6 deposited on both side surfaces of the mesa stripe.

[0007]

By the way, the first problem of the vertical type FET of the prior art 1 is that the gate electrode 6, 6 and the side wall of the n-type GaAs source layer 4 in the mesa stripe form. Since the gap exists, the depletion layer needs to be expanded more than in the case where there is no gap. In addition to the point that the pinch-off voltage becomes unnecessarily large, the FE having a large transconductance is provided.
It is difficult to manufacture T.

The second problem is that the lateral dimensions of the gate electrodes 6, 6 determine the effective gate length of the n-type AlGaAs.
It is larger than the thickness of the channel layer 3 and the gate electrodes 6, 6
Most of the depletion layers extending vertically downward contribute to the parasitic capacitance of the gate, so that the gate capacitance is relatively large and disadvantageous for high-frequency operation. The third problem is that a high electric field region formed by application of a high drain voltage spreads inside the n-type GaAs drain layer 2 having a relatively low bandgap. This is a disadvantage for power applications.

The first problem of the vertical FET of the prior art example 2 is that the thickness of the metal gate electrodes 6, 6 obtained by depositing a metal on the side walls of the mesa stripe by vapor deposition defines the gate length. The gate length is susceptible to process variations, the control of the effective gate length is difficult, and the uniformity and reproducibility in the manufacture of FETs are poor.

The second problem is that the lateral dimensions of the gate electrodes 6, 6 which determine the effective gate length are larger than the thicknesses of the gate electrodes 6, and most of the depletion layers extending vertically downward to the gate electrodes 6 In order to contribute as a parasitic capacitance, the gate capacitance is relatively large, which is disadvantageous for high-frequency operation.
A third problem is that a high electric field region formed by application of a high drain voltage causes an n-type G region having a relatively low bandgap.
This is disadvantageous for high power applications used under a high drain voltage because it extends inside the aAs drain layer 2.

The present invention has been made in view of the above circumstances, and an electric field effect capable of amplifying a large power by applying a high drain voltage, having excellent high frequency characteristics, and improving productivity. It is an object to provide a transistor and a method for manufacturing the transistor.

[0012]

In order to solve the above-mentioned problems, the present invention provides the following field-effect transistor and a method of manufacturing the same. That is, the field-effect transistor of the present invention, on a semiconductor substrate, a channel layer made of a first semiconductor, the channel on one main surface of the channel layer
A source layer formed of a second semiconductor having a wider bandgap than the first semiconductor formed with a width wider than the width of the layer; and a source layer formed on the other main surface of the channel layer and wider than the first semiconductor. A drain layer made of a third semiconductor having a forbidden band width, a gate electrode formed to be in contact with a side surface of the channel layer and a surface of the drain layer, a source electrode formed on the source layer, And a drain electrode formed on the drain layer.

[0013] The third semiconductor is composed of III containing Al.
And -V compound semiconductor, at least of the drain layer
High resistance containing Al on the surface in contact with the gate electrode
A layer may be formed.

According to the method of manufacturing a field effect transistor of the present invention, a channel layer made of a first semiconductor is formed on a semiconductor substrate, and a band gap formed on one main surface of the channel layer and wider than the first semiconductor is formed. And a drain layer formed on the other main surface of the channel layer and formed of a third semiconductor having a wider bandgap than the first semiconductor. , A step of selectively removing the channel layer and the source layer, and a step of further selectively removing the channel layer.

After the step of selectively removing the channel layer and the source layer, a step of ion-implanting and damaging the exposed surface of the drain layer to make the surface a high-resistance layer may be provided.

In the field effect transistor of the present invention, the first
The first main surface of the channel layer made of the semiconductor
By forming the source layer made of the second semiconductor having a wider bandgap than the semiconductor of the above, the conduction band energy becomes discontinuous at the interface between the source layer and the channel layer,
When electrons are injected from this source layer into the channel layer,
The injected electrons travel as hot electrons in the channel layer, and the time required to cross the channel layer (channel travel time) is reduced. This makes it possible to improve the current gain cutoff frequency.

Further, by forming a drain layer made of a third semiconductor having a wider bandgap than the first semiconductor on the other main surface of the channel layer, the withstand voltage characteristics can be improved. Become. In addition, since the gate electrode is formed so as to be in contact with the side surface of the channel layer and the surface of the drain layer, the gate length of the gate electrode becomes a short gate length determined by the thickness of the channel layer, and the parasitic capacitance of the gate electrode is reduced. The DC characteristics and the high-frequency characteristics are improved. Further, by employing a hetero-drain structure, impact ionization hardly occurs inside the drain layer having a large band gap. This enables operation under a high drain voltage, and can be used for high power.

According to the method of manufacturing a field effect transistor of the present invention, a step of selectively removing the channel layer and the source layer and a step of further selectively removing the channel layer are provided. A gate electrode having a short gate length determined by the thickness of the channel layer at the time of crystal growth can be formed without depending on the precision of lithography. As a result, a vertical field-effect transistor having excellent DC characteristics and high-frequency characteristics can be manufactured with good reproducibility, and productivity can be increased.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a field effect transistor of the present invention and a method of manufacturing the same will be described with reference to the drawings.

[First Embodiment] FIG. 1 is a sectional view showing a field effect transistor (FET) according to a first embodiment of the present invention. In FIG. 1, reference numeral 21 denotes a semi-insulating GaAs substrate (semiconductor substrate); 22 is an n-type GaAs contact layer (drain / contact layer), 23 is a drain layer made of an n-type semiconductor (third semiconductor) having a wider bandgap than GaAs, and 24 is an n-type GaAs (first semiconductor) channel layer ,
Reference numeral 25 denotes a source layer made of an n-type semiconductor (second semiconductor) having a wider bandgap than GaAs; 26, a high resistance layer formed on the surface of the drain layer 23; It is a gate electrode formed to be in contact with each of the high resistance layers 26 on the surface.

The width of the source layer 25 is made larger than the width of the channel layer 24, and the gate electrode 27 is formed.
Are formed so as to be in contact with both side surfaces of the channel layer 24, and the gate electrode 27 has a Schottky barrier formed with respect to the channel layer 24. Although the gate electrode 27 is also in contact with the drain layer 23, the surface of the drain layer 23 in contact with the gate electrode 27 is modified to
6.

Here, semi-insulating GaAs is used as the semiconductor substrate.
The reason why the s-substrate 21 is used is that easiness of integration is taken into consideration.
It is also possible to configure T. Also, semi-insulating GaAs
N-type GaAs contact layer 2 formed on S substrate 21
Since 2 is introduced for the purpose of reducing the contact resistance of the ohmic electrode on the drain side, it can be omitted when an n-type GaAs substrate is used as the semiconductor substrate.

As the drain layer 23, for example, n-type AlGaAs having a composition of A1 of 0.25 is preferably used, but other compositions such as n-type AlGaAs and GaAs are preferably used.
For example, n-type InGaP lattice-matched to s may be used.
In addition, since a portion of the surface of the drain layer 23 that contacts the gate electrode 27 causes an increase in the parasitic capacitance of the gate, it is desirable to modify the vicinity of the contact portion to the high resistance layer 26 in advance.

When the operating frequency required for the vertical FET is not so high, the high resistance layer 26 is not provided.
The surface of the drain layer 23 may be kept at the original n-type. The donor concentration and the thickness of the n-type semiconductor constituting the drain layer 23 can be freely selected. For example,
By reducing the donor concentration or increasing the thickness of the drain layer 23, the withstand voltage of the FET can be increased.

On the drain layer 23, an n-type GaAs channel layer 24 is formed. Both the donor concentration of the channel layer 24 and the width of the channel layer 24 are vertical FE
It is an important parameter that defines the threshold voltage of T and the maximum drain current that can flow. Further, the thickness of the channel layer 24 (the distance between the source layer 25 and the drain layer 23) determines the gate length of the gate electrode 27 deposited on both side surfaces thereof, and cuts off the current gain of the vertical FET. It is an important parameter for determining high frequency characteristics such as frequency.

Source layer 2 located on channel layer 24
As 5, n-type InGaP or n-type AlGaAs can be used. However, in order to reduce the source resistance and obtain a high mutual continuity, n-type InGaP, which can dope a high concentration dopant, is more suitable.

The source electrode 5 and the drain electrode 7 are ohmic electrodes, and can be realized, for example, by forming an AuGe / Ni-based material by vapor deposition and then performing a heat treatment at about 400 ° C. Further, for the purpose of reducing the source resistance, an even higher concentration n-type GaAs is formed on the source layer 25.
The s layer is prepared as a source contact layer during initial epitaxial growth, and the source electrode 5 is
It may be formed on the contact layer. For the gate electrode 27, a metal that forms a Schottky barrier with respect to the channel layer 24 is used. Here, for example, a tungsten silicide (WSi: tungsten silicide) film formed by reactive sputtering or the like is used in order to deposit a metal with good covering properties on both sides of the recessed channel layer 24.

In this FET, when a negative voltage is applied to the gate electrode 27, a depletion layer is formed from both sides of the channel layer 24, thereby changing the electrical resistance of the channel layer 24 in the vertical direction. Now, when a positive voltage is applied to the drain electrode 7 with respect to the source electrode 5, a drain current flows from the drain electrode 7 to the source electrode 5 in the vertical direction. The magnitude of the drain current depends on the value of the gate voltage. Change. Therefore, when the relationship between the drain voltage and the drain current is plotted using the gate voltage as a parameter, a current-voltage characteristic as shown in FIG. 2 is obtained.

Next, a method of manufacturing the FET according to the present embodiment will be described with reference to the drawings. First, as shown in FIG. 3A, an n-type GaAs is formed on a semi-insulating GaAs substrate 21.
s contact layer 22, n-type AlGaAs drain layer 3
1. An n-type GaAs channel layer 32 and an n-type InGaP source layer 33 are sequentially epitaxially grown.

Next, as shown in FIG. 3B, an insulating film 34 is formed on the entire surface, and this insulating film 34 is processed into an insulating film 34a having a line width pattern by photolithography and insulating film etching. . Thereafter, anisotropic dry etching is performed by using the insulating film 34a as a mask, thereby obtaining FIG.
As shown in (c), the n-type GaAs channel layer 32 and the n-type InGaP source layer 33 are selectively etched.

Next, as shown in FIG. 3D, the surface of the exposed n-type AlGaAs drain layer 31 is
Reform to 5. As a method of this surface modification, AlGa
Either a method of directly oxidizing As or a method of introducing damage to a semiconductor by ion implantation is used. In the direct oxidation method, for example, the drain layer 31
Is AlGaAs, A1GaAs can be directly transformed into a high-resistance oxide film by thermal oxidation in a steam atmosphere. In the damage introduction method by ion implantation, AlGaAs is used as a material for forming the drain layer 31.
InGaP or the like can be used instead of s.

Next, as shown in FIG.
Only the aAs channel layer 32 is selectively etched from both side surfaces to reduce the lateral width of the n-type GaAs channel layer 32 and to reduce the lateral width of the n-type G
The aAs channel layer 24 is used. This width determines the threshold voltage of the FET.

Next, as shown in FIG. 4F, a tungsten silicide (WSi) film 37 is formed by reactive sputtering.
Is formed on the entire surface. Next, as shown in FIG.
WSi film 37 isotropically dry-etched,
The insulating film 34a is removed. As a result, the WSi film 37 remains only on both side surfaces of the n-type GaAs channel layer 24, and the gate electrode 27 whose effective gate length is determined by the thickness of the n-type GaAs channel layer 24 is obtained.

Finally, as shown in FIG. 4H, the n-type GaAs contact layer 22 is exposed using a photoresist pattern, and the n-type AlGaAs drain layer 31 and the high-resistance layer 35 are simultaneously formed. Processing into a predetermined shape, n
An ohmic source electrode 5 and a drain electrode 7 are formed on the type InGaP source layer 33 and the n type GaAs contact layer 22, respectively. By the above steps, FIG.
The vertical FET shown in (h) is completed.

In general, the withstand voltage of an FET is closely related to the occurrence of impact ionization in a high electric field region, and it is well known that a high electric field is generated near the drain end of the gate electrode 27. Impact ionization is a phenomenon that occurs when carriers are accelerated beyond the forbidden band width. Therefore, the frequency of occurrence is generally smaller for semiconductors having a larger forbidden band width. Therefore, if a semiconductor having a large forbidden band width and a small impact / ionization rate is used as the material near the drain end of the gate, the withstand voltage of the FET can be improved.

In this case, the semiconductor material immediately below the gate includes:
It is necessary to use a material with high mobility to operate the FET at high speed.However, in the vicinity of the drain end of the gate, a large electric field causes many carriers to travel at a saturation speed, so that the forbidden band width on the drain side becomes large The use of a large and small mobility semiconductor does not significantly affect the high frequency characteristics of the FET.

In the conventionally known lateral FET, since the gate electrode is formed two-dimensionally on the stacked semiconductor layers, the type of the semiconductor material is changed between the lower part of the gate electrode and the drain region. However, in a vertical FET in which the effective gate length can be defined by the thickness of the semiconductor layer, different semiconductor materials can be used for the gate region and the drain region. . In the vertical FET of the present embodiment, n forming the drain layer 23
Since the type semiconductor has a wider bandgap than the n-type GaAs forming the channel layer 24, the withstand voltage characteristics can be improved.

If the forbidden band width of the semiconductor forming the source layer 25 is made larger than the forbidden band width of the semiconductor forming the channel layer 24, the conduction band energy is formed at the interface between the source layer 25 and the channel layer 24. Becomes discontinuous. At this time, when electrons are injected from the source layer 25 into the channel layer 24,
The injected electrons travel in the channel layer 24 as hot electrons, and the time required to cross the channel layer 24 (channel traveling time) is reduced. That is, the current gain cutoff frequency of the FET can be improved by introducing the source layer 25 having a wide band gap made of a heterojunction.

When the source layer 25 and the channel layer 24 and the type of the semiconductor constituting the channel layer 24 are different from each other, an etching solution or an etching gas capable of selectively etching only the channel layer 24 is used. The width of the source layer 25 can be wider than the width of the source layer 24. As a result, the source resistance can be reduced. Also, by using this selective etching, the formation of the gate electrode 27 can be performed simply and with high accuracy.

Furthermore, if the surface of the drain layer 23 in contact with the gate electrode 27 is left as an n-type semiconductor, the carriers in the drain layer 23 show a response due to the application of the gate voltage, so that the parasitic gate And the high-frequency characteristics of the FET deteriorate. Therefore, by modifying only the surface of the drain layer 23 in contact with the gate electrode 27 to the high-resistance layer 26, the increase in the parasitic gate capacitance can be prevented, and the deterioration of the high-frequency characteristics can be suppressed.

[Second Embodiment] A method of manufacturing an FET according to a second embodiment of the present invention will be described with reference to the drawings.
Since the manufacturing method of the present embodiment has exactly the same basic components as the manufacturing method of the above-described first embodiment, FIG.
The method of manufacturing the FET according to the present embodiment will be described with reference to FIGS.

First, as shown in FIG. 3A, a semi-insulating GaAs substrate 21 is formed on a semi-insulating GaAs substrate 21 by molecular beam epitaxy.
N-type GaAs contact layer 22 doped with 1 × 10 ¹⁸ cm ^{−3 of} Si at 500 nm, and n-type AlGaAs drain layer 3 doped with 1 × 10 ¹⁷ cm ⁻³ and having an Al composition of 0.25
1 is 400 nm, n-type GaAs channel layer 32 doped with 1 × 10 ¹⁷ cm ^{−3 of} Si is 300 nm, and 3 × 10
N-type InGaP doped with ¹⁸ cm ^-3 and having a Ga composition of 0.51
The source layer 33 is sequentially grown to 300 nm.

Next, as shown in FIG. 3B, for example, the insulating film 3 made of SiO _{2 is} formed by using a low pressure CVD method.
4 is deposited on the entire surface to a thickness of 200 nm. Next, using a photolithography, for example, a photoresist pattern (not shown) having a line width of 1.5 μm is formed, and using this as a mask, an insulating film 34a of the pattern is formed. When processing the insulating film 34 using SiO ₂ , for example, buffered hydrofluoric acid is preferably used.

Next, as shown in FIG. 3C, using the insulating film 45a as a mask, the n-type InGaP source layer 33 and the n-type GaAs channel layer 32 are sequentially processed by anisotropic dry etching. At this time, by using a mixed gas of BCl ₃ and SF ₆ as the etching gas, the etching is automatically stopped when the surface of the n-type AlGaAs drain layer 31 is exposed.

Next, as shown in FIG. 3D, heat treatment at 400 ° C. in a nitrogen atmosphere containing water vapor is carried out.
The high resistance layer 35 is formed by selectively oxidizing only the surface of the n-type AlGaAs drain layer 31. This is mainly due to A
A1 contained in lGaAs is one using a property that changes in the high-resistance alumina (AI ₂ 0 ₃₎ by oxidation.

Next, as shown in FIG. 4E, only the n-type GaAs channel layer 32 is selectively etched using, for example, a mixed aqueous solution of citric acid and hydrogen peroxide.
The n-type GaAs channel layer 24 having a small line width is used. The remaining line width can be, for example, 0.5 μm.
Thereafter, as shown in FIG. 4F, a WSi film 37 is deposited to a thickness of about 150 nm on the entire surface by using a reactive sputtering method.

Next, as shown in FIG. 4G, the WSi film 37 is processed by, for example, isotropic dry etching using SF ₆ gas, and the WSi film 37 is formed only on both side surfaces of the n-type GaAs channel layer 24. Leave. The remaining WSi film 37 functions as the gate electrode 27. Next, an opening is formed in the n-type AlGaAs drain layer 31 by using photolithography, and the surface of the n-type GaAs contact layer 22 is exposed.

Finally, as shown in FIG. 4H, the exposed n-type GaAs contact layer 22 and the n-type InGaP
An ohmic electrode made of, for example, AuGe / Ni is vapor-deposited on the source layer 33, and then heat-treated at 400 ° C. to form the drain electrode 7 and the source electrode 5. Through the above steps, a vertical FET is completed. As described above, according to the method for manufacturing the FET of the present embodiment, the same effects as those of the above-described method for manufacturing the FET of the first embodiment can be obtained.

[Third Embodiment] A method of manufacturing an FET according to a third embodiment of the present invention will be described with reference to the drawings.
The manufacturing method of the present embodiment has exactly the same basic components as the manufacturing methods of the first and second embodiments described above. Therefore, by applying FIGS.
The method of manufacturing the ET will be described.

Here, the n-type InGaP source layer 33 and the n-type GaAs channel layer 32 are sequentially processed by anisotropic dry etching using the insulating film 45a as a mask in the same manner as in the second embodiment. (FIG. 3 (c)).
However, the thickness of the SiO ₂ film formed as the insulating film 34a is slightly increased to, for example, 400 nm.

Next, as shown in FIG. 3D, for example, boron (B) is ion-implanted over the entire surface,
The high resistance layer 35 is formed on the exposed surface of the n-type AlGaAs drain layer 31. Here, since the thickness of SiO ₂ is large, boron (B) ions are supplied to the n-InGaP source layer 33.
Is not injected. The ion implantation conditions for forming a good high-resistance layer 35 are the n-type A1GaAs drain layer 31.
For example, the dose may be 1 × 10 ¹⁴ cm ⁻² at an acceleration energy of −70 keV, depending on the thickness and the donor concentration.

The subsequent steps are performed in the same manner as in the second embodiment to complete a vertical FET as shown in FIG. As described above, the FET of the present embodiment
According to the manufacturing method of the first embodiment, the FET of the first embodiment
The same effect as that of the manufacturing method can be obtained.

[0053]

As described above, according to the field-effect transistor of the present invention, the second main layer having a wider bandgap than the first semiconductor is formed on one main surface of the channel layer made of the first semiconductor. Since a source layer made of a semiconductor was formed,
At the interface between the source layer and the channel layer, conduction band energy becomes discontinuous, and electrons injected from the source layer into the channel layer travel as hot electrons through the channel layer and are required to cross the channel layer. The time (channel running time) can be reduced, and the current gain cutoff frequency can be improved.

Further, since the drain layer made of the third semiconductor having a wider bandgap than the first semiconductor is formed on the other main surface of the channel layer, the withstand voltage characteristics can be improved. In addition, since the gate electrode is formed so as to be in contact with the side surface of the channel layer and the surface of the drain layer, the gate length of the gate electrode can be a short gate length determined by the thickness of the channel layer. Parasitic capacitance can be reduced. Therefore, DC characteristics and high frequency characteristics can be improved. Furthermore, the use of a hetero-drain structure makes it difficult for impact ionization to occur inside the drain layer having a large forbidden band width, allows operation under a high drain voltage, and realizes use for high power. Can be.

According to the method for manufacturing a field-effect transistor of the present invention, the step of selectively removing the channel layer and the source layer and the step of further selectively removing the channel layer are included. A vertical field-effect transistor with excellent DC and high-frequency characteristics that can form a gate electrode with a short gate length determined by the thickness of the channel layer at the time of crystal growth, regardless of the accuracy of lithography Can be manufactured with good reproducibility, so that the production yield can be improved and the productivity can be improved.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a field-effect transistor according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating voltage-current characteristics of the field-effect transistor according to the first embodiment of the present invention.

FIG. 3 is a process chart showing a method for manufacturing a field-effect transistor according to each of the first to third embodiments of the present invention.

FIG. 4 is a process chart showing a method for manufacturing the field-effect transistor according to each of the first to third embodiments of the present invention.

FIG. 5 is a sectional view showing a conventional vertical FET.

FIG. 6 is a cross-sectional view showing another vertical FET of the conventional example.

[Explanation of symbols]

Reference Signs List 1 n-type GaAs substrate 2 n-type GaAs drain layer 3 n-type AlGaAs channel layer 4 n-type GaAs source layer 5 source electrode 6 gate electrode 7 drain electrode 11 n-type GaAs channel layer 12 n-type AlGaAs source layer 13 n Type GaAs contact layer 21 semi-insulating GaAs substrate (semiconductor substrate) 22 n-type GaAs contact layer (drain / contact layer) 23 drain layer 24 n-type GaAs channel layer 25 source layer 26 high resistance layer 27 gate electrode 31 n-type AlGaAs drain Layer 32 n-type GaAs channel layer 33 n-type InGaP source layer 34 insulating film 34a insulating film 35 high-resistance layer 37 tungsten silicide (WSi) film

Claims (4)

(57) [Claims] A channel layer formed of a first semiconductor on a semiconductor substrate; and a channel layer formed on one main surface of the channel layer.
A source layer made of a second semiconductor having a wider bandgap than the first semiconductor and formed with a wider width than the first semiconductor; and a forbidden band formed on the other main surface of the channel layer and wider than the first semiconductor. A drain layer made of a third semiconductor having a band width; a gate electrode formed to be in contact with a side surface of the channel layer and a surface of the drain layer; a source electrode formed in the source layer; A field-effect transistor comprising: a drain electrode formed in a layer. 2. The method according to claim 1, wherein said third semiconductor is made of III containing Al.
And -V compound semiconductor, at least of the drain layer
High resistance containing Al on the surface in contact with the gate electrode
2. The electrode according to claim 1, wherein a layer is formed.
Field effect transistor. 3. A chip comprising a first semiconductor on a semiconductor substrate.
A channel layer and one of the main surfaces of the channel layer.
A second semiconductor having a wider bandgap than the first semiconductor
A source layer Ru Rana, formed on the other main surface of the channel layer
By a third with a band gap has a wide than the first semiconductor
To form a laminated structure having a drain layer made of a semiconductor
And selectively removing the channel layer and the source layer
A step of further selectively removing the channel layer
Field effect tiger Njisuta characterized in that a step
Manufacturing method. 4. The method according to claim 1, wherein the channel layer and the source layer are selectively removed.
After the step of removed by, i the exposed surface of the said drain layer
A process is provided to damage the ON-implantation and make the surface a high-resistance layer.
Field effect transistor according to claim 3, wherein the kite
Manufacturing method.