JP3102947B2 - Device isolation method for heterojunction field effect transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for separating a heterojunction field effect transistor from one another, which can reduce gate leakage current and improve reproducibility and uniformity.

[0002]

2. Description of the Related Art The structure of a field effect transistor (FET) using a heterojunction as a channel is shown in FIG. 4 as an example of the prior art. Non-doped In
_0.53 Ga _0.47 As layer and n-type In _0.52 Al
_0.48 As-layer heterojunction non-doped InGaAs
High-speed operation is achieved by utilizing a high-mobility two-dimensional electron gas generated on the layer side. On a semi-insulating InP substrate 41, I
nAlAs buffer layer 42, non-doped InGaAs layer 43 in which two-dimensional electron gas 46 is formed, non-doped IGaAs
After epitaxially growing a spacer layer 44 of nAlAs, a carrier supply layer 45 of n-type InAlAs, and a cap layer 47 of n-type InGaAs to form a source electrode 49-1 and a drain electrode 49-2, an InGa of a gate portion is formed.
As cap layer 47 and InAlAs carrier supply layer 45
Is etched in a concave shape, and then a gate electrode 48 is formed in the region. At this time, the epitaxial layer has grown over the entire surface of the substrate, and in order to electrically isolate each FET, it is necessary to previously remove the epitaxial layer other than the FET active layer by increasing the resistance or etching. In the case of a GaAs / AlGaAs heterojunction field effect transistor, the band gap of each semiconductor is large (GaAs: 1.43 eV, AlGa
As: about 1.9 eV) By selectively implanting oxygen ions or hydrogen ions into regions other than the FET active layer to introduce deep impurity levels, it is possible to increase the resistance of the above regions. there were. However, InGaAs
Since the bandgap of the cap layer 47 having a narrow band gap such as s is as small as 0.76 eV, it is difficult to increase the resistance by ion implantation, and element isolation by etching is usually used.

[0003]

As described above, in the prior art, isolation between elements is performed by etching a region other than the FET active region. However, as shown in FIG. 4, when the gate electrode or the power supply wiring to the gate electrode crosses the etching step for element isolation, a narrow bandgap semiconductor in which the two-dimensional electron gas exposed on the etching end face exists. Then, the gate electrode or the power supply wiring to the gate electrode comes into contact, and a current flows directly from the gate electrode to a narrow band gap semiconductor layer which is a channel, resulting in a leak current other than current control in the active region. FIG. 5A is a plan view of a main part of the element,
(B) is a diagram showing a cross section along the gate electrode. In particular, the height of a Schottky barrier between a metal and a narrow band gap semiconductor such as InGaAs is as small as about 0.2 eV, and a junction close to an ohmic junction significantly increases a gate leak current and greatly enhances device characteristics. There was a problem of deterioration.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method of isolating a heterojunction field-effect transistor, which can suppress an increase in gate leakage current.

[0005]

The above object is achieved on a substrate by:
An element isolation method for a heterojunction field-effect transistor in which a device having a heteroepitaxial structure in which a wide bandgap semiconductor layer, a narrow bandgap semiconductor layer, and a wide bandgap semiconductor layer are sequentially stacked is removed by etching and electrically separated. in, the narrow bandgap semiconductor layer exposed in the etched side face selectively etched, only the narrow band-gap semiconductor forming the overhanging portion is retracted from the end surface, the portion
This can be achieved by forming an insulating film separately.

[0006]

The present invention selectively etches the narrow bandgap layer exposed at the etching end face when separating the elements of the heteroepitaxial structure stacked including the narrow bandgap semiconductor as described above by etching. Retracts from the end face by overhanging shape
Form part, order to form an insulating film on the partial, after which the gate electrode to be formed, the insulating film is also spatially between the narrow bandgap semiconductor layer is a channel
However, they are separated from each other, and the contact between them is reliably avoided, so that the gate leakage current is reduced, and stable and reproducible high device characteristics can be realized.

[0007]

Next, embodiments of the present invention and reference examples will be described with reference to the drawings. Fig. 1 shows one way to solve the above problem .
Manufacturing process diagram showing a reference example of the element isolation method of a heterojunction field effect transistor is a law 2 Contact Reference Example
FIG. 3 is a view showing the effect of the above embodiment, and FIG. 3 is a manufacturing process diagram showing a first embodiment of the device isolation method of the present invention.

[0008] In FIG. 1, showing a reference example Reference Example, (a), the
On the semi-insulating InP substrate 11, a non-doped In _0.52 Al _0.48 As layer 12 as a wide band gap semiconductor layer and a non-doped In _0.53 as a narrow band gap semiconductor layer are formed by, for example, molecular beam epitaxial growth. A Ga _0.47 As layer 13 of 30 nm;
Non-doped In as a wide bandgap semiconductor layer
_0.52 Al _0.48 As layer 14 is 2 nm, Si is 4 ×
10 ¹⁸ cm- ³ doped In _0.52 Al
_0.48 As layer 15 of 25 nm, Si of 4 × 10 ¹⁸ c
The _In 0.53 _{Ga 0.47} As layer 16 was m ~ ³ doped 10 nm, are sequentially grown. Reference numeral 17 denotes a secondary electron gas to be formed. Next, after a resist pattern 18 having an opening other than the element portion is formed, the In ₀ .1 is formed by using an etching solution such as a mixed solution of sulfuric acid and hydrogen peroxide in which the etching speed of the resist opening with respect to InAlAs and InGaAs is substantially equal _{. 53} Ga
_0.47 As layer 16, In _0.52 Al _0.48 As layer 15, In _0.52 Al _0.48 As layer 14, In
_0.53 Ga _0.47 As layer 13 and In _0.52 A
l _0.48 A part of the As layer 12 is removed as shown in FIG. Then, the etching rate of InGaAs becomes I
Etching is further added by an etching solution sufficiently fast with respect to the etching rate of nAlAs, for example, a mixed solution of citric acid and hydrogen peroxide solution. At this time, the In _0.53 Ga _0.47 As layer 16 exposed on the etching end face
1B and the end surface of the In _0.53 Ga _0.47 As layer 13 are selectively etched, receding from the end surface shown in FIG. 1B, and become as shown in FIG. Next, a resist pattern having an opening in the ohmic region is formed, and FIG.
Ohmic electrodes 19 are formed as shown in FIG. Thereafter, a resist pattern having an opening in a gate region is formed, and a concave etching is performed until a desired drain current is reached. Then, a gate metal is deposited to provide a gate electrode 20 as shown in FIG. The FET is completed.
At this time, the gate electrode 20 and a step portion formed by etching for element isolation have a cross section as shown in FIG. 1F, and the gate electrode 20 and In _0.53 Ga _0.47 which are narrow band gap semiconductors are formed. Since the As layer 13 is spatially separated from the As layer 13 and the contact between them is reliably avoided, the gate leakage current is reduced by the In _0.52 Al _0.48 As layer 15 which is a wide band gap semiconductor. Thus, the gate leakage current can be suppressed to a low value.

Therefore, the FE using the structure of this embodiment is
Comparing the Schottky characteristic of T with that of the FET having the conventional structure, the Schottky characteristic of the conventional structure is InGaAs having a low Schottky barrier height because the gate electrode is in contact with InGaAs as shown in FIG. The gate leakage current is extremely large, which is determined by the above characteristics. However, in the FET according to the present reference example , the gate leakage current is suppressed to a low value as described above, so that the height of the Schottky barrier is improved. As shown in FIG. 2, the gate leakage current is greatly reduced. In the figure, curves 1 and 2 show the case of the FET by the conventional device isolation method, and curves 3 and 4 show the cases of the FET by the device isolation method of the present embodiment and the first embodiment described later. The curve 1 and the curve 3 show the case where the gate voltage is changed from 0 to +2, and the gate leak current is remarkably reduced on the side where the gate voltage is low. Curves 2 and 4 show the case where the gate voltage is changed in the opposite direction, and the gate leak current is reduced over the entire region.

[0010] The first embodiment of the first embodiment the present invention will be described with reference to FIG. On the semi-insulating InP substrate 21, a non-doped In _0.52 Al _0.48 As layer 22 as a wide bandgap semiconductor layer is formed on the semi-insulating InP substrate 21 by, for example, molecular beam epitaxy.
m, non-doped In as a narrow bandgap semiconductor layer
_{The 0.53} Ga _0.47 As layer 23 has a thickness of 30 nm and is a non-doped In _0.52 A as a wide band gap semiconductor layer.
l _0.48 As layer 24 is 2 nm, Si is 4 × 10 ¹⁸ c
25 nm of the In _0.52 Al _0.48 As layer 25 doped with m- ^{3, and} 10 n of the In _0.53 Ga _0.47 As layer 26 doped with 4 × 10 ¹⁸ cm- ^{3 of} Si.
m, and sequentially grown and laminated as shown in FIG.
Next, after a resist pattern 28 having an opening other than the element portion is formed, an In _0.53 is formed by using an etching solution such as a mixed solution of sulfuric acid and hydrogen peroxide solution in which the etching speed of the resist opening with respect to InAlAs and InGaAs is substantially equal. Ga _0.47 As layer 26, In
_0.52 Al _0.48 As layer 25, In _0.52 Al
_{After a part of the 0.48} As layer 24, the In _0.53 Ga _0.47 As layer 23 and the In _0.52 Al _0.48 As layer 22 is removed as shown in FIG.
Etching is further performed with an etching solution having an etching rate of s sufficiently higher than that of InAlAs, for example, a mixed solution of citric acid and hydrogen peroxide solution. At this time, the In exposed on the etching end face
_0.53 Ga _0.47 As layer 26 and In _0.53 G
The end face of the a _0.47 As layer 23 is selectively etched as shown in FIG. 3C, and recedes from the end face shown in FIG. Next, a resist pattern having an opening in the ohmic region is formed, and ohmic electrodes 29 are formed as shown in FIG. Thereafter, an insulating film 30 of, for example, SiO ₂ is deposited as shown in FIG. 3E using a plasma CVD method having an isotropic film forming characteristic at a relatively low temperature, and then an opening is formed in the gate region. Is formed. Using the resist pattern as a mask, the insulating film 30 at the resist opening is removed by an anisotropic etching method such as reactive ion etching,
Further, after performing a concave etching to reach a desired drain current, a gate metal is deposited to complete an FET having a gate electrode 31 as shown in FIG. 3 (f). At this time, the gate electrode 31 and the etching step portion for element isolation have a cross section as shown in FIG. 3G, and the gate electrode 31 and In _0.53 Ga _0.47 As, which are narrow band gap semiconductors, are formed. The layer 23 is separated from the layer 23 by a space separated by the insulating film 30. The FET in this embodiment and the FE in the above reference example
T means that the semiconductor portion has exactly the same configuration
As for the initial characteristics, the same characteristics, that is, FIG.
It has the characteristics shown by curves 3 and 4 in FIG.

[0011] However, the separation space formed between the gate electrode 20 and the _In 0.53 _{Ga 0.47} As layer 13 due to the reference example, although there is a concern that contact by the movement of the gate metal On the other hand , when considering the long-term stability, it is possible to stably suppress an increase in the gate leak current by forming the insulating film 30 on the overhang portion on the element separation end face by applying the first embodiment.

[0012]

As described above, the method for separating the elements of the hetero-junction field effect transistor according to the present invention has the following advantages.
An element isolation method for a heterojunction field-effect transistor in which a device having a heteroepitaxial structure in which a wide bandgap semiconductor layer, a narrow bandgap semiconductor layer, and a wide bandgap semiconductor layer are sequentially stacked is removed by etching and electrically separated. In the above, the narrow bandgap semiconductor layer exposed on the etching end face is selectively etched, and only the narrow bandgap semiconductor is receded from the end face to form an overhang shape portion,
By forming an insulating film in this portion, a space is formed between the end face of the narrow bandgap semiconductor layer and the gate electrode of the element, and an insulating film is formed and separated in the space. Change the value of the leakage current by
Gate leakage current may increase due to contact
It can be deterred low without concern .

Although it is conceivable that InAs having a smaller band gap is used as the channel material in order to improve the performance of the FET, the present invention has the same effect on these material systems. As the bandgap of the channel material becomes smaller, the importance of the present invention will further increase.

[Brief description of the drawings]

[1] a diagram showing a device isolation how the heterojunction field effect transistor in reference example illustrates the (a) ~ (f) each manufacturing process.

FIG. 2 is a diagram showing effects of the reference example and the first embodiment .

FIGS. 3A to 3G are views showing a first embodiment of a device isolation method according to the present invention, wherein FIGS.

FIG. 4 is a diagram showing a conventional method for separating elements.

FIGS. 5A and 5B are diagrams showing a step of separating and etching between elements in the above-mentioned conventional technology, wherein FIG. 5A is a plan view of a main part of the element, and FIG.

[Explanation of symbols]

11, 21 Substrate 12, 14, 22, 24 Wide band gap semiconductor layer 13, 23 Narrow band gap semiconductor layer

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-63-318165 (JP, A) JP-A-4-280642 (JP, A) JP-A-5-275415 (JP, A) JP-A-5-275415 182991 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 29/778 H01L 21/338 H01L 21/76 H01L 29/812

Claims (1)

(57) [Claims] A heterojunction in which a device having a heteroepitaxial structure in which a wide bandgap semiconductor layer, a narrow bandgap semiconductor layer, and a wide bandgap semiconductor layer are sequentially stacked on a substrate is removed by etching and electrically separated. in the element isolation method type field effect transistor, the narrow bandgap semiconductor layer exposed in the etched side face selectively etched, only the narrow band-gap semiconductor forming the overhanging portion is retracted from the end surface, A method for separating elements of a heterojunction field effect transistor, comprising forming an insulating film on the portion .