JPS6115375A - Hetero junction fet - Google Patents

Abstract

PURPOSE:To improve the characteristic by reducing the resisrance of a source- drain layer by forming an eutectic layer of high conductivity on the surface of a source-drain region. CONSTITUTION:An N type GaAs layer 22 is epitaxially grown on a semiconductor substrate 21 doped with Cr, and an AlXGa1-XAs layer 23 and a W layer 24 are formed thereon, and then etched by using a resist layer 25 as a mask; further, Si is ion-implanted to the source-drain region 26. An Si oxide film 27 is formed after removal of the mask, and a side wall 28 of oxide film is formed at the gate region by reactive ion etching. Pt is evaporated over the whole surface, and an intermetallic compound layer of Pt/GaAs is formed by annealing at about 400 deg.C and then oxidized. Thereafter, etching is carried out by using this layer as a mask, when intermetallic layers 291 and 292 of Pt/GaAs are formed to the source-drain, and electrodes 211, 211, and 213 are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to the structure of a heterojunction field effect transistor.

(Prior art and its problems) Heterostructure field effect transistors (ETs) are promising as high-speed devices.

Figure 1 shows two heterojunction FETs presented at an academic conference.
A Q example is shown. Figure 1 (Al is semi-insulating GaAs-A1 doped with Or, for example.
Grow As layer 2, and further grow n-type AlXGa, As
Grow N3. As for X, the value of Shinto 0°3 is taken. Next, an n-type OaAs layer 4 is formed, and after etching the n-type OaAs layer 4 in the gate area, the gate is etched (
Form V5. 4. Source/drain electrodes 6, 7,
It is formed to make ohmic contact with the n-type OaAs substrate 2.

In the example of FIG. 1(b), AAixGa1. AsN
3 A non-doped layer is used here. Next, a Tammy oxide film pattern is formed on the gate region 5, and using this as a mask, the source 8. Drain 9 is formed by ion implantation.

After that, the gate electrode 5. A source electrode @6° drain region pole 7 is formed.

In all of these examples, there is a problem in that the source/drain resistance increases and the characteristics of the device deteriorate.

(Object of the Invention) An object of the present invention is to solve these problems and provide a heterojunction field effect transistor with low source-drain resistance.

(First Embodiment) FIGS. 2(a) to 2(e) are sectional views for explaining the first embodiment of the present invention. For example, on an insulating substrate 21 doped with Or, an n-type GaAs layer 22 (for example, Si doped with 5 x 1015 cIrL-3, thickness 0.2μ) is formed.
m) is epitaxially grown. On top of that, non-doped or Si-doped (e.g. IQ" crn-3) (
, AJ'GaX 1-X AsMiI23 (e.g. x = o, 3, thickness 8
00A) is epitaxially grown. Next, for example, W
A layer 24 is formed, and the gate region is etched using the resist Jii 25 as a mask. Furthermore, using these as a mask, Si ions are implanted into the source/drain regions 26.

(See Figure 2 (a) above) Next, a silicon oxide film 27 is grown by vapor phase growth.

(FIG. 2(b)) Next, the oxide film 27 is dry etched by reactive ion etching to form side walls of the oxide film in the gate region. (Figure 2 (C)) Next, PL was deposited on the entire surface, annealed at about 400°C, and PL
An intermetallic compound layer of t/GaAs is formed. After that, the wafer is oxidized, and the surface layer of the intermetallic compound has a thin layer of Ga, 0. A layer is formed. Using it as a mask, etch the PT with KON solution at 60°C to 100°C.
Then, only the P't/UaAs intermetallic compound layers 291 and 292 remain on the source and drain. (FIG. 2(d)) Next, a silicon oxide film 210 is formed on the entire surface, and then contacts are opened to the source/drain and gate r, and gates 211. Source 212° Drain 2
Each of the 13 electrodes is of the form IIx,T. (Second panel (e)) In this transistor structure, the resistance of the source and drain is small due to the eutectic layers 291 and 291 of the source and drain, and even for a transistor with a large gain, the series resistance is negligible. This structure is small, Ni,
Ti, W, Mo, etc. can also be realized by appropriate process changes. Especially WF.

+3H2→W The reduction reaction of +6HF (200 to 700°C) can be used because W selectively grows on the conductor and metal grown on the oxide film.

(Second Embodiment) FIGS. 3(at) and 3(b) are cross-sectional views illustrating a second embodiment of the present invention. In this embodiment, the gate electrode 31 is made of highly doped n-type GaAs. For example, the gate electrode 31 may be doped with IXIOlBcm-3 as a dopant, and the thickness of the gate electrode 31 may be set to 0.5 μm.

1XGa1. The As layer % may be non-doped or heavily doped. (FIG. 3(a)) Next, the structure shown in FIG. 3(b) is formed in the same steps as in FIGS. 2(b) to 2(d). However, in Figure 3(b), G
A eutectic layer 32 is also formed in the a As gate 31 . Finally, create a structure similar to that shown in Figure 2(e).

(Third Embodiment) FIG. 4 is a sectional view illustrating a third embodiment of the present invention. In this embodiment, no sidewall oxide film is used.

AltfIR4] is formed on the n-type GaAs layer 31 and then removed.

A 5i01 film 42 is grown to a thickness of about 0.5 μm using the evening method. Next, using the resist 43 as a mask, the gate region is covered with an oxide film, kl*n-GaAs, AlXGa 1. Etch down to the As film. The resist film 43 is removed, and then the source and drain layers 26 are formed by 8i ion implantation. Next, a thin film of Pt/Ge is grown.

(FIG. 4(a)), after forming a eutectic layer by heat treatment, the L't/Ge that has not become eutectic is etched, and the oxide film is etched. Finalization Create a structure similar to that shown in Figure 2(e). (・Fig. 4 Φn) (Another embodiment) The present invention is based on A J x Ga 0. cA s /G
a A s The FgT of the yarn was described in Examples and (7),
The same holds true for many other combinations of heterojunction materials or for FBTs containing superlattice structures. Also, the material of the source/drain and gate electrodes is Ga
Any material that forms an ohmic eutectic layer with As or other substrate semiconductors may be used. Also, regarding etching of the eutectic layer,
Any method may be used as long as the eutectic layer is left unetched and only the electrode metal is etched, and dry etching or wet etching may be used. In addition to the above embodiments, the combination of heterojunctions is InAlAs/ InP
(x:0.5), In, Ga,, AsX
1-X/InP (x”:ZO,5), AAxIn
,,P/GaAs (x:o,5)A ji' 1
n P/ I n y Ga I, A s (xgo 0
．． 5. y,:o,s).

X 1-X GaxI n 1. CP/GaAs I, x20.5
) etc. are possible.

These have large band discontinuity and can provide excellent characteristics as the field effect transistor of the present invention. Furthermore, a structure in which an insulating film is sandwiched between a wide bandgap semiconductor and a gate electrode is also considered.

Further, although the above embodiments have been described with respect to an N-channel field effect transistor, a similar structure can also be applied to a P-thickness field effect transistor.

Furthermore, although the conductivity type of the semiconductor for the gate electrode is the same as that of the channel conduction type, the present structure can also be applied to the opposite case.

(Effects of the Invention) By forming the eutectic layer as described above in the present invention, the resistance of the source filler layer can be lowered, and the characteristics of the heterojunction field effect transistor can be improved.

[Brief explanation of the drawing]

FIGS. 1(a) and 1(b) are cross-sectional views showing a conventional transistor structure. FIGS. 2(a) to 2(e) are cross-sectional views illustrating the first embodiment. FIGS. 3(, 1) and 3(b) are cross-sectional views illustrating the second embodiment. FIGS. 4(a) and 4(b) are sectional views explaining the third embodiment. 1.21--GaAs substrate, 2.4.22--G
a As layer, 3.23...A#GaAs layer,
6, 7... Source/fin 4 electrode, 291,
292...Eutectic layer 1 Figure 1 1 2QI 2q2 3rd, Figure

Claims (3)

[Claims] (1) A field effect transistor that utilizes conductivity modulation at the heterojunction interface and is formed so that the source/drain impurity layer overlaps the gate electrode has a highly conductive eutectic layer on the surface of the source/drain region. Heterojunction field effect transistor. (2) The heterojunction field effect transistor according to claim 1, wherein a semiconductor layer with a high impurity concentration is used as the gate electrode, and a highly conductive eutectic layer is formed on the surface of the semiconductor layer. (3) The heterojunction field effect transistor according to claim 1 or 2, wherein an insulating film is formed on the side surface of the gate electrode.