JPS63228762A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS63228762A JPS63228762A JP6294387A JP6294387A JPS63228762A JP S63228762 A JPS63228762 A JP S63228762A JP 6294387 A JP6294387 A JP 6294387A JP 6294387 A JP6294387 A JP 6294387A JP S63228762 A JPS63228762 A JP S63228762A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- type
- gate electrode
- ohmic
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 239000004065 semiconductor Substances 0.000 title claims description 14
- 229910052751 metal Inorganic materials 0.000 claims abstract description 26
- 239000002184 metal Substances 0.000 claims abstract description 26
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 239000010410 layer Substances 0.000 claims description 59
- 238000000034 method Methods 0.000 claims description 17
- 229920002120 photoresistant polymer Polymers 0.000 claims description 12
- 150000001875 compounds Chemical class 0.000 claims description 6
- 239000002344 surface layer Substances 0.000 claims description 2
- 238000005530 etching Methods 0.000 claims 1
- 230000010354 integration Effects 0.000 abstract description 5
- 230000003071 parasitic effect Effects 0.000 abstract description 4
- 230000008020 evaporation Effects 0.000 abstract description 2
- 238000001704 evaporation Methods 0.000 abstract description 2
- 150000002739 metals Chemical class 0.000 abstract description 2
- 238000007493 shaping process Methods 0.000 abstract 1
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 5
- 125000006850 spacer group Chemical group 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 3
- 238000001451 molecular beam epitaxy Methods 0.000 description 3
- 238000000992 sputter etching Methods 0.000 description 3
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 101000608750 Arachis hypogaea Alpha-methyl-mannoside-specific lectin Proteins 0.000 description 1
- 101000771730 Tropidolaemus wagleri Waglerin-3 Proteins 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical compound [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- PXBRQCKWGAHEHS-UHFFFAOYSA-N dichlorodifluoromethane Chemical compound FC(F)(Cl)Cl PXBRQCKWGAHEHS-UHFFFAOYSA-N 0.000 description 1
- 235000019404 dichlorodifluoromethane Nutrition 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
- H01L29/205—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/452—Ohmic electrodes on AIII-BV compounds
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は半導体装置の製造方法に関し、特に化合物半導
体を用いたトランジスタの製造方法に関するものである
。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a transistor using a compound semiconductor.
従来の技術
化合物半導体はＳｉに比べ電子移動度が大きく高周波特
性に優れた半導体装置を得ることが可能である。化合物
半導体の中でもＧ ａ Ａ ｍは、早くから研究され、
Ｇ ａ Ａ ｓショットキ障壁型電界効果トランジスタ
は、集積回路への応用が活発に行なわれている。また最
近では結晶成長技術の向上により、ヘヂロ接合構造のデ
バイスの開発も盛んに行なわれるようになり、特にＮ型
Ａ Ｉ Ｇ ａ Ａ ｓとＧ ａ Ａ ｓの界面にたま
る高移動度の電子をゲート電圧によって制御する高電子
移動度トランジスタ（Ｈｉｇｈ Ｅｌｅｃｔｒｏｎ Ｍ
ｏｂｉｌｉｔｙ Ｔｒａｎｓｉｓｔｏｒ；ＨＥＭＴ）は
集積回路への応用も既に進められている。しかしながら
これら化合物半導体デバイスの作製プロセスはＳｔ プ
ロセスはど成長しておらず、プロセスの進歩が今後重要
となる。第３図は、ＨＥＭＴを製造する従来の製造方法
を示すものである。第３図において４１は半絶縁性Ｇ
ａ Ａ ｓ基板、４２はノンドープＧ ａ Ａ ｓ層、
４３はノンドープＡｌＧａＡｓ スペーサ層、４４はＮ
型層 Ｉ Ｇ ａ Ａ ｓ 層、４６はＮ型層 ａ Ａ
ｓキャップ層、４６はオーミック電極、４７はゲート
電極である。Conventional compound semiconductors have higher electron mobility than Si and can provide semiconductor devices with excellent high frequency characteristics. Among compound semiconductors, GaAm was researched from an early stage.
GaAs Schottky barrier field effect transistors are being actively applied to integrated circuits. In recent years, with the improvement of crystal growth technology, devices with heterojunction structures have been actively developed. High electron mobility transistor (High Electron M) controlled by gate voltage
The application of power transistor (HEMT) to integrated circuits is already underway. However, the St process has not yet developed as a manufacturing process for these compound semiconductor devices, and progress in the process will be important in the future. FIG. 3 shows a conventional manufacturing method for manufacturing a HEMT. In Figure 3, 41 is semi-insulating G
aAs substrate, 42 is a non-doped GaAs layer,
43 is a non-doped AlGaAs spacer layer, 44 is N
Type layer I G a A s layer, 46 is N type layer a A
s cap layer, 46 is an ohmic electrode, and 47 is a gate electrode.
半絶縁性Ｇ ａ Ａ ｓ基板４１上に分子線エピタキシ
ー法でノンドープＧ ａ Ａ ｓ層４２、ノンドープＡ
Ｉ Ｇ ａ Ａ ｓ スペーサ層４３、Ｎ型層 Ｉ
Ｇ ａ Ａ ｓ 層４４、Ｎ型層 ａ Ａ ｓ層４６
は成長する（ａ）。その後、リフトオフ法でオーミック
金属例えばＡ ｕ Ｇ＠／Ｎｉ／Ａｕを形成し４６０℃
、６分間アロイレオ−ミック電極４６を形成する（ｂ）
。次にソース・ドレイン電極間にゲート電極開口部をフ
ォトレジスト等で形成し、Ｎ型層 ａ Ａ−キャップ層
４５を除去しＮ型層 Ｉ Ｇ ａ Ａ ｓ上にゲート金
属例えばＴｉ／Ｐｔ／Ａｕをリフトオフ法で形成しゲー
ト電極４７を形成し、ＨＥＭＴを完成する（Ｃ）。A non-doped Ga As layer 42 and a non-doped A layer are formed on a semi-insulating Ga As substrate 41 by molecular beam epitaxy.
I Ga As spacer layer 43, N type layer I
G a As layer 44, N type layer a As layer 46
grows (a). After that, an ohmic metal such as AuG@/Ni/Au is formed using a lift-off method at 460°C.
, forming the alloy rheomic electrode 46 for 6 minutes (b)
. Next, a gate electrode opening is formed between the source and drain electrodes using a photoresist or the like, the N-type layer aA-cap layer 45 is removed, and a gate metal such as Ti/Pt/Au is formed on the N-type layer IGaAs. A gate electrode 47 is formed by a lift-off method, and the HEMT is completed (C).
発明が解決しようとする問題点
第３図で説明したようなＨＥＭＴの製造方法は、オーミ
ック接触のオーミック電極とショットキ接触のゲート電
極は異種の材料からなり、ゲート電極は、ソースオーミ
ック電極とドレインオーミック電極の間に別の工程で形
成しなければならなく、ソース・ドレインオーミック電
極とゲート電極の短絡を防ぐためにソース電極およびド
レイン電極とゲート電極の間隔はある程度大きくしなけ
ればならなかった。このためソース寄生抵抗は増大し素
子特性に悪影響を及ぼしていた。また素子占有面積も大
きく集積化には問題があった。Problems to be Solved by the Invention In the HEMT manufacturing method as explained in FIG. The electrodes must be formed in a separate process, and the distance between the source and drain ohmic electrodes and the gate electrode must be increased to some extent to prevent short circuits between the source and drain ohmic electrodes and the gate electrode. As a result, the source parasitic resistance increases, which adversely affects device characteristics. Furthermore, the device occupies a large area, which poses a problem in integration.
問題点を解決するための手段
前記問題点を解決するために本発明は、表面層がＮ型層
ａ Ａ ｓ層からなる化合物半導体基板表面に高濃度
Ｎ型ＩｎｘＧａ１−ｘＡｓ 層を形成する工程と、ゲー
ト電極形成部の前記高濃度Ｎ型ＩｎｘＧａ１−ｘＡＳ層
を除去し前記Ｎ型Ｇ ａ Ａ ｓ層を露出させる工程と
、？Ｎ型ＩｎｘＧａ１ −ｘＡｓ 層下部に凹部を形
成する工程と、前記ゲート電極形成部および前記高濃度
Ｎ型Ｉ ｎｘＧａｌ、Ａｒｔ 層上にフォトレジスト
を用いて単一の開口部を形成する工程と、ショットキ金
属を基板と垂直の方向から全面に形成する工程と、前記
７オトレジスト上のショットキ金属を選択的に除去する
工程からなるものである。Means for Solving the Problems In order to solve the above problems, the present invention includes a step of forming a highly concentrated N-type InxGa1-xAs layer on the surface of a compound semiconductor substrate whose surface layer is an N-type layer aAs layer. , a step of removing the high concentration N-type InxGa1-xAS layer in the gate electrode forming portion and exposing the N-type GaAs layer; A step of forming a recess in the lower part of the N-type InxGa1-xAs layer, a step of forming a single opening using a photoresist on the gate electrode forming part and the high concentration N-type InxGal, Art layer, and a Schottky method. This process consists of a step of forming metal on the entire surface in a direction perpendicular to the substrate, and a step of selectively removing the Schottky metal on the photoresist.
作 用
本発明は上記した構成により、オーミック電極形成部に
高濃度Ｎ型層を設け、オーミック電極とゲート電極を同
一の電極金属でしかも同時に形成できるトランジスタの
製造方法を提供するものである。また、本発明では、オ
ーミック電極とゲート電極との距離が短かくできソース
寄生抵抗の低減による特性の向上や、素子面積の減少に
よる高集積化も可能となる。Function The present invention provides a method of manufacturing a transistor having the above-described structure, in which a highly concentrated N-type layer is provided in the ohmic electrode forming portion, and the ohmic electrode and the gate electrode can be formed using the same electrode metal and at the same time. Further, according to the present invention, the distance between the ohmic electrode and the gate electrode can be shortened, and characteristics can be improved by reducing source parasitic resistance, and high integration can be achieved by reducing the element area.
実施例
本発明半導体装置の製造方法の第１の実施例を第１図に
示す。第１図において１は半絶縁性ＧａＡｓ基板、２は
ノンドープＧ ａ Ａ ｓ層、３はノンドープＡ４Ｇａ
Ａｓ スペーサ層、４はＮ型層 Ｉ Ｇ ａ Ａ ｓ
層、６はＮ型層 ａ Ａ ｓキャップ層、６は高濃度
Ｎ型ＩｎＧａＡｓ層、７はゲート電極形成部、τは凹部
、８はオーミック電極形成部、９はフォトレジスト、１
０はショットキ金属、１１はゲート電極、１２はオーミ
ック電極である。Embodiment A first embodiment of the method for manufacturing a semiconductor device of the present invention is shown in FIG. In FIG. 1, 1 is a semi-insulating GaAs substrate, 2 is a non-doped GaAs layer, and 3 is a non-doped A4Ga substrate.
As spacer layer, 4 is N type layer I Ga As
6 is an N-type layer aAs cap layer, 6 is a high concentration N-type InGaAs layer, 7 is a gate electrode formation part, τ is a recessed part, 8 is an ohmic electrode formation part, 9 is a photoresist, 1
0 is a Schottky metal, 11 is a gate electrode, and 12 is an ohmic electrode.
半絶縁性Ｇ ａ Ａ ｔ＊基板１上に分子線エピタキシ
ー法を用いてノンドープＧ ａ Ａ ｓ層２を５０００
Ａ、ノンドープＡｌＧａＡｓ 、Ｘ、ペーサ層３を２０
人、ＳＬをＩ Ｘ １ ｏ１８Ｃ１ｌ−５ドープしたＮ
型層 Ｉ Ｇ ａ Ａ ｓ 層４を４００人、ｓｔを５
Ｘ １０”４”−３ドープしたＮ型層ａＡｌキ＋７ブ
層６を１００ＯＡ、その上に８１を５Ｘ１０ （Ｆｌ
ｌｌ ドープした高濃度Ｎ型Ｉ ｎ ｘＧ ａ １ｘ
Ａ ｍ 層６をＩを０から０．７’ｄで増大させな
がら５００人形成する（ａ）。次にゲート電極形成部７
の高濃度Ｎ型ＩｎｘＧａ１−ｘＡｓ 層をイオンミリ
ングで除去しＮ型層 ａ Ａ ｓキャップ層６を露出さ
せ、その後活性層をメサエッチングする伽）。A non-doped GaAs layer 2 with a thickness of 5000 nm is formed on a semi-insulating GaAt* substrate 1 using molecular beam epitaxy.
A, non-doped AlGaAs, X, spacer layer 3 at 20
Human, SL I X 1 o18C1l-5 doped N
Type layer I G a A s 400 people in layer 4, 5 people in st
X 10"4"-3 doped N type layer aAl +7 layer 6 at 100OA, 81 on top
ll Doped highly concentrated N-type I n xG a 1x
500 A m layers 6 are formed while increasing I from 0 to 0.7'd (a). Next, the gate electrode forming part 7
The high concentration N-type InxGa1-xAs layer is removed by ion milling to expose the N-type aAs cap layer 6, and then the active layer is mesa-etched.
次に、ゲート電極形成部７のｎ型層 ａ Ａ ｓキャッ
プ層６をＣＣｌ２Ｆ２ガスのりアクティブイオンエツチ
ングで選択的に除去し、わずかにサイドエツチングし高
濃度Ｎ型ＩｎｘＧａ１−ｘＡＳ 層６の下部に凹部７′
を形成する（ｃ）。次に７オトレジスト９を用いてゲー
ト電極形成部７およびオーミック電極形成部８の高濃度
Ｎ型ＩｎＧａＡｓ 層ｅ上に単一の開口部を設け、全面
にショットキ金属１０例えばＴｉ／Ｐｔ／Ａｕを基板と
垂直方向から蒸着で形成する（ｄ）。その後リフトオフ
法でフォトレジストｓ上の不要ゲート金属１ｏを除去し
、開口部のみにゲート金属１ｏを残こす。この時、ゲー
ト金属１０は法線蒸着により形成するため、オーミック
電極形成部とゲート電極形成部のゲート金属は接触する
ことなく形成でき、ゲート電極１１とオーミック電極１
２が同時に形成できＨＥＭＴが完成する（ｅ）。Next, the n-type aAs cap layer 6 of the gate electrode forming portion 7 is selectively removed by active ion etching using CCl2F2 gas, and slightly side-etched to create a recess at the bottom of the highly concentrated N-type InxGa1-xAS layer 6. 7′
(c). Next, a single opening is formed on the highly doped N-type InGaAs layer e of the gate electrode forming part 7 and the ohmic electrode forming part 8 using a 7-photoresist 9, and a Schottky metal 10 such as Ti/Pt/Au is applied to the entire surface of the substrate. (d). Thereafter, the unnecessary gate metal 1o on the photoresist s is removed by a lift-off method, leaving the gate metal 1o only in the opening. At this time, since the gate metal 10 is formed by normal vapor deposition, the gate metals in the ohmic electrode forming part and the gate electrode forming part can be formed without contacting each other, and the gate electrode 11 and the ohmic electrode 1 can be formed without contacting each other.
2 can be formed at the same time, completing the HEMT (e).
次に第２の実施例を第２図に示す。第２図において、２
１は半絶縁性Ｇ ａ Ａ ｓ基板、２２は活性層、２３
は高濃度Ｎ型ＩｎｘＧａ１−ｘＡｓ 層、２４はゲー
ト電極形成部、２４′は凹部、２６は絶縁膜、２６は絶
縁膜の側壁部、２７はフォトレジスト、２８はショット
キ金属、２９はオーミック電極、３゜はゲート電極であ
る。Next, a second embodiment is shown in FIG. In Figure 2, 2
1 is a semi-insulating GaAs substrate, 22 is an active layer, 23
24 is a gate electrode formation part, 24' is a recessed part, 26 is an insulating film, 26 is a side wall part of the insulating film, 27 is a photoresist, 28 is a Schottky metal, 29 is an ohmic electrode, 3° is the gate electrode.
半絶縁性Ｇ ａ Ａ ｓ基板２１にイオン注入法を用い
てＳＬイオンを５０ Ｋｅｖで５Ｘ１０ ｃ！Ｒイオ
ン注入し、アルシン雰囲気中で８２０℃１５分間熱処理
し活性層２２を形成する（ａ）。次に分子線エピタキシ
ー法でＳｔを５ Ｘ １０”ｃｓ−’ ドーピングし
た高濃度Ｎ型ＩｎＧａＡｓ層２３を全面に形成する（ｂ
）。次にイオンミリングでゲート電極形成部２４の高濃
度Ｎ型ＩｎＧａＡｓ を除去する（Ｃ）。そして全面に
絶縁膜２６例えばシリコン窒化膜をプラズマＣＶＤ法で
形成する（ｄ）。その後全面をリアクティブイオンエツ
チングし平坦部のシリコン窒化膜を除去し、ゲート電極
形成部２４の側壁のみに絶縁膜の側壁部２６を形成する
（・）。次に活性層２２をリン酸系エッチャントでエツ
チングし高濃度Ｎ型Ｉ ｎ 、Ｇ ａ １．Ａ ｓ
２３下部に凹部２４′を形成しフォトレジスト２７を用
いてゲート電極形成部２４およびゲート電極形成部２４
の両側のオーミック電極形成部上に単一の開口部を形成
し、全面にショットキ金属２８例えばＴｉ／Ｐｔ／Ａｕ
を法線蒸着で形成する（ｆ）。その後リフトオフ法でフ
ォトレジスト２７上の不要ゲート金属を除去し、開口部
のみにゲート金属２８を残こす。この時ゲート電極形成
部とオーミック電極形成部は絶縁膜で分離されているた
め接触はせず、オーミック電極２９とゲート電極３０が
同時に形成でき、ＦＥＴが形成できる（ｑ）。以上、２
つの実施例を説明したが、ゲート金属のＴ ｉ ／Ｐ
ｔ ／Ａｕは、ｎ型層ａＡｓ＋ｎｉＡ Ｉ Ｇ ａ Ａ
ａ上ではショットキ接合となりオーミック接合にはな
らない。しかし、ｊｇＧａＡｉはバンドギャップが狭く
かつ高濃度にドーピングしたＮ型ＩｎＧａＡｓ上では、
Ｔｉ／Ｐｔ／Ａｕでもオーミック接合となる。このため
本発明では高濃度Ｎ型ＩｎＧａＡｓ を用いることによ
り、一種類の金属でオーミック電極とショットキゲート
電極が、同一プロセスでセルフアライメントで形成でき
るのである。Using the ion implantation method, SL ions are implanted into the semi-insulating GaAs substrate 21 at 50 Kev in 5×10 c! R ions are implanted and heat treated at 820° C. for 15 minutes in an arsine atmosphere to form an active layer 22 (a). Next, a high concentration N-type InGaAs layer 23 doped with 5 x 10"cs-' of St is formed on the entire surface by molecular beam epitaxy (b
). Next, the high concentration N-type InGaAs in the gate electrode forming portion 24 is removed by ion milling (C). Then, an insulating film 26, such as a silicon nitride film, is formed on the entire surface by plasma CVD (d). Thereafter, the entire surface is subjected to reactive ion etching to remove the silicon nitride film in the flat portion, and a side wall portion 26 of the insulating film is formed only on the side wall of the gate electrode forming portion 24 (.). Next, the active layer 22 is etched with a phosphoric acid etchant to form high concentration N-type In, Ga 1. As
A recess 24' is formed in the lower part of 23, and a photoresist 27 is used to form a gate electrode forming part 24 and a gate electrode forming part 24.
A single opening is formed on the ohmic electrode formation portion on both sides of the ohmic electrode, and a Schottky metal 28 (for example, Ti/Pt/Au) is formed on the entire surface.
is formed by normal evaporation (f). Thereafter, unnecessary gate metal on the photoresist 27 is removed by a lift-off method, leaving the gate metal 28 only in the opening. At this time, since the gate electrode forming part and the ohmic electrode forming part are separated by an insulating film, they do not come into contact with each other, so that the ohmic electrode 29 and the gate electrode 30 can be formed at the same time, and an FET can be formed (q). Above, 2
Although two embodiments have been described, T i /P of the gate metal
t/Au is the n-type layer aAs+niA I G a A
On a, there is a Schottky junction and no ohmic junction. However, jgGaAi has a narrow bandgap and is formed on heavily doped N-type InGaAs.
Ti/Pt/Au also forms an ohmic junction. Therefore, in the present invention, by using highly doped N-type InGaAs, an ohmic electrode and a Schottky gate electrode can be formed using one type of metal in the same process in a self-aligned manner.
また、第１の実施例では高濃度Ｎ型ＩｎｘＧａ１ ｘ
ＡｓのＸを０から順次増大させ０．７まで成長したのは
Ｇ ａ Ａ ｓとＩｎＧａＡｓ との格子不整合による
歪等を防ぐためであり、これは例えば、０ 、０．１．
０．２・・・０．７と段階的に行ってもよい。Furthermore, in the first embodiment, high concentration N-type InxGa1 x
The reason why X of As was increased sequentially from 0 to 0.7 was to prevent distortion due to lattice mismatch between GaAs and InGaAs.
It may be performed in steps of 0.2...0.7.
なお、本実施例ではゲート金属にＴｉ／Ｐｔ／Ａｕを用
いたがゲート金属はこれに限らず高濃度Ｎ型ＩｎＧａＡ
ｓ上でオーミック接合となるショットキ金属であれば何
でも良く、例としてＷ、Ｐｔ、Ａ４等があげられる。Note that although Ti/Pt/Au was used for the gate metal in this example, the gate metal is not limited to this.
Any Schottky metal can be used as long as it forms an ohmic contact on s, and examples include W, Pt, A4, etc.
発明の効果
本発明は、オーミック電極形成部に高濃度ｎ型層を用い
ることにより、オーミック電極とゲート電極を同一の電
極金属でしかも同時に形成することができプロセスが簡
略化される。またオーミック電極とゲート電極との距離
が短かくでき、ソース寄生抵抗の低減による特性の向上
や、素子面積の減少でき高集積化も容易に行うことがで
きる。Effects of the Invention In the present invention, by using a highly doped n-type layer in the ohmic electrode forming portion, the ohmic electrode and the gate electrode can be formed using the same electrode metal and at the same time, thereby simplifying the process. Furthermore, the distance between the ohmic electrode and the gate electrode can be shortened, characteristics can be improved by reducing source parasitic resistance, and the device area can be reduced, making it easy to achieve high integration.
第１図は本発明の第１の実施例における半導体装置の製
造方法を説明するだめの工程断面図、第２図は本発明の
第２の実施例における半導体装置の製造方法を説明する
ための工程断面図、第３図は従来の製造方法を説明する
ための工程断面図である。
１・・・・・・半絶縁性Ｇ ａ Ａ ｓ基板、６・・・
・・・Ｎ型Ｇ ａ Ａ ｓ層、６゛°パ・・高濃度ｎ型
ＩｎＧａＡｓ 層、７・・・・・・ゲート電極形成部
、７′・川・凹部、９・・・・・・フォトレジスト、１
０・・・・・・ショットキ金属。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名１−
４１とＢ柱Ｇｔｔ、１Ｉｓｌ、飯
温１図
９−−−フ坪しリＺト
（Ｏ−一−ショット〒虐シ１
２５−艶１盈膿
第２図
’２６；’ ２ｆ；’−１１１ｆ静第 ３ 図・FIG. 1 is a process sectional view for explaining the method of manufacturing a semiconductor device according to the first embodiment of the present invention, and FIG. 2 is a cross-sectional view for explaining the method of manufacturing the semiconductor device according to the second embodiment of the present invention. FIG. 3 is a process cross-sectional view for explaining a conventional manufacturing method. 1...Semi-insulating GaAs substrate, 6...
...N-type GaAs layer, 6゛°pa...high concentration n-type InGaAs layer, 7...gate electrode formation part, 7', river, recess, 9... Photoresist, 1
0... Schottky metal. Name of agent: Patent attorney Toshio Nakao and 1 other person1-
41 and B pillar Gtt, 1Isl, Ion 1 Figure 9 --- Futsuboshirito Z (O-1-shot 〒弒し 1 25-缝 1 终pus 2 Figure '26;'2f;'-111f Still Figure 3・
Claims (2)
板表面に高濃度Ｎ型Ｉｎ＿ｘＧａ＿１＿−＿ｘＡｓ層を
形成する工程と、ゲート電極形成部の前記高濃度Ｎ型Ｉ
ｎ＿ｘＧａ＿１＿−＿ｘＡｓ層を除去し前記Ｎ型ＧａＡ
ａ層を露出させる工程と、前記露出したＮ型ＧａＡｓ層
をエッチングし、高濃度Ｎ型Ｉｎ＿ｘＧａ＿１＿−＿ｘ
Ａｓ層下部に凹部を形成する工程と、前記ゲート電極形
成部および前記高濃度Ｎ型Ｉｎ＿ｘＧａ＿１＿−＿ｘＡ
ｓ層上にフォトレジストを用いて単一の開口部を形成す
る工程と、ショットキ金属を基板と垂直の方向から全面
に形成する工程と、前記フォトレジスト上のショットキ
金属を選択的に除去する工程を有してなる半導体装置の
製造方法。(1) A step of forming a high concentration N-type In_xGa_1_-_xAs layer on the surface of a compound semiconductor substrate whose surface layer is an N-type GaAs layer, and the step of forming a high concentration N-type I
The n_xGa_1_-_xAs layer is removed and the N-type GaA
A step of exposing the a layer and etching the exposed N-type GaAs layer to form a high concentration N-type In_xGa_1_-_x
A step of forming a concave portion in the lower part of the As layer, and forming the gate electrode forming portion and the high concentration N-type In_xGa_1_-_xA.
A step of forming a single opening on the S layer using a photoresist, a step of forming a Schottky metal on the entire surface in a direction perpendicular to the substrate, and a step of selectively removing the Schottky metal on the photoresist. A method for manufacturing a semiconductor device comprising:
ｘを０から順次増大させて形成する特許請求の範囲第１
項記載の半導体装置の製造方法。(2) High concentration N-type In_xGa_1_-_xAs layer,
Claim 1 formed by sequentially increasing x from 0
A method for manufacturing a semiconductor device according to section 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6294387A JPS63228762A (en) | 1987-03-18 | 1987-03-18 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6294387A JPS63228762A (en) | 1987-03-18 | 1987-03-18 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63228762A true JPS63228762A (en) | 1988-09-22 |
Family
ID=13214890
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6294387A Pending JPS63228762A (en) | 1987-03-18 | 1987-03-18 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63228762A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01120871A (en) * | 1987-11-05 | 1989-05-12 | Fujitsu Ltd | Semiconductor device |
| EP0394590A2 (en) * | 1989-04-27 | 1990-10-31 | Mitsubishi Denki Kabushiki Kaisha | Field effect transistors and method of making a field effect transistor |
| US5231040A (en) * | 1989-04-27 | 1993-07-27 | Mitsubishi Denki Kabushiki Kaisha | Method of making a field effect transistor |
-
1987
- 1987-03-18 JP JP6294387A patent/JPS63228762A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01120871A (en) * | 1987-11-05 | 1989-05-12 | Fujitsu Ltd | Semiconductor device |
| EP0394590A2 (en) * | 1989-04-27 | 1990-10-31 | Mitsubishi Denki Kabushiki Kaisha | Field effect transistors and method of making a field effect transistor |
| US5231040A (en) * | 1989-04-27 | 1993-07-27 | Mitsubishi Denki Kabushiki Kaisha | Method of making a field effect transistor |
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