JPH0523497B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a field effect transistor using high-speed electrons at a heterojunction interface.

[Conventional technology]

Field-effect transistors (hereinafter referred to as FETs), which use a high-speed two-dimensional electron channel at the heterointerface of GaAs and AlGaAs, are faster and have higher performance than FETs using GaAs, making them ideal for low-noise devices and high-speed ICs. Applications are being actively researched. This 2
In order to further improve the performance of FETs using dimensional electron channels, it is important to reduce the source resistance.
As an example of this, as shown in the cross-sectional structure in FIG.
The n ⁺ type impurity region 16 is formed in the IEEE Electron Device Letters No. EDL.
-Reported in Volume 5, Page 129 (1984). In Fig. 2, 5 is a high-resistance GaAs substrate, 11 is an undoped GaAs layer, 12 is an n-type AlGaAs layer, and 13 is a high-resistance GaAs substrate.
is a heat-resistant gate electrode, 14A is a source electrode, 1
4B is a drain electrode, and 3 is a two-dimensional electron channel.

The manufacturing process of this FET is to form a heat-resistant gate electrode 13 made of W or the like on an n-type AlGaAs layer 12, use this as a mask to implant, for example, Si ions as an n-type dopant, and perform heat treatment to form an n ⁺ -type impurity region. 1
After forming source and drain electrodes 14
A, 14B are formed.

[Problem that the invention seeks to solve]

However, in the conventional FET manufacturing method described above, since the thickness of the n-type AlGaAs layer 12 is as thin as several hundred angstroms (Å), high-dose ions are implanted into such a thin layer and the surface of the undoped GaAs layer 11. It is difficult to obtain low sheet resistance, that is, low source resistance.

In addition, if the implantation is deep to reduce the sheet resistance, the device with a short distance between the N ⁺ type impurity regions 16, which will become the source and drain regions, will be undoped.
As a result of the increase in the current injected into the GaAs layer 11, there is a problem in that so-called short channel effects such as an increase in drain conductance and a shift in threshold voltage occur. Furthermore, since high-temperature heat treatment is required for activation, there is also the problem that impurities diffuse into the undoped GaAs layer, causing deterioration of crystal quality.

Furthermore, since the heat-resistant gate electrode has a relatively high resistance and a large internal stress, the gate resistance may increase and the reliability may decrease. Further, although this gate electrode is usually formed by dry etching, it is still difficult to achieve submicronization and it is difficult to miniaturize the device.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a field effect transistor having a fine device structure that has low gate resistance and does not cause short channel effects.

[Means for solving problems]

The method for manufacturing a field effect transistor of the present invention includes:
After forming a high-purity first semiconductor layer on a high-resistance substrate, forming one or more second semiconductor layers containing impurities of one conductivity type on the first semiconductor layer;
forming a mask having openings for the source and drain regions on the second semiconductor layer; etching the second semiconductor layer in the openings;
forming a high concentration impurity layer of one conductivity type vertically on the exposed first semiconductor layer to be thicker than the mask and serving as source and drain regions; and forming an insulating film over the entire surface. After depositing, the insulating film is etched by an anisotropic etching method to leave the insulating film only on the side surfaces of the high concentration impurity layer, and the mask on the second semiconductor layer is removed to form a gate opening. and a step of depositing metal on the entire surface including the gate opening and then patterning it to form a gate electrode in the gate opening.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIGS. 1A to 1I are cross-sectional views of a semiconductor chip shown in the order of steps for explaining an embodiment of the present invention.

First, as shown in FIG. 1a, a first semiconductor layer 4 made of p-type GaAs with a carrier density of about 1×10 ¹⁴ /cm ³ and a thickness of 1 μm is formed by molecular beam epitaxy on a high-resistance GaAs substrate 5. form. This is followed by a 20 Å thick undoped Al _0.3 Ga _0.7 As layer, 100 Å thick.
Å n-type Al _0.3 Ga _0.7 As layer, 200 Å thick n-type Al _x
Ga _1-x As layer (x changes from 0.3 to 0)
Then, a second semiconductor layer 2 made of an n-type GaAs layer with a thickness of 200 Å is formed. Next, the entire surface is coated with a thickness of 3000Å.
After forming the SiO ₂ film, it is patterned to form a mask 1 in which the openings 10 of the source and drain regions are separated by 0.9 μm so that the current direction of the FET is <011>.

Next, as shown in FIG. 1b, the upper portions of the second semiconductor layer 2 and the first semiconductor layer 4 in the opening 10 of the mask 1 are etched.

Next, as shown in FIG. 1c, the first semiconductor layer 4 in the opening 10 is grown by hydride vapor phase epitaxy at a substrate temperature of 650° C. and a carrier concentration of 6×10 ^{18 .}
An n ⁺ -type GaAs layer 6 is grown with a thickness of ⁵⁰⁰⁰ Å and a thickness of 5000 Å. This n ⁺ type GaAs
Layer 6 is formed with substantially vertical sides.

Next, as shown in FIG. 1d, a silicon nitride film 7 with a thickness of about 2000 Å is formed over the entire surface by sputtering.

Next, as shown in FIG. 1e, the silicon nitride film 7 is etched by an anisotropic dry etching method using CF ₄ gas, leaving the silicon nitride film 7 only on the side surfaces of the n ⁺ type GaAs layer 6. At this time, since the portion of the two-dimensional electron channel 3 on the first semiconductor layer 4 is protected by the mask 1, the device characteristics will not deteriorate.

Next, as shown in FIG. 1f, the mask 1 made of SiO ₂ film is selectively removed using a hydrofluoric acid solution.
A gate opening 20 is formed.

Next, as shown in Figure 1g, the entire surface is coated with a thickness of 5000 mm.
After forming an Al film 8 having a thickness of .ANG., it is patterned to form a gate electrode 8A as shown in FIG. 1h.

Next, as shown in Figure 1i, AuGe public funds and
After depositing Ni, patterning and heat treatment are performed.
A source electrode 9A and a drain electrode 9B are formed on the n ⁺ type GaAs layer 6.

As described above, in this embodiment, since the n ⁺ type GaAs layer 6 which will become the source/drain region is grown on the etched first semiconductor layer 4, the source/drain region with a small sheet resistance can be obtained. Furthermore, since heat treatment for activation is not required, the crystal quality of the first semiconductor layer 4 does not deteriorate. Furthermore, since the gate electrode 8A is formed in a self-aligned manner after providing the n ⁺ type GaAs layer 6 as the source and drain regions,
The metal forming the gate electrode is not limited to one having heat resistance. Therefore, it has a gate electrode made of a metal with low resistivity and has excellent breakdown voltage between the gate and source and between the gate and drain.
FETs can be manufactured. In addition, since a gate electrode with a smaller area than conventional gate electrodes can be formed by self-alignment, the input capacitance is reduced.
The high-speed and high-frequency characteristics of the FET will be improved.

In the above embodiment, a case has been described in which a GaAs layer or the like containing n-type impurities is used as the second semiconductor layer, but one or more semiconductor layers containing p-type impurities may also be used.

〔Effect of the invention〕

As explained above, in the present invention, after forming a high concentration impurity layer of one conductivity type which becomes a source/drain region on an etched first semiconductor layer, a gate electrode insulated from this high concentration impurity layer is formed. Forming by matching has the advantage that it is possible to manufacture a field effect transistor having a fine device structure with low gate resistance and without short channel effect.

[Brief explanation of drawings]

Figures 1 a to i are cross-sectional views of a semiconductor chip shown in the order of manufacturing steps to explain an embodiment of the present invention, and Figure 2 is a cross-sectional view of a semiconductor chip to explain a conventional FET manufacturing method. be. 1... Mask, 2... Second semiconductor layer, 3...
two-dimensional electron channel, 4...first semiconductor layer, 5
... GaAs substrate, 6 ... N ⁺ type GaAs layer, 7 ... silicon nitride film, 8 ... Al film, 8A ... gate electrode, 9A ... source electrode, 9B ... drain electrode, 10 ... opening , 11...Undoped GaAs
layer, 12... n-type AlGaAs layer, 13... gate electrode, 20... gate opening.

Claims (1)

[Claims] 1. After forming a high-purity first semiconductor layer on a high-resistance substrate, forming one or more second semiconductor layers containing impurities of one conductivity type on the first semiconductor layer; forming a mask having openings for source and drain regions on the semiconductor layer; etching the second semiconductor layer in the openings to expose the first semiconductor layer; A process of vertically forming a high concentration impurity layer of one conductivity type to be the source and drain regions on the semiconductor layer thicker than the mask, and after depositing an insulating film on the entire surface, the insulating film is removed by an anisotropic etching method. a step of etching to leave an insulating film only on the side surfaces of the high concentration impurity layer; a step of removing the mask on the second semiconductor layer to form a gate opening; and a step of etching a metal layer over the entire surface including the gate opening. 1. A method for manufacturing a field effect transistor, comprising the step of depositing and patterning to form a gate electrode in a gate opening.