JP2591162B2 - Method of manufacturing semiconductor device and semiconductor device manufactured thereby - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor device having a semiconductor layer and a metal gate forming a Schottky barrier. The present invention relates to a method for improving a noise figure and an operation speed. A first step of forming
A second step of forming a window exposing the first semiconductor layer in the insulating layer; and making a Schottky contact with the exposed first semiconductor layer in the window and extending over the insulating layer. A third step of forming a metal electrode having an end; and a fourth step of removing the insulating layer under the extending end of the metal electrode to expose the first semiconductor layer. Forming a protective film on the surface of the metal electrode including the extending end portion and the surface of the first semiconductor layer exposed under the end portion following the surface. Leaving a space between the extending end of the first semiconductor layer and the first semiconductor layer and exposing the first semiconductor layer in the window.
Forming a first semiconductor layer and a gate electrode which makes Schottky contact with one surface of the first semiconductor layer, the method comprising: a fifth step of protecting a surface of the first semiconductor layer. A metal electrode, a part of the metal electrode, extending from the top of the metal electrode to both sides on the surface of the first semiconductor layer, and the metal electrode in a direction in which the end extends. A source electrode and a drain electrode which are arranged so as to be opposed to each other across the surface of the first semiconductor layer and are in contact with the surface of the metal electrode including the end and a region immediately below the end; An insulating protective film that covers the surface of the first semiconductor layer and the source electrode and the drain electrode that follow the surface of the first semiconductor layer. A first semiconductor layer and the first semiconductor layer; A space surrounded by the source electrode and a space surrounded by the metal electrode, the first semiconductor layer, and the drain electrode, each surface of which is covered by the protective film, is a gap. It is configured like a semiconductor device.

[Industrial applications]

The present invention relates to a semiconductor device having a semiconductor layer and a metal gate forming a Schottky barrier, and more particularly to a method of manufacturing a HEMT (High Electron Mobility Transistor).

[Conventional technology]

MESFETs (metal-semiconductor field effect transistors) and HEMTs have been put to practical use using compound semiconductors centered on GaAs. These are characterized by a high switching speed utilizing high electron mobility of a compound semiconductor such as GaAs, and have a structure including a semiconductor layer and a metal gate forming a Schottky barrier. In particular, HEMTs that use a two-dimensional electron gas as the carrier
The electron mobility is higher than that of the ESFET, so the noise figure is smaller and the operation speed is higher. In order to effectively exhibit such characteristics, the intrinsic function, that is, the transconductance (gm) is increased, and the parasitic capacitance (Cg
It is important to reduce s, Cgd).

[Problems to be solved by the invention]

In the conventional MESFET or HEMT, there is a problem that a characteristic defect occurs due to an insulating layer made of, for example, SiO ₂ formed between a gate electrode and a semiconductor layer serving as a contact layer of a source / drain region. Hereinafter, the above-mentioned problems will be described using a conventional HEMT as an example.

FIG. 4 is a cross-sectional view of a main part of the structure of a conventional HEMT, in which an intrinsic GaAs (i-GaAs) layer 1 serving as an electron transit layer and an n ⁺ -Al GaAs layer 2 serving as an electron supply layer are laminated. , n ⁺ −Al GaAs
A gate electrode 8 that is in Schottky contact with layer 2 is formed. On both sides of the gate electrode 8, source / drain electrodes 10 made of a metal layer that makes ohmic contact with the n ⁺ -GaAs layer 3 that becomes a contact layer (or a cap layer) that contacts the source / drain regions are formed. I have.

As shown in FIG. 4, n ⁺ -Ga As layer 3 to provided the opening, i.e., the recess portion of the n ⁺ -Ga As layer 3, the sidewall layer 7 made of SiO ₂ is present. This SiO ₂ side wall layer 7
As shown in FIG. 5A, the gate electrode 8 is patterned using the resist pattern 9 as a mask, and the SiO ₂ layer 4 exposed at this time is applied to the gate electrode 8 as shown in FIG. 5B. 8 as a mask to remove n ⁺ -Ga A
When the s layer 3 is exposed, the SiO ₂ layer remains immediately below the gate electrode 8. The presence of the SiO ₂ side wall layer 7 causes the following problem.

Gate electrode 8, n ⁺ -Ga As layer 3 and n ⁺ -Al GaAs layer 2
In particular, the n ⁺ −Ga As layer 3 which is a main component of the gate-drain capacitance (C _gd ) greatly affects the speed of the transistor operation at the three terminals. On the continuous surface, the stress due to the lattice matching and the difference in the coefficient of thermal expansion between the SiO ₂ side wall surface 7 and the n ⁺ -Al GaAs layer 2 and the n ⁺ -Ga As layer 3 is concentrated. , The reverse breakdown voltage between the gate and the source or between the gate and the drain is likely to decrease.
A large variation occurs in the reverse breakdown voltage of a large number of elements formed on the same wafer. A large number of microcracks are generated in the SiO ₂ side wall layer 7 in contact with the recessed portion of the n ⁺ -GaAs layer 3 due to the stress concentration. , Electrostatic breakdown easily occurs. Therefore, an object of the present invention, which causes a decrease in the source-drain breakdown voltage, is to solve the above-described problems in the conventional structure and to improve the high-frequency operation characteristics and the DC breakdown voltage of the transistor.

[Means for solving the problem]

The object is to provide a first step of forming an insulating layer on a first semiconductor layer, a second step of forming a window exposing the first semiconductor layer in the insulating layer, A third step of forming a metal electrode having Schottky contact with the exposed first semiconductor layer and having an end extending over the insulating layer; and forming a metal electrode under the extending end of the metal electrode. A fourth step of removing the existing insulating layer to expose the first semiconductor layer; and a step of exposing the surface of the metal electrode including the extending end and the surface exposed below the end. Forming a protective film on the surface of the first semiconductor layer following these surfaces, leaving a space between the extending end of the metal electrode and the first semiconductor layer and exposing in the window. A method of manufacturing a semiconductor device or a first semiconductor layer, the method comprising: protecting a surface of the first semiconductor layer. And a metal electrode constituting the gate electrode of Schottky contact with one surface of the first semiconductor layer, said first on both sides from the top of the metal electrode to a portion of said metal electrode
An end extending on the surface of the semiconductor layer, and a source electrode disposed in contact with the surface of the first semiconductor layer so as to face each other with the metal electrode interposed therebetween in the direction in which the end extends. And the drain electrode, and the surface of the metal electrode including the end and the surface of the first semiconductor layer exposed in the region immediately below the end, and the surfaces of the source electrode and the drain electrode. An insulating protective film, wherein a space surrounded by the metal electrode, the first semiconductor layer, and the source electrode, each surface of which is covered by the protective film, and each surface is covered by the protective film. This is achieved by a semiconductor device, wherein a space surrounded by the metal electrode, the first semiconductor layer, and the drain electrode is a gap.

(Operation)

By removing the insulating layer between the recessed portion of the n ⁺ -GaAs layer 3 and the gate electrode 8 so as not to fill the gap with an insulator, the parasitic capacitance between the gate and the source and between the gate and the drain is reduced. As a result, the high frequency characteristics are improved. Further, the recessed portion of the n ⁺ -Ga As layer 3, the conventional SiO ₂
Since a thick insulating layer such as the side wall layer 7 does not contact, stress concentration and microcracks in the insulating layer do not occur, and there is no reduction in breakdown voltage or electrostatic breakdown of the insulating layer due to stress concentration or microcracks.

Embodiment An embodiment of the present invention will be described below with reference to the drawings. In the following drawings, the same parts as those in the already-described drawings are denoted by the same reference numerals.

FIG. 1 is a cross-sectional view of a main part showing the structure of an HEMT according to the present invention. As in the conventional structure shown in FIG. 4, i-GaAs layer 1 serving as an electron transit layer and n serving as an electron supply layer are provided. ^{A +} -Al GaAs layer 2 is laminated, and a gate electrode 8 made of a metal layer which is Schottky connected to the n ⁺ -Al GaAs layer 2 is formed. On both sides of the gate electrode 8, and n ⁺ -Ga As layer 3 serving as a cap layer in contact with the source / drain region is formed, n ⁺
A source / drain electrode 10 made of a metal layer in ohmic contact with the GaAs layer 3;

In FIG. 1, an opening provided in the n ⁺ -Ga As layer 3 is shown.
That is, there is no insulating layer burying the recessed portion of the n ⁺ -Ga As layer 3, that is, the side wall layer 7 in FIG. An air gap 11 exists between the gate electrode 8 and the n ⁺ -Ga As layer 3. Then, the exposed surface of the n ⁺ -Ga As layer 3 and the gate electrode 8
The surface and the surface of the source / drain electrode 10 are made of, for example, Si ₃ N
It is covered by a thin insulating layer 12 of ₄ . As a result, the parasitic capacitance (Cgs and Cgd) between the gate and the source and between the gate and the drain is reduced, the high-frequency characteristics can be improved, and the DC breakdown voltage of the element is improved. Furthermore, since the insulating layer 12 has a small thickness, microcracks are unlikely to occur even when subjected to stress, and the exposed surface of the n ⁺ -Al GaAs layer 2 is protected, and the stability of the device characteristics is guaranteed.

FIG. 2 is a sectional view of a main part in a manufacturing process of the HEMT according to the present invention. First, referring to FIG. 1A, on a substrate on which an n ⁺ -Al GaAs layer 2 and an n ⁺ -Ga As layer 3 are sequentially formed on an i-GaAs layer 1, a layer having a thickness of about 0.3 μm is formed. After depositing a SiO ₂ layer 4, a resist is coated on the SiO ₂ layer 4. An opening corresponding to a gate pattern having a gate length of about 0.4 μm is formed in this resist layer (not shown) using a known lithography technique. Using this resist layer as a mask,
The SiO ₂ layer 4 exposed in the opening is removed by etching. Thus, the opening 5 is formed in the SiO ₂ layer 4.

The resist layer is removed, and then, using the SiO ₂ layer 4 as a mask, the n ⁺ -Ga As layer 3 exposed in the opening 5 is subjected to an anisotropic etching method, for example, CCl ₂ F ₂ (CFC 12). Is selectively removed by a well-known reactive-on-etching (RIE) method using as an etchant. As a result, a recess 6 is formed in the n ⁺ -Ga As layer 3 as shown.

Next, as shown in FIG. 2B, n ⁺ -Al Ga exposed in the SiO ₂ layer 4 and the recess 6 is formed by using a well-known CVD method.
After depositing a SiO ₂ layer 7 ₀ a thickness of about 0.3μm on the As layer 2,
For example, a well-known R using CF ₄ (carbon tetrafluoride) as an etchant
The IE method for SiO ₂ layer 7 _0, subjected to so-called etch back. Thus with n ⁺ -Al GaAs layer 2 is exposed again, as shown in FIG. 2 (c), the side surfaces of the n ⁺ -Ga As layer 3 in the recessed portion 6, the side wall made of the SiO ₂ layer 7 ₀ Layer 7 remains. Substantially only the SiO ₂ layer 4 remains on the n ⁺ -Ga As layer 3 other than the recess 6.

Next, as shown in FIG. 2 (d), a metal layer 8 ₀ on n ⁺ -Al GaAs layer 2 exposed on the upper and the recessed portion 6 SiO ₂ layer 4 and the sidewall layer 7. Metal layer 8 _0, tungsten silicide (WSi) layer having a thickness of about 0.2 m, a titanium (Ti) layer having a thickness of about 0.02 [mu] m, and, formed by sequentially depositing a gold (Au) layer having a thickness of about 0.4μm It has a laminated structure and is formed by a well-known sputtering method.

Then, resist is applied to the metal layer 8 _0, the known lithography technique, as shown in FIG. 2 (e), a resist pattern 9 which covers the recess portion 6 (commonly known as over gate), the resist pattern 9 as a mask
The metal layer 8 ₀ to exposed is removed by a known RIE method. In this manner, the gate electrode 8 made of a metal layer 8 ₀ is formed.

Next, the SiO ₂ layer 4 is removed by etching using a buffered hydrofluoric acid solution. In the present invention, the SiO ₂ just below the gate electrode 8 is used.
The sidewall layer 7 is also removed at the same time. As a result, as shown in FIG. 2 (f), an n ⁺ -Ga As layer 3 is exposed, and an n ⁺ -Al GaAs layer is provided between the gate electrode 8 and the n ⁺ -Ga As layer 3. 2 comes out.

The resist pattern 9 is removed, and then the gate electrode 8 is removed.
Using a mask as a mask, a metal layer in ohmic contact with the n ⁺ -Ga As layer 3 is deposited and patterned, and FIG. 2 (g)
A source / drain electrode 10 is formed as shown in FIG. The metal layer constituting the source / drain electrode 10 has a thickness of about
0.05μm gold germanium (AuGe) layer, about 0.01μm thick
Nickel (Ni) layer and gold (Au) about 0.2μm thick
It has a laminated structure in which layers are sequentially deposited, and is formed by a well-known vacuum deposition method.

After the above, the exposed surface of the n ⁺ -Ga As layer 3 and the gate electrode 8
On the surface and the surface of the source / drain electrode 10, for example, Si ₃ N
The insulating layer 12 having a thickness of 200 to 300 ° made of ₄ is formed, and the HEMT according to the present invention shown in FIG. 1 is formed. The formation of the insulating layer 12 is performed, for example, by chemical vapor deposition (CV
Perform at low temperature using method D). UV-excited CVD is another CV
An element having stable current characteristics and high-frequency characteristics without thermal damage or ion bombardment of the compound semiconductor crystal as in the method D can be obtained.

In the above-mentioned HEMT of the present invention, since the SiO ₂ side wall layer does not exist directly under the gate electrode 8, the drain feedback capacitance is increased from the conventional 0.07 (pF / 200 μm) to 0.02.
It was reduced to 5 (pF / 200 μm). The change in the drain feedback capacitance due to the provision of the Si ₃ N ₄ insulating layer 12 is 0.025 (pF / 200μ
m) to 0.03 (pF / 200 μm), which is almost the same. As a result, as shown in FIG. 3, the noise figure (NF) at the measurement frequency f = 12 GHz was 0.2.
It decreased by more than dB, and the incidental gain (G _as ) improved by more than 2 dB. In the figure, * marks indicate measured values for the HEMT having the conventional structure having the sidewall layer 7, and # marks indicate measured values for the HEMT according to the present invention.

Since there is no SiO ₂ side wall layer, the stress concentration at the discontinuous surface of the recessed portion of the n ⁺ -Ga As layer 3 is reduced. As a result, the reverse breakdown voltage (V _gso ) between the gate and the source and the reverse voltage between the gate and the drain are reduced. Direction withstand voltage (V _gdo ) has increased from 4 to 6 V in the past to 8 to 11 V.

As a result of avoiding the problem of electrostatic breakdown caused by microcracks generated in the SiO ₂ side wall layer, the distribution of the breakdown voltage between the source and the drain has been increased from the conventional 20 to 30 V to 50 to 60 V.

In the above description, the HEMT has been described as an example, but it goes without saying that the present invention can be applied to other semiconductor devices having a metal gate forming a Schottky barrier in a semiconductor layer.

〔The invention's effect〕

According to the present invention, a MESF having a Schottky contact gate
It is possible to improve high-frequency characteristics such as ET and HEMT, gate withstand voltage and source / drain withstand voltage, improve reliability during operation, and reduce variations in characteristics in the manufacture of these semiconductor devices and improve manufacturing yield. Has the effect of doing

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a main part of a structure of a HEMT according to the present invention, FIG. 2 is a cross-sectional view of a main part in a manufacturing process of the HEMT according to the present invention, and FIG. FIG. 4 is a cross-sectional view of a main part of the structure of the conventional HEMT, and FIG. 5 is a cross-sectional view of the main part in a manufacturing process of the conventional HEMT. In the figure, 1 is i-GaAs layer, 2 n ⁺ -Al GaAs layer, 3 n ⁺ -Ga As layer, 4 and 7 ₀ SiO ₂ layer, 5 is an opening, 6 is recessed portion, 7 sidewall layer , 8 denotes a gate electrode, 8 ₀ metal layer, 9 resist pattern, 10 the source / drain electrodes, is 11 voids, 12 denotes an insulating layer.

Claims (4)

(57) [Claims] A first insulating layer formed on the first semiconductor layer;
And a second step of forming a window exposing the first semiconductor layer in the insulating layer; and making a Schottky contact with the first semiconductor layer exposed in the window and on the insulating layer. A third step of forming a metal electrode having an end extending to the first step; and removing the insulating layer under the extending end of the metal electrode to expose the first semiconductor layer. Forming a protective film on the surface of the metal electrode including the extending end and the surface of the first semiconductor layer exposed under the end, following the surfaces. A fifth step of leaving a space between the extending end of the metal electrode and the first semiconductor layer and protecting the surface of the first semiconductor layer exposed below the end. And a method of manufacturing a semiconductor device. 2. A step of forming a second semiconductor layer having an opening for exposing the first semiconductor layer on the first semiconductor layer prior to the first step; Forming the insulating layer so as to extend from the first semiconductor layer to the second semiconductor layer, and exposing the first semiconductor layer in the opening. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising: an insulating layer second step of forming the window in the insulating layer. 3. A first semiconductor layer, a metal electrode forming a gate electrode that makes Schottky contact with one surface of the first semiconductor layer, and a part of the metal electrode, on both sides from the top of the metal electrode. An end extending on the surface of the first semiconductor layer; and an end extending in a direction in which the end extends, being opposed to each other across the metal electrode and in contact with the surface of the first semiconductor layer. The source and drain electrodes, the surface of the metal electrode including the end and the surface of the first semiconductor layer and the surface of the source and drain electrodes exposed in a region immediately below the end. An insulating protective film covering the metal electrode, the first semiconductor layer, and the source electrode, each surface of which is covered by the protective film. Covered by a protective film Wherein a space surrounded by the metal electrode and the first semiconductor layer and the drain electrode is void. 4. The semiconductor device according to claim 3, wherein a second semiconductor layer is interposed between said source and drain electrodes and said first semiconductor layer.