JPH0411741A - Field-effect transistor and its manufacture - Google Patents

Abstract

PURPOSE:To prevent a parasitic capacitance from being increased at a gate electrode and to improve a gain by a method wherein, at a passivation film with which the gate electrode of a mashroom structure is covered, voids are formed at the lower part of eaves of the gate electrode. CONSTITUTION:A first insulating film 2 is formed on a GaAs substrate 1; after that, an opening part 3 is formed in a position to be used as a gate region in the film 2. Then, a resist layer 4 is coated; the resist corresponding to the lower side of eaves of a mushroom gate is left on both sides of the inside of the opening part 3 in the film 2; an opening part 5 is formed between them; after that, a recess part 6 at a desired depth is formed by making use of the resist 4 as a mask. Then, a gate metal is vapor-deposited; it is patterned in the upper-part width of the mushroom gate; after that, a gate electrode 7 of a mushroom structure is formed. When a second insulating film 8 is formed, voids 9 are produced at the lower part of eaves of the electrode 7 of the mushroom structure. Thereby, since the permittivity of the air is smaller than that of the film 8, it is possible to prevent a parasitic capacitance from being increased at the electrode 7 and the improve a gain.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a field effect transistor, and particularly to a method for manufacturing a field effect transistor having a pine mushroom gate structure.

[Conventional technology]

In general, gallium arsenide field effect transistors (CaAsFET) for low-noise amplification and field effect transistors (HEMT, MODFET) having an aluminum gallium arsenide/gallium arsenide heterojunction.

In order to improve the microwave performance of HJ-FET (hereinafter referred to as HJ-FET in the main text), the gate length (
Efforts are being made to shorten Lg) and reduce source resistance (Rs). In particular, shortening the gate length is very effective, and EB
(Electron beam) 0.25 to 0.3 μm depending on drawing method etc.
Elements with gate lengths of about 300 yen have been put into practical use. However, due to this shortened gate length, the gate input capacity (Cgs
) is reduced, which on the other hand results in an increase in the gate resistance (Rg).

For this reason, in the past, efforts have been made to reduce gate resistance by applying a pine mushroom gate structure.

FIG. 2 shows an example, in which 1 is a CaAs substrate, 7 is a gate electrode provided in the recessed part 6, 10.11 is a source,
Each drain electrode 8 is a passivation film made of SiN or SiO□.

In this way, by forming the gate electrode 7 into a manshroom structure, the gate length is shortened and the gate resistance is reduced.

Although there are several methods of forming this pine mushroom gate, it is thought that formation by a resist lift-off method using an EB lithography method is advantageous in controlling the gate length.

[Problem to be solved by the invention]

In the conventional structure described above, when the passivation film 8 provided to ensure the reliability is formed to a sufficient thickness (usually 1000 Å or more) to ensure the reliability, the underside of the eaves of the gate electrode 7 is The invaded passivation film 8 causes an increase in parasitic capacitance, resulting in a decrease in microwave characteristics, especially gain. For example, gate length Lg30.3μm,
In a device with a gate width Wg = 200 am, a normal rectangular gate has a gate-drain capacitance Cgd of 0.015p.
Cgd increases to about 0.025 pF with respect to
The degree decreases. Further, in order to prevent an increase in parasitic capacitance, the passivation film 8 may not be formed, but this may cause contamination, deterioration, etc. in the reliability of the elements and during the wafer manufacturing process.

An object of the present invention is to provide a field effect transistor that prevents increase in parasitic capacitance and improves gain, and a method for manufacturing the same.

[Means for Solving the Problems] The field effect transistor of the present invention has a structure in which holes are provided under the eaves of the gate electrode in a padded resin film that covers a gate electrode with a mushroom structure provided on a GaAs substrate.

Further, the method for manufacturing a field effect transistor of the present invention includes G
a step of forming a first insulating film on the aA-s substrate, a step of providing an opening area in the first insulating film, and forming an opening at the same position as the opening while leaving a part of the opening area within the opening area. A step of forming a resist having a gate electrode having a pine mushroom structure by using the opening to deposit a gate metal on the GaAs substrate, removing the resist and using a lift-off method, and passivating the entire surface. The method includes a step of forming a second insulating film as a film by a deposition method.

[Effect]

According to the field effect transistor of the present invention, the parasitic capacitance of the gate electrode is reduced because holes are present in the passivation film under the eaves of the gate electrode.

〔Example] Next, the present invention will be explained with reference to the drawings.

FIGS. 1(a) to 1(l) are cross-sectional views showing an embodiment of the present invention in the order of manufacturing steps, and in particular, are views showing a method of manufacturing a gate electrode portion. This manufacturing process will be explained below.

First, as shown in FIG. 1(a), a first insulating film 2, for example SiO2, is deposited on a GaAs substrate 1 after forming an active region.
Form a relatively thick film (3000 people). Then,
An opening 3 is formed in the insulating film 2 at a position that will be the gate N region, the opening 3 being approximately the same width as the upper part of the mushroom gate.

Next, as shown in FIG. 1(b), a PMMA-based resist layer 4 is applied, and the resist 4 is patterned by the EB direct writing method. In this patterning, resists corresponding to the underside of the eaves of the mats/I/-Lay'-) are left on both sides of the inner surface of the opening 3 of the insulating film 2, and an opening 5 is formed between them.

In this case, since the EB drawing method is used, the alignment accuracy is high.

Thereafter, as shown in FIG. 1C, the surface of the GaAs substrate 1 is etched using the resist 4 as a mask to form a recess 6 of a desired depth. Then, as a gate metal, for example, Ti--Al is deposited by 200 to 4000 people and patterned to have the upper width of the pine mushroom gate. Thereafter, the resist 4 is removed and a gate electrode 7 having a mushroom structure is formed by a lift-off method.

In addition, after this, the sauce as shown in FIG.

Each drain electrode and its contact area are formed.
Since this method and the electrodes formed are the same as before, their explanation will be omitted.

Then, as shown in FIG. 1(d), a second insulating film 8 as a passivation film, for example, a SiN film by a deposition method such as plasma CVD, is formed over the entire surface to a thickness of 1000 nm. At this time, holes 9 are generated under the eaves of the gate electrode 7 having a mushroom structure.

The reason why the holes 9 are formed is that the eaves of the first insulating film 2 and the gate electrode 7 are very close to each other, and the first insulating film 2
This is because the second insulating film 8 contacts the tip of the eaves on the first insulating film 2 when the second insulating film 8 is grown. For example, in the case of this embodiment, about 1000 SiN films are grown as the second insulating film 8, but about 400 to 500 SiN films are grown under the eaves of the gate electrode 7.
Only about 0.00 people grow, and holes 9 are formed during this time.

In the field-effect transistor configured in this way, the lower part of the eaves of the gate electrode 7 is not filled with the second insulating film 8, but the holes 9 are present, so that the dielectric constant of the air is equal to the second insulating film 8. Since it is smaller than that of the insulating film 8, an increase in parasitic capacitance in the gate electrode 7 can be prevented.

Further, in this manufacturing method, if the first insulating film 2 is formed in advance in the vicinity of the gate electrode 7, the subsequent steps can be performed in the same manner as in the conventional method, and the manufacturing can be easily performed.

In this field effect transistor, even if there is a hole 9 under the eaves of the gate electrode 7, the recessed part 6 is protected by the second insulating film 8, so that reliability and wafer process 7 assembly process may be affected. Problems such as contamination and deterioration will not occur.

〔Effect of the invention〕

As explained above, the field effect transistor of the present invention has
Since holes are provided in the passivation film under the eaves of the gate electrode of the pine mushroom structure, the dielectric constant in this part is lowered, parasitic capacitance in the gate electrode is suppressed, and gain can be improved.

Furthermore, compared to conventional manufacturing methods, the method for manufacturing a field effect transistor of the present invention is characterized in that the first
Since it is only necessary to form an insulating film in advance, the conventional process can be used as is, and the field effect transistor of the present invention can be manufactured easily.

[Brief explanation of drawings]

FIGS. 1(a) to d) are cross-sectional views showing the field effect transistor of the present invention in the order of manufacturing steps, and FIG. 2 is a cross-sectional view of a conventional field effect transistor. DESCRIPTION OF SYMBOLS 1... GaAs substrate, 2... First insulating film, 3...
・Opening, 4...Resist, 5...Opening, 6...
- Recessed part, 7... Gate electrode, 8... Second insulating film (passivation film), 9... Hole, 10.11
・・・Source, Figure 1

Claims (1)

[Claims] 1. In a field effect transistor in which a mushroom-structured gate electrode is formed on a GaAs substrate and this gate electrode is covered with a passivation film, the passivation film has holes formed under the eaves of the gate electrode. A field effect transistor characterized by having: 2. Forming a first insulating film on the GaAs substrate;
A step of providing an opening region in the first insulating film, a step of forming a resist having an opening at the same position as the opening while leaving a part of the resist in the opening region, and using this opening to The method includes the steps of depositing a gate metal on the substrate, removing the resist, and forming a gate electrode with a mushroom structure using a lift-off method, and forming a second insulating film as a passivation film on the entire surface using a deposition method. A method of manufacturing a field effect transistor, characterized in that: