KR100262941B1 - Method for forming t-type gate of semiconductor device - Google Patents

Abstract

The present invention relates to the field of semiconductor technology, and more particularly, to a method of forming a fine T-type gate of a compound semiconductor device, and to a method of forming a fine T-type gate of a compound semiconductor device capable of easily forming a fine T-type gate in a stable structure. The purpose is to provide. To this end, in the present invention, the deposition temperature is gradually changed during deposition of a sacrificial film (eg, silicon nitride film) for forming a T-type gate to deposit a multilayer thin film, and thereafter, the etching rate difference between layers according to the deposition temperature during wet etching. In addition, a stepped fine T-type gate having a stable structure is formed by using a flow characteristic in which the electron beam resist pattern flows down at a high temperature. That is, the present invention forms a stepped structure where the gate bridge and the head meet each other to prevent the gate bridge and the head from breaking, and because the insulating film supports the gate bridge from both sides, the fine gate bridge and the large T-type are large. The gate electrode can be manufactured without lifting.

Description

Method of forming fine tee gate of compound semiconductor device

TECHNICAL FIELD The present invention relates to the field of semiconductor technology, and more particularly, to a method of forming a fine T-type gate of a compound semiconductor device.

In general, reducing the gate length is most effective for fabricating high performance transistors. In other words, reducing the gate length not only increases the blocking frequency of the transistor, but also improves various related characteristics.

However, as the gate length decreases, the gate has a T-shape because the cross-sectional area of the metal decreases and the resistance and noise characteristics deteriorate. Such T-gates can be manufactured by various methods, and many examples have been reported so far. All of them mainly use two- or three-layer resists using electron beam (E-beam) lithography with excellent resolution. In other words, an electron beam lithography process creates an inverted triangular T-shaped resist shape and deposits metal thereon and lifts it off, or creates a temporary gate to create a fine gate-shaped groove, and then widens it again. An upper resist pattern is formed to deposit a metal and lift-off to fabricate a T-type gate electrode. However, both of these methods are effective for making T-type gates, but making fine gates is not easy.

Recently, in order to form a fine gate pattern, an acceleration voltage is increased to 100 kV. If the acceleration voltage is increased, a fine gate pattern can be formed. However, since the ratio of the gate length to the height of the gate bridge portion is relatively increased during the deposition of the gate metal, the gate bridge and the head are broken when the metal is deposited.

Hereinafter, a typical representative T-type gate fabrication technique will be considered with reference to the accompanying drawings.

1A to 1E illustrate a manufacturing process of a field effect compound semiconductor device (eg, a gallium arsenide high electron mobility transistor (HEMT) and a metal-semiconductor field effect transistor (MESFET)) according to the prior art. The production process is briefly described below.

First, referring to FIG. 1A, reference numeral 10 denotes a semi-insulating gallium arsenide substrate, 11 denotes a buffer layer, 12 denotes an AlGaAs / GaAa superlattice buffer layer, 13 denotes a channel layer, and 14 denotes a spacer layer. '15' represents a Schottky layer, '16' represents an N-type GaAs ohmic layer, and '17' represents a photoresist pattern for forming ohmic electrodes of a source electrode and a drain electrode.

Next, referring to FIG. 1B, the photoresist layer pattern 17 is formed as described above, and then AuGe in an alloy form is formed to a thickness of 1000 to 2000 kPa and Ni to 400 to 1000 kPa in a heat resistant heating vacuum evaporator. After deposition, Au is sequentially deposited to form an ohmic metal layer 18 composed of AuGe / Ni / Au.

Subsequently, the ohmic metal layer 18 is deposited as shown in FIG. 1C, and then the photoresist pattern 17 is removed by a lift-off method to form the source electrode and the drain electrode 19, and then the temperature is about 430 ° C. Heat treatment is performed for about 20 seconds at.

Subsequently, as shown in FIG. 1D, a polymethyl methacrylate (PMMA) / P (MMA-MAA) photosensitive film pattern 20 for forming a T-type gate of the field-effect compound semiconductor device is formed, and the gate recess is formed by dry etching. (recess)

Next, as shown in FIG. 1E, when the metal layer composed of Ti / Pt / Au is deposited and the photoresist pattern 20 is removed by a lift-off method, an electric field effect of HEMT, MESFET, etc. having a fine T-type gate 21 is formed. A type compound semiconductor device is manufactured.

However, the field effect compound semiconductor device fabricated by the above method adopts an epitaxial layer structure composed of a single layer, so that the ohmic resistance is relatively high and there is no etch-stop layer. There is a problem that is difficult to control. The one-step gate recess method also makes the gate recess structure symmetrical and leaves an ohmic layer near the drain. As a result, the breakdown voltage between the gate and the drain is decreased, and the parasitic capacitance C _gd between the gate and the drain is increased, thereby deteriorating the high frequency characteristics of the compound semiconductor device.

2A through 2H illustrate a manufacturing process of another field effect compound semiconductor device according to the related art, and a brief description thereof will be given below.

First, as shown in FIG. 2A, an ohmic layer 31 and a primary metal layer 32 are formed on a substrate 30.

Subsequently, as shown in FIG. 2B, the PMMA resist 33 is applied to the entire structure and soft-dried. Then, as shown in FIG. 2C, the sensitivity to the electron beam is relatively higher than that on the PMMA resist 33. After applying the MMA-MAA copolymer (34) (34) is also softened and dried. Subsequently, as shown in FIG. 2D, the PMMA resist 35 is once again applied over the entire structure to form a three-layer resist structure.

Then, after performing electron beam exposure as shown in FIG. 2E, the resists 35, 34, 33 are developed and washed to form a T-type resist profile as shown in FIG. 2F.

Next, as shown in FIG. 2G, the substrate 30 is recessed and the gate metal 36 is deposited.

Finally, as shown in FIG. 2H, the remaining resists 35, 34, 33 are removed to fabricate the compound semiconductor device having the T-type gate metal 36a.

However, the above technique has a problem in that it is difficult to form a fine T-type gate due to the proximity effect during electron beam exposure by using three layers of resists.

An object of the present invention is to provide a method for forming a fine T-type gate of a compound semiconductor device capable of easily forming a fine T-type gate in a stable structure.

1a to 1e is a process diagram of a field effect compound semiconductor device manufacturing according to the prior art.

Figure 2a to 2h is a field effect type compound semiconductor device manufacturing process diagram according to another prior art.

3a to 3n is a process diagram of manufacturing a field effect compound semiconductor device according to an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

40: GaAs substrate 41: ohmic metal layer

42: primary metal layer 43: silicon oxide layer (silicon dioxde layer)

44, 45, 46 silicon nitride film 47 aluminum film

48: PMMA resist (pattern) 49: Ti / Pt / Au metal layer

49a: T-type gate

The present invention to achieve the above object, the first step of forming a first insulating film on a compound semiconductor substrate having a predetermined lower layer; A second step of forming a plurality of second insulating films on the first insulating film, wherein the wet etch rate is increased toward the uppermost layer; Forming a photoresist pattern for forming a gate bridge pattern on the second insulating film; A fourth step of dry etching the plurality of second insulating layers and the first insulating layer using the photoresist pattern as an etching mask; A fifth step of forming a stepped profile by wet etching the plurality of second insulating layers; A sixth step of opening the gate formation region by flowing the photoresist pattern; Forming a gate conductive layer on the entire structure; And an eighth step of lifting-off the photoresist pattern to form a gate.

That is, according to the present invention, the deposition temperature of the sacrificial layer (eg, silicon nitride layer) for forming the T-type gate is gradually changed to deposit a multilayer thin film, and then the etching rate difference between layers according to the deposition temperature during wet etching. And a stepped fine T-type gate having a stable structure by using a flow characteristic in which the electron beam resist pattern flows down at a high temperature. That is, the present invention forms a stepped structure where the gate bridge and the head meet each other to prevent the gate bridge and the head from breaking, and because the insulating film supports the gate bridge from both sides, the fine gate bridge and the large T-type are large. The gate electrode can be manufactured without lifting.

Hereinafter, the embodiments of the present invention will be introduced for preferred and easy implementation.

3A to 3N illustrate a process for manufacturing a field effect compound semiconductor device according to an exemplary embodiment of the present invention. Hereinafter, the process will be described with reference to the accompanying drawings.

First, as shown in FIG. 3A, an ohmic metal layer 41 and a primary metal layer 42 are formed on a GaAs substrate 40 on which a channel layer is formed and washed.

Next, as shown in FIG. 3B, the silicon oxide film 43 is deposited on the entire structure at a temperature of 300 to 350 ° C. at a thickness of 2000 microseconds, and then 250 on the silicon oxide film 43 as shown in FIG. 3C. The silicon nitride film 44 is deposited to a thickness of 1500 Å by PECVD (Plasma Enhanced Chemical Vapor Deposition) at a high temperature of about ℃.

Subsequently, as illustrated in FIG. 3D, the silicon nitride film 45 is deposited to a thickness of 1500 占 폚 by PECVD at a temperature of about 200 ° C., and the silicon nitride film 46 by PECVD at a temperature of about 100 ° C. as shown in FIG. 3E. ) Is deposited to 5000 mm thick.

Subsequently, as shown in FIG. 3F, an aluminum film 47 is deposited to a thickness of 50 to 100 Å on the whole structure at room temperature. At this time, the aluminum film 47 is removed after the lithography process as an auxiliary layer for increasing the resolution during the electron beam lithography process.

Next, as shown in FIG. 3g, the substrate is pretreated with HMDS (HexaMethyl DiSilazane), and then the PMMA resist 48 is applied to a thickness of 0.25 μm, and a baking process is performed.

Subsequently, after the exposure is performed using a mask for forming a gate bridge as shown in FIG. 3H, a resist pattern 48 is formed by developing using a mixed solution of Methyl Iso Butyl Ketone (MIBK): IsoPropylAlcohol (IPA). After the baking is carried out, the residue is treated with O ₂ plasma.

Subsequently, as shown in FIG. 3I, the vertical pattern is transferred to the silicon oxide film 43 by a dry etching method using a C ₂ F ₆ + CHF ₃ mixed gas. At this time, the dry etching selectivity of the GaAs substrate 40 and the silicon oxide film 43 is typically 1:30, so that pattern transfer is possible without damaging the GaAs substrate 40.

Thereafter, as shown in FIG. 3J, the aluminum film 47 and the silicon nitride films 46, 45, and 44 are etched using a 30: 1 BOE (Buffered Oxide Etchant) solution. At this time, the aluminum film 47 has an etching selectivity similar to that of the silicon nitride film 46 below, and the silicon nitride films 46, 45, and 44 have different etching rates depending on their deposition temperatures. A stepped etching cross section can be easily obtained, and the gate bridge pattern transferred to the high temperature silicon oxide film 43 is hardly damaged during wet etching. The wet etch rate (when using 30: 1 BOE) according to the deposition temperature of the silicon nitride film is shown in FIG. 4. As shown, an etching selectivity of tens or hundreds can be obtained.

Subsequently, heat treatment is carried out at high temperature to facilitate gate metal deposition, and the resist pattern 48 flows down to obtain a shape as shown in FIG. 3K. At this time, the proper temperature of heat treatment is 160 degreeC or more.

Subsequently, a portion of the GaAs substrate 40 is etched to form a gate electrode as shown in FIG. 3L, and then gate recessed. Then, as shown in FIG. 3M, a Ti / PT / Au metal layer ( 49) is deposited and the resist pattern 48 is lifted off as shown in FIG. 3N to complete the fabrication of the T-type gate 49a.

The silicon oxide film 43, the silicon nitride films 44, 45, 46, and the aluminum film 47 used in the above-described embodiment may be replaced with other material films according to their respective roles.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.

As described above, the present invention has the following advantages over the conventional T-type gate forming process.

First, since only a single layer of PMMA resist is used in the electron beam resist gate forming process, there is no influence due to the proximity effect, so that a fine gate pattern can be formed. Second, since the insulating film supports the T-type gates at the left and right of the gate, the metal due to the fine gate is used. Third, the gate bridge and the head meets automatically formed a stepped structure, so the ratio of gate line width to height is improved, and fine gate deposition is possible. The thickness makes it easy to adjust the gate metal deposition thickness.

Claims (11)

A first step of forming a first insulating film on the compound semiconductor substrate on which a predetermined lower layer is formed; A second step of forming a plurality of second insulating films on the first insulating film, wherein the wet etch rate is increased toward the uppermost layer; Forming a photoresist pattern for forming a gate bridge pattern on the second insulating film; A fourth step of dry etching the plurality of second insulating layers and the first insulating layer using the photoresist pattern as an etching mask; A fifth step of forming a stepped profile by wet etching the plurality of second insulating layers; A sixth step of opening the gate formation region by flowing the photoresist pattern; Forming a gate conductive layer on the entire structure; And An eighth step of forming a gate by lifting the photoresist pattern off; Fine T-type gate forming method of a compound semiconductor device comprising a. The method of claim 1, The method of forming a fine T-type gate of a compound semiconductor device, characterized in that the photoresist pattern is an electron beam photoresist pattern. The method of claim 1, And performing a ninth step of forming a gate recess in the compound semiconductor substrate after performing the sixth step. The method of claim 2, And a tenth step of forming a lithography auxiliary layer on the entire structure after performing the second step. The method according to any one of claims 1 to 4, The method of forming a fine T-type gate of a compound semiconductor device, wherein the first insulating film is a silicon oxide film. The method according to any one of claims 1 to 4, The method of forming a fine T-type gate of a compound semiconductor device, wherein the second insulating film is a silicon nitride film. The method of claim 6, In the second step, the method of forming a fine T-type gate of the compound semiconductor device, characterized in that the deposition temperature of each of the plurality of second insulating film is reduced to the uppermost. The method of claim 4, wherein The method of forming a fine T-type gate of a compound semiconductor device, characterized in that the lithography auxiliary film is an aluminum film. The method according to claim 2 or 4, The electron beam photoresist pattern is a polymethyl methacrylate (PMMA) photoresist pattern, characterized in that the fine T-type gate forming method of a compound semiconductor device. The method of claim 9, In the sixth step, the flow of the photoresist pattern is a fine T-type gate forming method of the compound semiconductor device, characterized in that at least 160 ℃. The method of claim 7, wherein In the fifth step, a method of forming a fine T-type gate of the compound semiconductor device, characterized in that using a buffered oxide etchant (BOE) solution.