KR102437939B1 - Method of formation of self-aligned source/drain and ultra-short gate length with wet etching - Google Patents

Abstract

A method of forming a self-aligned source/drain and ultrafine gate using wet etching is disclosed. forming a sacrificial layer and a first insulating oxide layer (SiO ₂ ) on the substrate; depositing a metal film for an etching mask after applying a photoresist and forming a pattern for forming a source electrode and a drain electrode; removing the metal film for an etch mask deposited on the region of the source electrode and the drain electrode, and removing the photoresist under the metal film; dry etching the first oxide insulating layer and the sacrificial layer in the source electrode and drain electrode regions; performing an ion implantation process for the source electrode and the drain electrode; forming a fin structure by performing lateral directional wet etching on the sacrificial layer in the gate electrode formation region after removing the metal film for an etching mask in the gate electrode formation region; The step of removing the fin structure and forming a T-type gate electrode in the corresponding region is configured.

Description

METHOD OF FORMATION OF SELF-ALIGNED SOURCE/DRAIN AND ULTRA-SHORT GATE LENGTH WITH WET ETCHING

The present invention relates to a method of forming a semiconductor electrode, and more particularly, to a method of forming a self-aligned source/drain and an ultrafine gate using wet etching.

In general, when a semiconductor electrode is formed, when diffusion occurs between the source electrode and the drain electrode, each region of the source electrode and the drain electrode increases.

In this case, a short channel effect is generated in the channel below the gate electrode, so that desired operating characteristics cannot be obtained.

In order to prevent such a problem, in the related art, sidewalls are provided at both ends of the gate electrode to set a spacer between the source electrode and the drain electrode to prevent diffusion.

However, more processes are added by the formation process of the sidewall, and a lot of cost and time are required. Of course, this process may also bring about a decrease in yield.

On the other hand, this short channel effect can be solved to some extent by reducing the parasitic capacitance by forming the T-gate electrode as a microelectrode. Conventionally, a tri-layer resist film is mainly used to form a microelectrode in the vertical direction of the T-gate electrode.

However, since the process is increased in the process of using the double layer and triple photoresist film, there are still problems of lowering the yield and increasing the cost.

As described above, it is inevitable to add many processes for the formation of the conventional T-gate microelectrode or for alignment between the source electrode and the drain electrode.

Registered Patent Publication No. 10-0301969 Laid-Open Patent Publication No. 10-2008-0093659

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of forming a self-aligned source/drain and an ultrafine gate using wet etching.

The self-aligned source/drain and ultra-fine gate formation method using wet etching according to the above-described object of the present invention includes: forming a sacrificial layer and a first insulating oxide layer (SiO ₂ ) on a substrate; depositing a metal film for an etching mask after applying a photoresist and forming a pattern for forming a source electrode and a drain electrode; removing the metal film for an etch mask deposited on the region of the source electrode and the drain electrode, and removing the photoresist under the metal film; dry etching the first oxide insulating layer and the sacrificial layer in the source electrode and drain electrode regions; performing an ion implantation process for the source electrode and the drain electrode; forming a fin structure by performing lateral directional wet etching on the sacrificial layer in the gate electrode formation region after removing the metal film for an etching mask in the gate electrode formation region; It may be configured to include removing the fin structure and forming a T-type gate electrode in the corresponding region.

Here, the step of forming the sacrificial layer and the first insulating oxide layer (SiO ₂ ) on the substrate may include forming a 2DEG by heterojunction with a buffer layer, a channel layer, and the channel layer for blocking leakage current on the substrate. It may be configured to sequentially form a barrier layer, and to form a sacrificial layer and an oxide insulating film on the barrier layer.

In addition, the forming of the sacrificial layer and the first insulating oxide layer (SiO ₂ ) on the substrate may include forming the sacrificial layer using any one of Si, InGaAs, GaAs, or GaN.

And performing the ion implantation process for the source electrode and the drain electrode includes depositing an ion implantation protective layer as a whole to protect the gate electrode formation region, and applying ions for forming the source electrode and the drain electrode to the barrier layer. It may be configured to implant into the ion implantation layer and remove the ion implantation protective layer.

Here, the ion implantation protective layer may be formed of any one of SiN, SiO ₂ , Al ₂ O ₃ , or HfO ₂ .

In addition, in the performing the ion implantation process for the source electrode and the drain electrode, lateral wet etching may be performed so that the fin structure has a width of 40 nm or less.

Meanwhile, removing the fin structure and forming the T-type gate electrode in the region includes depositing a second insulating oxide layer (SiO ₂ ) as a whole, and etching the second insulating layer to expose the upper portion of the fin structure. Then, only the fin structure may be selectively wet-etched to form a fin structure space.

Here, the step of removing the fin structure and forming the T-type gate electrode in the region may be configured such that the T-type gate electrode is formed on the fin structure space and the width of the fin structure space is 40 nm or less. can

According to the self-aligning source/drain and ultrafine gate formation method using the wet etching described above, the width of the GaN fin is reduced by reducing the microcavity by lateral directional wet etching when forming the T-type gate microelectrode. By being configured to form a T-type gate microelectrode, it is possible to easily and quickly form a T-type gate microelectrode with fewer steps compared to the conventional microelectrode formation using a tri-layer resist, as well as to further reduce the width of the microelectrode. can have an effect. Ultimately, there is an effect of further reducing the gap between the source/drain electrodes.

In addition, it is configured to immediately form source/drain electrodes by ion implantation while protecting the gate electrode region using a metal film for an etching mask, thereby self-aligning the source/drain electrodes without a separate sidewall. , it has the effect of reducing the process. In addition, since the distance between the source/drain electrodes can be reduced, there is an effect that can be applied to the fabrication of a high-frequency device having a narrow distance between the source/drain electrodes.

1 to 11 are process flow diagrams of a method of forming a self-aligned source/drain and an ultrafine gate using wet etching according to an embodiment of the present invention.

Since the present invention can have various changes and can have various embodiments, specific embodiments are illustrated in the drawings and will be described in detail in the detailed content for carrying out the invention. However, this is not intended to limit the present invention to specific embodiments, and should be understood to include all modifications, equivalents and substitutes included in the spirit and scope of the present invention. In describing each figure, like reference numerals have been used for like elements.

Terms such as first, second, A, and B may be used to describe various elements, but the elements should not be limited by the terms. The above terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, a first component may be referred to as a second component, and similarly, a second component may also be referred to as a first component. and/or includes a combination of a plurality of related listed items or any of a plurality of related listed items.

When a component is referred to as being “connected” or “connected” to another component, it may be directly connected or connected to the other component, but it is understood that other components may exist in between. it should be On the other hand, when it is said that a certain element is "directly connected" or "directly connected" to another element, it should be understood that the other element does not exist in the middle.

The terms used in the present application are only used to describe specific embodiments, and are not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly dictates otherwise. In the present application, terms such as “comprise” or “have” are intended to designate that a feature, number, step, operation, component, part, or combination thereof described in the specification exists, but one or more other features It is to be understood that this does not preclude the possibility of the presence or addition of numbers, steps, operations, components, parts, or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in a commonly used dictionary should be interpreted as having a meaning consistent with the meaning in the context of the related art, and should not be interpreted in an ideal or excessively formal meaning unless explicitly defined in the present application. does not

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings.

1 to 11 are process flow diagrams of a method of forming a self-aligned source/drain and an ultrafine gate using wet etching according to an embodiment of the present invention.

First, referring to FIG. 1 , a buffer layer 101 , a channel layer 102 , a barrier layer 103 and a sacrificial layer 104 on a substrate 100 . are formed sequentially.

Here, the buffer layer 101 is a high resistivity layer, and may block leakage current of the channel layer 102 to be formed on the buffer layer 101 . The buffer layer 101 may be made of GaN.

In addition, the channel layer 102 may be a conductive region as an operating region of the semiconductor device. The channel layer 102 may be made of GaN.

In addition, the barrier layer 103 is composed of a component different from that of the channel layer 102 to form a heterojunction, and can form 2-dimensional electron gas (2DEG). Accordingly, a potential is formed between the channel layer 102 and the barrier layer 103 , and it is possible to prevent electrons or holes from the channel layer 102 from being transferred to the barrier layer 103 .

Meanwhile, a first oxide insulating layer (SiO2) 105 having a thickness of at least 100 nm or more is formed on the sacrificial layer 104 . Then, a photoresist may be applied thereon by a lithography process, and a pattern may be formed using a mask.

In this case, the photoresist of the source electrode region and the drain electrode region may be made insoluble to form a negative photoresist 106 in the corresponding regions.

In FIG. 2 , an etch mask metal layer 107 having a thickness of 150 nm or more is entirely deposited. The metal layer 107 for an etch mask is configured to allow the first insulating oxide layer 105 to remain without being etched, thereby leaving the first insulating oxide layer 105 and the sacrificial layer 104 in the gate region.

As the metal film 107 for the etch mask, a Ni/Au layer may be used.

In FIG. 3 , only the metal film 107 for the etching mask on the negative photoresist 106 is lifted off using the metal film 107 for the etching mask of FIG. 2 and removed. Then, the negative photoresist 106 and the first oxide insulating film 105 in the corresponding region are removed. After this process, only the metal layer 107 for the etch mask in the gate electrode region remains as shown in FIG. 4 .

Next, the sacrificial layer 104 in the region excluding the region where the metal film 107 for the etch mask remains is dry etched. That is, as shown in FIG. 5 , the metal layer 107 for an etching mask blocks the dry etching gas, and only the sacrificial layer 104 in the remaining area is etched and removed.

Next, an ion implantation process is performed to form a source electrode or a drain electrode. Prior to ion implantation, as shown in FIG. 6 , an ion implantation passivation layer 108 is first deposited as a whole. The ion implantation protective layer 108 may be formed of any one of SiN, SiO ₂ , Al ₂ O ₃ , or HfO ₂ . Then, the source electrode 109 and the drain electrode 109 - 1 are formed by implanting ions into the barrier layer 103 using PECVD or ALD. 6 illustrates an N+ dopant as an ion.

Next, the ion implantation passivation layer 108 is removed, and the metal layer 107 for an etching mask is also lifted off and removed. Then, as shown in FIG. 7 , lateral directional wet etching is performed on the sacrificial layer 104 under the first insulating oxide layer 105 to perform etching only in the lateral direction.

As shown in FIG. 7 , a fin structure 104a is formed by using the sacrificial layer 104 by such lateral wet etching. By wet etching, only the sacrificial layer 104 of GaN is selectively etched while leaving the first insulating oxide film 105 as it is, and the sacrificial layer 104 is etched only in the lateral direction by lateral etching to form a fin structure 104a create a shape

The fin structure 104a may be configured to have a horizontal width of 40 nm or less.

Next, the first insulating oxide film 105 is removed, and the second insulating oxide film 110 is entirely deposited. Referring to FIG. 8 , it can be seen that the second oxide insulating layer 110 is entirely coated to cover the ions 109 and the fin structure 104a.

Next, as shown in FIG. 9 , the upper surface of the second oxide insulating layer 110 is dry etched, and when the fin structures 104a are exposed, the fin structures 104a are selectively removed by wet etching. When the fin structure 104a is removed, as shown in FIG. 10 , the fin structure space 104b is formed.

Next, a T-type gate electrode 111 as shown in FIG. 11 is formed on the fin structure space 104b. Here, the T-type gate electrode 111 may be formed through a lithography process.

Although described with reference to the above embodiments, those skilled in the art can understand that various modifications and changes can be made to the present invention without departing from the spirit and scope of the present invention as set forth in the following claims. There will be.

100: substrate
101: buffer layer
102: channel layer
103: barrier layer
104: sacrificial layer
104c: fin structure
104b: pin structure space
105: first oxide insulating film
106: photoresist
107: metal film for etching mask
108: ion implantation shield
109: source electrode
109-1: drain electrode
110: second oxide insulating film
111: T-type gate electrode

Claims (8)

forming a barrier layer, a sacrificial layer, and a first insulating oxide layer (SiO ₂ ) on a substrate;
depositing a metal film for an etching mask after applying a photo resist, forming a pattern for forming a source electrode and a drain electrode;
removing the metal film for an etch mask deposited on the region of the source electrode and the drain electrode, and removing the photoresist under the metal film;
dry etching the first oxide insulating layer and the sacrificial layer in the source electrode and drain electrode regions;
performing an ion implantation process for the source electrode and the drain electrode on the barrier layer;
forming a fin structure by performing lateral directional wet etching on the sacrificial layer in the gate electrode formation region after removing the metal film for an etching mask in the gate electrode formation region;
and removing the fin structure and forming a T-type gate electrode in the corresponding region.
According to claim 1,
Forming a barrier layer, a sacrificial layer and a first oxide insulating film (SiO ₂ ) on the substrate,
A buffer layer for blocking leakage current, a channel layer, and a barrier layer forming a 2DEG by heterojunction with the channel layer are sequentially formed on the substrate, and a sacrificial layer and an oxide insulating film are formed on the barrier layer A method of forming a self-aligned source/drain and ultrafine gate using wet etching, characterized in that.
According to claim 1,
Forming a barrier layer, a sacrificial layer and a first oxide insulating film (SiO ₂ ) on the substrate,
A method of forming a self-aligned source/drain and ultrafine gate using wet etching, characterized in that the sacrificial layer is formed using any one of Si, InGaAs, GaAs, or GaN.
3. The method of claim 2,
The step of performing an ion implantation process for the source electrode and the drain electrode on the barrier layer,
Wet type, characterized in that it is configured to deposit an ion implantation protective film as a whole to protect the gate electrode formation region, implant ions for forming the source electrode and the drain electrode into the barrier layer, and remove the ion implantation protective film A self-aligned source/drain and ultrafine gate formation method using etching.
5. The method of claim 4,
The ion implantation protective film,
SiN, SiO ₂ , Al ₂ O ₃ or HfO ₂ A self-aligned source/drain and ultrafine gate formation method using wet etching, characterized in that it consists of any one.
According to claim 1,
The step of performing an ion implantation process for the source electrode and the drain electrode on the barrier layer,
The self-aligned source/drain and ultrafine gate formation method using wet etching, characterized in that the fin structure is lateral wet etched to have a width of 40 nm or less.
According to claim 1,
The step of removing the fin structure and forming a T-type gate electrode in the corresponding region comprises:
A second insulating oxide film (SiO ₂ ) is deposited as a whole, and the second insulating oxide film is etched to expose the upper portion of the fin structure, and then only the fin structure is selectively wet-etched to form a fin structure space. A method of forming self-aligned source/drain and ultrafine gates using wet etching.
8. The method of claim 7,
The step of removing the fin structure and forming a T-type gate electrode in the corresponding region comprises:
A method of forming a self-aligned source/drain and ultrafine gate using wet etching, characterized in that a T-type gate electrode is formed on the fin structure space and the width of the fin structure space is 40 nm or less.

Images