TW201919131A - Method for forming semiconductor structure - Google Patents

Abstract

The present invention provides a method for forming a gate structure, comprising forming a first patterned photoresist layer on a substrate; forming a spacer on a sidewall of the first patterned photoresist layer wherein the spacer contains a curved portion; removing the first patterned photoresist layer; forming a replacement photoresist layer on the substrate wherein the spacer is inserted within the replacement photoresist and the curved portion is exposed; and removing the spacer to form an opening within the replacement photoresist, wherein the opening defines a size of a bottom portion of a gate. The present invention also provides the gate structure formed using the above method.

Description

 Semiconductor structure and method of forming same  

The present invention relates to a method of forming a semiconductor structure, and more particularly to a method of forming a semiconductor structure including a gate.

T-type gates, also known as Y-type gates or mushroom gates, are commonly used gate structures in three-five family of transistor power amplifiers. 1 is a schematic cross-sectional view showing a portion of a structure of a high electron mobility transistor (HEMT) used as a power amplifier, which includes a T-type gate 101 having a narrow root 101a in contact with the channel region and a head 101b wider above. . The wider head 101b can increase the cross-sectional area and reduce the gate series resistance; the narrower root 101a can reduce the gate length and reduce the gate capacitance. In order to achieve a very short gate length, the prior art uses an expensive electron beam lithography process or a deep UV stepper to fabricate a T-type gate, which results in high cost and is difficult to popularize. Therefore, there is still a need for novel and innovative technologies to solve the above problems.

In one aspect, the present invention provides a method of fabricating a gate using a spacer to define a gate length. The method of the present invention produces a variety of semiconductor gates including T-type gates. The implementation of the present invention allows the use of general lithography process equipment, and is not limited by expensive electron beam lithography processes or deep UV steppers. The present invention also provides an easy method of protecting the substrate from the active region during gate fabrication. The present invention utilizes a photoresist that defines a gate structure to protect other active regions of the substrate, thereby eliminating many additional protection processes. In addition, the present invention can simultaneously remove all the photoresists defining the gate structure, which makes the process easier.

The present invention is advantageous in the manufacture of a III-V compound semiconductor device by fabricating a gate using a lift-off process. In general III-V compound semiconductor devices, it is relatively difficult to fabricate a T-type gate by metal etching because the material properties of the III-V compound itself are dry etching (such as inductively coupled plasma ion etching ICP or reactive ion etching RIE). ) sensitive, the surface is easily damaged and the carrier concentration is lost. Since the active layer of the element is very thin, ion etching close to the surface easily removes the active layer or causes serious carrier loss, and the integrity of the active layer cannot be maintained, an etching process is used to fabricate a general III-V compound semiconductor device. It is more difficult. The present invention utilizes a lift-off process to fabricate a gate, particularly a T-type gate of a III-V compound semiconductor to avoid the dilemma of metal etching.

The method of the present invention produces a variety of semiconductor gates including T-type gates. The implementation of the present invention allows the use of general lithography process equipment, and is not limited by expensive electron beam lithography processes or deep UV steppers.

The present invention is also intended to cover other problems and the embodiments described above are disclosed in detail in the following embodiments.

101, 1420, 1520‧‧‧T-type gate

101a, 1710r‧‧‧ root

101b, 1710h‧‧‧ head

200, 200', 1700‧‧‧ substrates

S‧‧‧ source

G, 1100, 1300‧‧ ‧ gate

D‧‧‧汲

310, 310', 610', 730'‧‧‧ photoresist layer

310d, 310s‧‧‧ photoresist sidewall

320, 811d, 811s, 1416d, 1416s, 1516d, 1516s, 1705, 1707‧‧

Sw, Dw‧‧‧ sidewall

410‧‧‧ dielectric layer

510d, 510s, 1412d, 1412s, 1512d, 1512s, 1701, 1702‧ ‧ spacers

511‧‧‧Bend section

522‧‧‧ equal parts

610‧‧‧second photoresist layer

811r‧‧‧ gap

730, 1415, 1515‧‧‧ alternative photoresist layer

920, 1020‧‧‧ insulation

930, 1010‧‧‧ conductive layer

940‧‧‧ Third patterned photoresist

220, 220'‧‧‧ Schottky barrier layer

1120

210’‧‧‧coating

1400, 1500, 1700a‧‧‧ dent

1410, 1510‧‧‧ first patterned photoresist layer

200'a, 200"a, 1700s‧‧‧ substrate surface

1501‧‧‧ platform

1703‧‧‧patterned photoresist layer

1706‧‧‧flat photoresist layer

A1, A2‧‧‧

1 is a schematic cross-sectional view showing a portion of a structure of a high electron mobility transistor (HEMT) used as a power amplifier; FIGS. 2a, 2b, 3, 4, 5, 5a, 6a, 7a, 8a, 6b, 6b', 7b 8b, 9, 10, 11 are schematic views showing a manufacturing process of the gate structure according to the first embodiment of the present invention, wherein FIGS. 6a, 7a and 8a relate to the first method; and FIGS. 6b, 6b', 7b and 8b relate to the second method 12 and 13 are schematic views showing a manufacturing process of a gate structure according to a second embodiment of the present invention; and FIGS. 14a, 14b and 14c are views showing a manufacturing process of a gate structure according to a third embodiment of the present invention; FIGS. 15a, 15b and 15c show the present invention; BRIEF DESCRIPTION OF THE DRAWINGS FIG. 16 shows a gate structure of a fifth embodiment of the present invention; and FIGS. 17a, 17b, 17c and 17d show a manufacturing process of a gate structure according to a sixth embodiment of the present invention. .

Preferred embodiments of the present invention will be exemplified below with reference to the accompanying drawings. Like components in the drawings have the same component symbols. It should be noted that the various elements in the drawings are not drawn to the actual scale, and in order to avoid obscuring the present invention, the following description also omits conventional principles, components, related materials, and related processes. technology.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the gate structure of the present invention will be described with reference to the accompanying drawings.

First, a first embodiment will be described to provide a substrate. The substrate is usually a gallium arsenide substrate, but may be any other semiconductor material suitable for forming a gate structure thereon, such as InP, GaN, Si, SiC, SiGe, GaSb, Group IV, Group IV-IV, III-V. Family, II-VI. The substrate can include various active components such as various epitaxial layers used to fabricate pHEMT, HEMT, MESFET, MOSFET, and the like. In this embodiment, a gate of a HEMT is exemplified. The step begins with a substrate 200 that includes each epitaxial layer, source S, and drain D. Fig. 2a is a plan view of the substrate 200, and Fig. 2b is a schematic cross-sectional view taken along the dashed line from point A to point A' in Fig. 2a. The surface of the substrate 200 includes a plurality of drains D and a plurality of sources S protruding from the surface of the substrate 200.

Referring to FIG. 3, a first patterned photoresist layer 310 is formed on the substrate 200. The first patterned photoresist layer 310 covers a portion of the substrate 200. The pattern of the first patterned photoresist layer 310 determines the location at which the gate is to be subsequently formed. In this embodiment, the position of the gate is preferably preset between the source S and the source S and closer to the sidewall Sw of the source S with respect to the drain D. As shown in FIG. 3, in the present embodiment, the first patterned photoresist layer 310 is designed to cover all of the drain D and the source S and has an opening 320 between one of the drains D and one of the sources S thereof. Used to make gates. The first patterned photoresist layer 310 specifically includes a sidewall Sw of the photoresist sidewall 310s covering the source S, and also includes a sidewall Dw of the photoresist D covering the drain sidewall D. The first patterned photoresist layer 310 can be formed by conventional spin coating and lithography. The photoresist thickness can be, for example, a thickness of 100 to 10,000 angstroms. In some examples, if the thickness of the first patterned photoresist layer 310 is too large, an excessive aspect ratio may be formed to affect the filling of the subsequent gate metal.

Referring also to FIGS. 3 and 4, a dielectric layer 410 is conformally deposited along the surface of the structure 200 of FIG. In detail, the dielectric layer 410 covers a portion of the substrate 200 that is not covered by the first patterned photoresist layer 310; the dielectric layer 410 also covers the top and sidewalls of the first patterned photoresist layer 310, which includes the cover light. The sidewalls 310s and 310d are blocked. Dielectric layer 410 may be formed using plasma assisted chemical vapor deposition (PECVD) or atomic layer deposition (ALD) or other CVD , and the material may be yttrium oxide (SiOx) or nitrogen oxide (SiNx) or other suitable material. The thickness of the dielectric layer 410 depends on the gate length of the gate to be subsequently formed. According to the method of the present invention, the thickness of the dielectric layer 410 is preferably in the range of 50 angstroms to 8000 angstroms.

Referring to FIG. 5, spacers 510d and 510s are formed on sidewalls of the first patterned photoresist layer 310. The dielectric layer 410 on the surface of the substrate 200 and the top of the first patterned photoresist layer 310 is removed by anisotropic etching (dry etching), but the dielectric covering the sidewalls 310d and 310s of the first patterned photoresist layer 310 is left. The layer 410 is formed to form spacers 510d and 510s, wherein the spacers 510d are adjacent to the drain D, and the spacers 510s are adjacent to the source S. As shown, in this embodiment, the spacer 510s is the position at which the gate is to be subsequently formed. Figure 5a is an enlarged schematic view of the spacer 510s/510d. The spacer 510s/510d includes a curved portion 511 (which may be referred to as a bending spacer) and an equal portion 522 (which may be referred to as an equal gap, uniform) Spacer) below. Preferably, the height ratio of the curved portion 511 to the height of the flush portion 522 is about 1:2.

Two methods of forming a gate opening using the spacer 510s are described below. Figures 6a, 7a and 8a show a first method; Figures 6b, 6b', 7b and 8b show a second method. After the gate opening is formed, the gate insulating layer and the gate metal can be filled to complete the gate structure.

Referring first to FIG. 6a of the first method, a second photoresist layer 610 is formed on the substrate 200, and the second photoresist layer 610 covers the first patterned photoresist layer 310 and the spacers 510d and 510s. The second photoresist layer 610 can be formed flat by conventional spin coating and lithography methods. The second photoresist layer 610 and the first patterned photoresist layer 310 may use the same or different materials, preferably using the same material with subsequent one-time removal. In a preferred embodiment, to make the second photoresist layer 610 form a flat upper surface as much as possible, the height of the second photoresist layer 610 may be larger.

Referring to FIG. 7a of the first method, a portion of the second photoresist layer 610 and a portion of the first patterned photoresist layer 310 are removed to expose the curved portion 511 of the spacer 510d/510s. This step can be carried out using reactive ion etching or any other suitable technique such as plasma asher. As described above, the spacer 510d/510s includes the curved portion 511 and the equal portion 522, and the photoresist removal amount in this step is controlled to expose the curved portion 511 of the spacer 510d/510s, and the equal portion 522 remains in the remaining portion. The two photoresist layers 610' are in the remaining first patterned photoresist layer 310'. The portion of the spacers 510d/510s buried in the residual photoresist layers 610' and 310' determines the subsequent formation of the gate root profile. If the bent portion 511 is not entirely exposed and buried in the residual photoresist layers 610' and 310', the subsequently formed gate may have a narrow and fragile neck.

Referring to FIG. 8a of the first method, the spacers 510d and 510s are removed to form an opening 811s and 811d in the remaining second photoresist layer 610' and the remaining first patterned photoresist layer 310'. The opening 811s defines a gate. A bottom dimension in which the opening 811s is adjacent to the source S. The present invention provides various embodiments with openings ranging from 50 angstroms to 6000 angstroms. This step can be carried out using liquid phase chemical etching, such as BOE/HF + H2O. After the openings 811s and 811d are formed, a gate insulating layer (not necessary) may be formed along the surfaces of the openings 811s and 811d by various suitable methods and a gate conductive layer may be formed on the gate insulating layer to constitute a gate structure. In addition, FIG. 8a also shows another optional step of forming the notch portion 811r in the substrate 200 after removing the spacers 510d and 510s. In some instances, this step can be used to remove the cladding layer on the surface of the substrate 200. The method is as follows: the residual second photoresist layer 610 ′ and the remaining first patterned photoresist layer 310 ′ are masked, and the openings 811 s and 811 d of the bottom substrate 200 are etched to form a notch portion 811 r to expose an epitaxial layer inside the substrate 200 . Floor. For example, the cladding layer on the surface of the substrate 200 is removed, for example, to expose the Schottky barrier layer.

A second method of forming a gate opening using a spacer is illustrated below as shown in Figures 6b, 7b and 8b. Continuing with Figures 5 and 5a, and subsequently referring to Figure 6b of the second method, the first patterned photoresist layer 310 is completely removed and this step can be accomplished by a suitable etching and development process. Next, an alternative photoresist layer 730 is formed on the surface of the substrate 200 with reference to FIG. 7b of the second method, and the thickness of the replacement photoresist layer 730 is controlled to cover the source S, the drain D, or other active regions on the substrate 200. The equidistant portions 522 of the spacers 510d and 510s are buried in the replacement photoresist layer 733 and the curved portions 511 of the spacers 510d and 510s are exposed. The alternative photoresist layer 730 can be formed using any suitable means to avoid damaging the spacers 510d and 510s and to accurately control the thickness of the replacement photoresist layer 730. For example, referring to FIG. 6b', a flat photoresist layer 730' may be formed to cover the source S, the drain D, other active regions on the substrate 200, and all portions of the spacers 510d and 510s, and then etch back flat. A portion of the material of the photoresist layer 730' is exposed such that the curved portions 511 of the spacers 510d and 510s are exposed, and the equal portions 522 of the spacers 510d and 510s are still buried in the flat photoresist layer, and the etched flat photoresist layer 730' is the alternative photoresist layer 733 (as shown in Figure 7b). A suitable photoresist material can be placed in a nozzle to form a flat photoresist layer 730' by a vapor spray method. Note that the portion of the spacer 510d/510s buried in the replacement photoresist layer 730 determines the subsequent formation of the gate root profile. If the curved portion 511 is not entirely exposed and buried in the replacement photoresist layer 730, the subsequently formed gate has a narrow and fragile neck.

Referring to Figure 8b of the second method, the spacers 510d and 510s are removed to form an opening 811s and 811d in the alternative photoresist layer 730. The opening 811s defines a bottom dimension of the gate, wherein the opening 811s is adjacent to the source S. The present invention provides various embodiments with openings ranging from 50 angstroms to 6000 angstroms. This step can be carried out using liquid phase chemical etching, such as BOE/HF + H2O. After the openings 811s and 811d are formed, a gate insulating layer (not necessary) may be formed along the surfaces of the openings 811s and 811d by various suitable methods and a gate conductive layer may be formed on the gate insulating layer to constitute a gate structure. In addition, FIG. 8b also shows another optional step of forming the notch portion 811r in the substrate 200 after removing the spacers 510d and 510s. This step can be referred to the foregoing without further description.

The gate insulating layer can be fabricated by continuing the first method of FIG. 8a or the second method of FIG. 8b. The fabrication of the gate insulating layer of Figure 9 is continued with Figure 8b of the second method. Only the gate insulating layer is not necessary and can be chosen selectively. A conformal insulating layer 920 is formed to cover the openings 811d/811s and the replacement photoresist layer 730 (if the first method covers the remaining second photoresist layer 610' and the residual first photoresist layer 310'). In the example in which the notch 811r is formed, the conformal insulating layer 920 also covers the notch 811r. This step can be accomplished using plasma assisted chemical vapor deposition (PECVD) , other CVD, or atomic layer deposition (ALD). The insulating layer 920 is a relatively thin layer compared to each of the photoresist layers described above. Preferably, the insulating layer 920 has a thickness in the range of 50 to 2000 angstroms, and the preferred material may be a high K (high K) insulating material such as HfOx or AlOx or TiOx .

Next, referring to FIG. 9, the fabrication of the gate conductive layer is performed. After the conformal insulating layer 920 is formed, a conductive layer 930 is formed to cover the conformal insulating layer 920, and the openings 811d/811s and the notches 811r are filled. This step can be accomplished by sputtering or other isotropic deposition methods. The material of the conductive layer 930 can be any suitable metal or conductive material. Next, referring also to FIG. 9, a third patterned photoresist 940 is formed on the conductive layer 930, and the third patterned photoresist 940 defines the top shape of the gate. In this embodiment, the gate is located near the opening 811s of the source, so the third patterned photoresist 940 does not cover the opening 811d near the drain. In the example of forming a T-type gate, the third patterned photoresist 940 can be used to design the wide head of the gate, but this case is not limited to the T-type gate. Forming the third patterned photoresist 940 can be performed by conventional spin coating methods and lithography. The third patterned photoresist 940 may use the same or different material as the foregoing alternative photoresist layer 730, the second photoresist layer 610, or the first patterned photoresist layer 310, and preferably the same material has a subsequent use. Remove.

Next, referring to FIG. 9 and FIG. 10, the third patterned photoresist 940 is used as a mask, and a portion of the conductive layer 930 is removed to form a gate conductive layer 1010; the third patterned light may be used in the same step or in different steps. The resistor 940 is a mask, and a portion of the conformal insulating layer 920 is removed to form a gate insulating layer 1020. This step can be accomplished using wet etching or with dry plasma etching. Note that this step also removes the conformal insulating layer 920 and the conductive layer 930 in the opening 811d and the notch 811r.

Referring to FIG. 11, the third patterned photoresist 940 and the replacement photoresist layer 730 are removed to expose the gate 1100 on the substrate 200. Figure 11 shows an example of forming a T-type gate having a wider top and a narrower root. This step can be performed by any suitable method, such as liquid phase etching, using any suitable photoresist removal technique. In a preferred embodiment, instead of the photoresist layer 730 (the remaining second photoresist layer 610' (as shown in FIGS. 7a and 8a), the remaining first patterned photoresist layer 310' (as shown in FIGS. 7a and 8a) and The third patterned photoresist 940 can be removed simultaneously.

Note that the gate 1100 shown in FIG. 11 is located between the drain D and the source S, and the gate 1100 is adjacent to the source S compared to the drain D. In addition, this example proposes a structure in which the gate 1100 and the drain D have a notch 811r, and the notch 811r exposes an epitaxial layer inside the substrate 200, such as a Schottky barrier layer. The gap 811r can be placed at the depletion edge by appropriate design, which can alleviate the current crowding effect to increase the breakdown voltage without reducing or sacrificing the cut-off frequency and gain of the transistor. This can increase the performance of the power amplifier. The present invention includes another embodiment in which a metal layer is deposited on the notch 811r but not as a gate, and the metal layer is floated and not electrically connected to the outside, and the metal layer can be adapted to the surface depletion region. The electric field is distributed to achieve the required breakdown voltage and high cutoff frequency and high gain.

Referring to FIG. 11, a semiconductor structure is provided, including a substrate 200 having a drain D, a source S, and a gate 1100 between the drain D and the source S. The substrate 200 further includes a substrate surface 200a and a substrate surface 200a. There is a notch 811r between the drain D and the gate S. The substrate 200 further includes an epitaxial structure. The epitaxial structure includes a cladding layer 210. The notch 811r is formed in the cladding layer 210 and exposes a Schottky barrier layer 220 under the cladding layer 210. Note that the substrate surface 200a further includes a gate opening (ie, the aforementioned opening 811s), and the gate 1100 extends upward from the gate opening 811s. Since the gate opening 811s and the notch 811r are formed in the same layer and in the same process, the gate opening 811s and the notch 811r have substantially the same depth.

Figures 12 and 13 show a second embodiment of the method in which there is no gap between the gate and the drain. Figure 12 is a Figure 6b following the second method. The spacer 510d is further removed with reference to FIG. 6b to form a structure in which only the spacer 510s remains as shown in FIG. Performing this step can cover the gate S and the drain D and the spacer 510s with a suitable mask to remove the spacer 510d by liquid etching. Then, referring to the foregoing FIGS. 6b', 7b, 8b, FIG. 9 to FIG. 11, and the like, the gate 1300 shown in FIG. 13 can be obtained, and there is no gap 811r between the gate 1300 and the drain D.

Figures 14a, 14b and 14c show a third embodiment of the invention. The third embodiment differs from the first embodiment in that the substrate 200 of the first embodiment (Fig. 2b) has a substrate surface between the drain D and the source S which is flat, so that the spacer 510d/510s is formed in On the flat surface; the substrate 200' of the third embodiment (Fig. 14a) has a wide recess 1400 between the drain D and the source S, and the spacers 1412d/1412s are formed on the surface of the wide recess 1400. Note that this wide depression is mainly used to relieve surface depletion and surface current clustering effects to increase the breakdown voltage, mainly to improve the performance of high power amplifiers.

Referring to FIG. 14a, a substrate 200' having respective epitaxial layers, a source S and a drain D is provided, wherein the substrate 200' has a wide recess 1400 between its drain D and source S; the first on the substrate 200' A patterned photoresist layer 1410; and spacers 1412d/1412s are formed on the surface of the wide recess 1400. In this embodiment, the surface of the substrate 200' may be a cladding layer 210', and under the cladding layer 210' is a Schottky barrier layer 220'. Therefore, the surface of the wide recess 1400 is the cladding layer 210'.

The method of forming the structure of Fig. 14a includes first providing a substrate 200' having a wide recess 1400, and then forming a first patterned photoresist layer 1410 with its sidewalls falling on the surface of the wide recess 1400. A spacer 1412d/1412s is then formed on the surface of the wide recess 1400. For details of the application, refer to FIG. 2a, FIG. 2b, FIG. 3 to FIG. 5, and FIG. 5a of the foregoing first embodiment.

After the structure of Fig. 14a is formed, the openings can be defined by the spacers 1412d/1412s, referring to the methods of Figs. 6b, 7b, and 8b of the first embodiment, to form the structure as shown in Fig. 14b. As shown, openings 1416s and 1416d are in the alternative photoresist layer 1415, and opening 1416s is adjacent to source S and defines a bottom dimension of the gate. The opening 1416d is adjacent to the drain D. Note that the openings 1416s and 1416d may have a certain depth to expose the Schottky barrier layer 220'.

After the structure of Fig. 14b is formed, the structure having the T-type gate 1420 as shown in Fig. 14c can be formed by referring to the methods of Figs. 9, 10, and 11 of the first embodiment described above. As shown in FIG. 14c, a semiconductor structure is provided, comprising a substrate 200' having a drain D, a source S and a gate 1420 between the drain D and the source S, wherein the substrate 200' further comprises a substrate surface 200. 'a, the substrate surface 200'a has a wide recess 1400 between the drain D and the source S and a notch (ie, the aforementioned opening 1416d is formed on the bottom surface of the wide recess 1400, wherein the notch 1416d is located at the gate 1420 and the drain D The substrate 200' further includes an epitaxial structure including a cladding layer 210', and the wide recess 1400 and the notch 1416d are formed in the cladding layer 210', wherein the notch 1416d is exposed under the cladding layer 210' a Schottky barrier layer 220'. The bottom surface of the wide recess 1400 further includes a gate opening (ie, opening 1416s), the gate 1420 extends upward from the gate opening 1416s, and the gate opening 1416s and the notch 1416d have substantially The same depth is formed because they are on the same layer and in the same process step. Meanwhile, as shown in Fig. 12, the third embodiment can also remove the notch 1416d.

Figures 15a, 15b and 15c show a fourth embodiment of the invention. The difference between the fourth embodiment and the third embodiment is that the substrate 200' of the third embodiment (as shown in Fig. 14a) has a wide recess 1400 between the drain D and the source S, and the spacers 1412d/1412s are formed in the wide recess. On the surface of 1400; the substrate 200" of the fourth embodiment (Fig. 15a) has a wide recess 1500 between the drain D and the source S and a land 1501 adjacent to the wide recess 1500, and a spacer 1512d adjacent to the drain D is formed. On the surface of the stage 1501, a spacer 1512s adjacent to the source S is formed on the surface of the wide recess 1500. Therefore, the spacer 1512d is positioned higher than the spacer 1512s.

Referring to FIG. 15a, a substrate 200" having respective epitaxial layers, a source S and a drain D, wherein the substrate 200" has a wide recess 1500 between the drain D and the source S and a platform 1501 adjacent to the wide recess 1500 a first patterned photoresist layer 1510 on the substrate 200"; and a spacer 1512d adjacent to the drain D as described above is formed on the surface of the stage 1501, and a spacer 1512s adjacent to the source S is formed on the surface of the wide recess 1500 The surface of the substrate 200" may be a cladding layer 210", and the underlying layer 210" is a Schottky barrier layer 220". Note that in this embodiment, the surface of the platform 1501 is a cladding layer 210", a wide depression 1500 The surface is also a cladding layer 201". The method of forming the structure of Figure 15a includes first providing a substrate 200" having a wide recess 1500 and a land 1501, followed by forming a first patterned photoresist layer 1510, and then forming spacers 1512d/1512s. For detailed application methods, reference may be made to FIGS. 2a, 2b, 3 to 5, and 5a of the foregoing first embodiment.

After forming the structure of FIG. 15a, referring to the methods of FIG. 6b, FIG. 7b, and FIG. 8b of the foregoing first embodiment, the gate opening 1516s and the opening 1516d adjacent to the drain are defined by the spacer 1512d/1512s, and formed as shown in the figure. The structure shown in 15b. As shown, openings 1516s and 1416d are formed in the alternative photoresist layer 1515, which defines a bottom dimension of the gate. Note that the opening 1516s has a certain depth to expose the Schottky barrier layer 220". The opening 1516d does not expose the Schottky barrier layer 220" only to expose the overlying cladding layer 210".

After the structure of Fig. 15b is formed, the structure of the T-type gate 1520 as shown in Fig. 15c can be formed by referring to the methods of Figs. 9, 10, and 11 of the first embodiment. As shown in FIG. 15c, a semiconductor structure includes a substrate 200" having a drain D, a source S and a gate 1520 between the drain D and the source S, and the substrate 200" further includes a substrate surface 200"a, The substrate surface 200"a has a wide recess 1500 between the drain D and the source S and is closer to the source S, and at least one notch (ie, the aforementioned opening 1516d) is formed between the wide recess 1500 and the drain D. The 200" further includes an epitaxial structure, the epitaxial structure includes a cladding layer 210", and the wide recess 1500 and the notch 1516d are formed in the cladding layer 210". Note that the notch 1516d does not expose the Schottky barrier layer 220" under the cladding layer 210". The surface of the wide recess 1500 further includes a gate opening (i.e., the aforementioned opening 1516s), and the gate 1520 extends upward from the gate opening 1516s. This gap 1516d can be used to adapt the breakdown voltage of the transistor in the high power amplifier without sacrificing the cutoff frequency and gain of the transistor to achieve optimum power amplification performance. Fig. 16 shows a fifth embodiment of the multi-notch of the present invention, which can be implemented by referring to the above description.

17a to 17d show a sixth embodiment of the present invention, which is a method of manufacturing a T-type gate. As shown in Figure 17a, the step begins with a substrate 1700 that already includes each epitaxial layer. The substrate 1700 includes a plurality of drain electrodes D protruding from the surface of the substrate 1700. There is a wide recess 1700a between the drain D and the source S. The surface of the substrate 1700 further includes a spacer 1701 and a spacer 1702 in a region of the wide recess 1700a and closer to the source S. An opening 1705 is formed between the spacer 1701 and the spacer 1702 to expose the surface of the substrate 1700 on the wide recess 1700a. The bottom of the opening 1705 defines the gate length Lg of the T-type gate. The surface of the substrate 1700 further includes a patterned photoresist layer 1703 adjacent to the spacer 1701 and the spacers 1702. The patterned photoresist layer 1703 covers most of the region of the substrate 1700, the drain D and the source S, but does not cover the spacer 1701, the spacer 1702, and the opening 1705. The structure illustrated in Figure 17a can be fabricated by reference to the method of forming the structure of Figure 5 previously described.

Note that in this embodiment, as shown, the preferred width w of the spacer 1701 or the spacer 1702 is between 0.05 and 0.2 μm, and the distance L between the outer side of the spacer 1701 and the outer side of the spacer 1702 is The preferred range is between 0.25 and 0.7 μm or less, such as between 0.1 and 0.2 μm. The gate length Lg, the distance L between the outer side of the spacer 1701 and the outer side of the spacer 1702, and the width w of the spacer 1701 or the spacer 1702 substantially conform to the following formula: Lg = L - 2w. From this, it is understood that the gate length Lg in accordance with the expectation can be produced by appropriately adjusting the width w of the spacer.

Next, as shown in FIG. 17b, a flat photoresist layer 1706 is formed to cover the structure shown in FIG. 17a, and the flat photoresist layer 1706 fills the opening 1705 at the same time. The thickness of the flat photoresist layer 1706 is preferably 0.3 to 2 μm. Note that the patterned photoresist layer 1703 is different from the flat photoresist layer 1706, and the patterned photoresist layer 1703 can be made of a material different in sensitivity to the flat photoresist layer 1706.

Next, referring to FIG. 17c, the flat photoresist layer 1706 is exposed and developed by optical lithography to expose the opening 1705 and form a larger opening 1707 over the opening 1705. As shown, the opening 1707 is formed by the inclined photoresist walls A1 and A2.

Referring to Figure 17d, a metallic conductive material is deposited in opening 1705 and opening 1707. This step can be accomplished using conventional directional deposition metal evaporation methods. Note that, as shown, the oblique orientation of the photoresist walls A1 and A2 will prevent the deposited metal from being tightly bonded to the photoresist walls A1 and A2, facilitating subsequent photoresist peeling. In contrast, as illustrated, the oblique direction of the spacer 1701 or the spacer 1702 will cause the deposited metal to be easily bonded to the spacer 1701 or the spacer 1702, facilitating the formation of a structurally stable T-gate. Next, the planar photoresist layer 1706 and the patterned photoresist layer 1703 are removed in a suitable manner, such as a liquid phase etching or development process, to form a structure as shown in Figure 17d.

Referring to Figure 17d, a semiconductor structure is shown comprising a substrate 1700 having a drain D, a source S and a gate G between the drain D and the source S. The substrate 1700 further includes a pair of spacers 1701/1702 adjacent to the gate G, and the pair of spacers 1701/1702 define a gate length Lg of the gate G. The gate G further includes a narrow root portion 1710r and a wide head portion 1710h. The pair of spacer walls 1701/1702 are located on the same plane as the narrow root portion 1710r. The pair of spacer walls 1701/1702 are adjacent to the narrow root portion 1710r, and the pair of spacers 1701/1701 The wide head portion 1710h is supported together with the narrow root portion 1710r. The substrate 1700 further includes a substrate surface of 1700 s, a wide recess 1700a on the surface of the substrate between the drain D and the source S, and the pair of spacers 1701/1702 and the narrow root 1710r are tied in the wide recess 1700a.

The above is only the preferred embodiment of the present invention. The present invention also encompasses many other embodiments as described in the scope of the patent application of the present invention. Equivalent changes or modifications made without departing from the spirit of the invention are intended to be included within the scope of the appended claims.

Claims (37)

 A method for forming a gate structure includes: forming a first patterned photoresist layer on a substrate; forming a spacer on a sidewall of the first patterned photoresist layer, wherein the spacer comprises a curved portion; Removing a first patterned photoresist layer; forming an alternative photoresist layer on the substrate, inserting the spacer in the replacement photoresist layer to expose the curved portion; and removing the spacer to form an opening In the alternative photoresist layer, wherein the opening defines a bottom dimension of a gate.    The method of claim 1, further comprising forming a gate insulating layer along the surface of the opening and forming a gate conductive layer on the gate insulating layer.    The method of claim 1, further comprising: forming a conformal insulating layer covering the opening and the replacement photoresist layer; forming a conductive layer covering the conformal insulating layer; and forming a third patterned photoresist On the conductive layer, the third patterned photoresist defines the top shape of the gate.    The method of claim 3, further comprising: removing the conductive layer to form a gate conductive layer by using the third patterned photoresist as a mask; and masking the third patterned photoresist The cover removes a portion of the conformal insulating layer to form a gate insulating layer.   The method of forming the method of claim 4, further comprising: simultaneously removing the residual _{Shirley Pan/leetsai} the second photoresist layer and the remaining first patterned photoresist layer and the third patterned photoresist to expose the The gate is on the substrate.  The method of claim 1, wherein the substrate comprises at least one drain and at least one source protrudes from a surface of the substrate, the first patterned photoresist layer covers the drain and the source, and the first A patterned photoresist layer has a sidewall adjacent to the source and away from the drain, the sidewall being interposed between the source and the drain.    The method of claim 2, further comprising forming a notch at the bottom of the opening to expose an epitaxial layer inside the substrate before forming the gate insulating layer.    The method of forming of claim 2, wherein the gate is a T-type gate.    The method of forming of claim 2, wherein the opening has a size ranging from 50 angstroms to 6,000 angstroms.    A method for forming a gate structure includes: forming a first patterned photoresist layer on a substrate; forming a spacer on a sidewall of the first patterned photoresist layer, wherein the spacer comprises a curved portion; Forming a second photoresist layer on the substrate, the second photoresist layer covering the first patterned photoresist layer and the spacer; removing a portion of the second photoresist layer and a portion of the first photoresist layer And exposing the bent portion of the spacer; and removing the spacer to form an opening in the remaining second photoresist layer and the first patterned photoresist layer, wherein the opening defines a bottom of a gate size.    The method of forming the method of claim 10, further comprising forming a gate insulating layer along the surface of the opening and forming a gate conductive layer on the gate insulating layer.    The method of claim 10, further comprising: forming a conformal insulating layer covering the opening and the remaining second photoresist layer and the remaining first photoresist layer; forming a conductive layer covering the conformal layer An insulating layer; and forming a third patterned photoresist on the conductive layer, the third patterned photoresist defining a top shape of the gate.    The method of claim 12, further comprising: removing the conductive layer to form a gate conductive layer by using the third patterned photoresist as a mask; and masking the third patterned photoresist The cover removes a portion of the conformal insulating layer to form a gate insulating layer.    The method of claim 13, further comprising: simultaneously removing the remaining second photoresist layer and the remaining first patterned photoresist layer and the third patterned photoresist to expose the gate to the substrate on.    The method of claim 10, wherein the substrate comprises at least one drain and at least one source protrudes from a surface of the substrate, the first patterned photoresist layer covers the drain and the source, and the gap A wall is between the source and the drain.    The method of claim 15, further comprising forming a notch at the bottom of the opening to expose an epitaxial layer inside the substrate before forming the gate insulating layer, the gap being between the gate and the gate Between bungee jumping.    The method of forming of claim 11, wherein the gate is a T-type gate.    The method of forming of claim 11, wherein the opening has a size ranging from 50 angstroms to 6,000 angstroms.    A semiconductor structure comprising: a substrate having a drain, a source, and a gate between the drain and the source, wherein the substrate further comprises a substrate surface, the substrate surface having a gap The drain is between the gate and the gate.    The semiconductor structure of claim 19, wherein the substrate further comprises an epitaxial structure, the epitaxial structure comprising a cladding layer formed in the cladding layer and exposing a shawl under the cladding layer Special base barrier layer.    The semiconductor structure of claim 19, wherein the substrate surface further comprises a gate opening, the gate extending upward from the gate opening, the gate opening having substantially the same depth as the gap.    The semiconductor structure of claim 19, wherein the gate is a T-type gate.    A semiconductor structure comprising: a substrate having a drain, a source and a gate between the drain and the source, wherein the substrate further comprises a substrate surface, the substrate surface having a wide recess A gap is formed between the drain and the source and a bottom surface of the wide recess, wherein the gap is between the gate and the drain.    The semiconductor structure of claim 23, wherein the substrate further comprises an epitaxial structure, the epitaxial structure comprising a cladding layer, the wide recess and the gap being formed in the cladding layer, wherein the recess exposes the A Schottky barrier under the cladding.    The semiconductor structure of claim 23, wherein the bottom surface of the wide recess further comprises a gate opening, the gate extending upward from the gate opening, the gate opening having substantially the same depth as the gap.    The semiconductor structure of claim 23, wherein the gate is a T-type gate.    A semiconductor structure comprising: a substrate having a drain, a source and a gate between the drain and the source, wherein the substrate further comprises a substrate surface, the substrate surface having a wide recess A gap between the drain and the source and at least one gap is formed between the drain and the drain.    The semiconductor structure of claim 27, wherein the substrate further comprises an epitaxial structure, the epitaxial structure comprising a cladding layer, the wide recess and the gap being formed in the cladding layer.    The semiconductor structure of claim 27, wherein the gap does not expose a Schottky barrier layer under the cladding layer.    The semiconductor structure of claim 27, wherein the surface of the wide recess further comprises a gate opening, the gate extending upwardly from the gate opening.    The semiconductor structure of claim 27, wherein the gate is a T-type gate.    The semiconductor structure of claim 27, wherein the plurality of notches are plural.    A semiconductor structure comprising: a substrate having a drain, a source, and a gate between the drain and the source, wherein the substrate further includes a pair of spacers adjacent to the gate, the pair The spacer system defines the gate length of the gate.    The semiconductor structure of claim 33, wherein the gate further comprises a narrow root portion and a wide head portion, the spacer wall and the narrow root portion being located on a same plane, the pair of spacer walls being adjacent to the narrow root portion, the pair of spacer walls and The narrow roots collectively support the wide head.    The semiconductor structure of claim 33, further comprising a substrate surface having a wide recess between the drain and the source, the pair of spacers and the narrow root being tied to the wide recess in.    The semiconductor structure of claim 33, wherein the respective widths of the pair of spacers are between 0.05 and 0.2 μm.    The semiconductor structure of claim 33, wherein a distance between the outer side of the spacer of one of the pair and the outer side of the other of the spacer is between 0.25 and 0.7 μm or between 0.1 and 0.2 μm.