CN104851788B - A kind of production method of the T-type grid of GaAs based transistor - Google Patents
A kind of production method of the T-type grid of GaAs based transistor Download PDFInfo
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- CN104851788B CN104851788B CN201510206635.1A CN201510206635A CN104851788B CN 104851788 B CN104851788 B CN 104851788B CN 201510206635 A CN201510206635 A CN 201510206635A CN 104851788 B CN104851788 B CN 104851788B
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- 229910001218 Gallium arsenide Inorganic materials 0.000 title claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 58
- 238000005530 etching Methods 0.000 claims abstract description 51
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 229910052751 metal Inorganic materials 0.000 claims abstract description 10
- 239000002184 metal Substances 0.000 claims abstract description 10
- 238000002360 preparation method Methods 0.000 claims abstract description 8
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 7
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims description 14
- MUBZPKHOEPUJKR-UHFFFAOYSA-N Oxalic acid Chemical compound OC(=O)C(O)=O MUBZPKHOEPUJKR-UHFFFAOYSA-N 0.000 claims description 9
- KRKNYBCHXYNGOX-UHFFFAOYSA-N citric acid Chemical compound OC(=O)CC(O)(C(O)=O)CC(O)=O KRKNYBCHXYNGOX-UHFFFAOYSA-N 0.000 claims description 9
- 239000011248 coating agent Substances 0.000 claims description 7
- 238000000576 coating method Methods 0.000 claims description 7
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 6
- KDYFGRWQOYBRFD-UHFFFAOYSA-N succinic acid Chemical compound OC(=O)CCC(O)=O KDYFGRWQOYBRFD-UHFFFAOYSA-N 0.000 claims description 6
- 238000007740 vapor deposition Methods 0.000 claims description 6
- 238000003384 imaging method Methods 0.000 claims description 5
- 150000002500 ions Chemical class 0.000 claims description 5
- 238000001312 dry etching Methods 0.000 claims description 4
- 238000000034 method Methods 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 3
- 230000003667 anti-reflective effect Effects 0.000 claims description 3
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 229910052804 chromium Inorganic materials 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 230000003628 erosive effect Effects 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 229910052750 molybdenum Inorganic materials 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 235000006408 oxalic acid Nutrition 0.000 claims description 3
- 238000007747 plating Methods 0.000 claims description 3
- 229910052697 platinum Inorganic materials 0.000 claims description 3
- 238000004544 sputter deposition Methods 0.000 claims description 3
- 239000001384 succinic acid Substances 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 239000003795 chemical substances by application Substances 0.000 claims 1
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 abstract description 20
- 230000000694 effects Effects 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 230000006641 stabilisation Effects 0.000 description 2
- 238000011105 stabilization Methods 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 230000004304 visual acuity Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 241000826860 Trapezium Species 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008033 biological extinction Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- KPUWHANPEXNPJT-UHFFFAOYSA-N disiloxane Chemical class [SiH3]O[SiH3] KPUWHANPEXNPJT-UHFFFAOYSA-N 0.000 description 1
- 239000000975 dye Substances 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66431—Unipolar field-effect transistors with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Weting (AREA)
Abstract
It is that anti-reflecting layer and the first photoresist are sequentially formed on GaAs (GaAs) base substrate the invention discloses a kind of production method of the T-type grid of GaAs based transistor, the aobvious open region that the exposed development formation width of the first photoresist is 0.13 0.18um；It is coated with the second photoresist, the etching window of T-type grid is collectively formed after exposed development with the aobvious open region of the first photoresist, the T-type grid that line width is 0.13 0.18um are formed by deposited metal.The anti-reflecting layer of the present invention is formed using DUO248 preparations, and photoresist and anti-reflecting layer carry out wet type stripping by CLK 888, avoids damage of the dry type stripping to gallium arsenide substrate, at low cost, production capacity is high, is suitable for production application.
Description
Technical field
The present invention relates to semiconductor technologies, more particularly to a kind of production method of the T-type grid of GaAs based transistor.
Background technology
GaAs (GaAs) is second generation semiconductor, has high saturated electrons rate, high electron mobility, high-breakdown-voltage
Etc. excellent electrology characteristic, the semiconductor devices high frequency of making, high temperature, low temperature performance well, noise is small, and capability of resistance to radiation is strong, extensively
It is general to be suitable for the fields such as integrated circuit, infrared light-emitting diode, semiconductor laser and solar cell.Wherein GaAs base is high
Electron mobility transistor (GaAs HEMT) unique structure, has the characteristics that high power gain, high efficiency, low-power, in crystal
It is more and more noticeable in the application of pipe.
The making of the grid of HEMT has vital influence to the cutoff frequency of device.In general, grid length is smaller,
Gate resistance is lower, then the cutoff frequency of device is higher.Small grid length and low gate resistance in order to balance, bottom lengths are small and sectional area is big
T-type grid structure be widely used, on the basis of this structure, grid length can be fabricated into micro-nano rank.
Development can be exposed by lithographic equipment combination photoresist by making the T-type grid of reduced size, be formed after T-type grid
Again photoresist is removed by way of dry type stripping.For GaAs base substrate, dry type stripping plasma-based used can make it
At plasma damage, cause end properties poor.
Invention content
It is an object of the invention to overcome the deficiency of the prior art, a kind of GaAs base of 0.13-0.18um grid lengths is provided
The production method of the T-type grid of transistor.
The technical solution adopted by the present invention to solve the technical problems is：A kind of system of the T-type grid of GaAs based transistor
Make method, includes the following steps：
1) GaAs (GaAs) base substrate is provided, in forming an anti-reflecting layer on substrate, wherein the anti-reflecting layer is
It is coated by DUO248 preparations, specifically, DUO248 preparations are the products of honeywell companies production；
2) in coating the first photoresist on anti-reflecting layer, the exposed development formation width of the first photoresist is 0.13-0.18um's
Lower etching window；
3) the second photoresist is coated above above structure, the second photoresist of removal corresponds in the part of lower etching window and formation
Window is etched, wherein the width of upper etching window is more than lower etching window, upper etching window and lower etching window-shaped are at T-type grid
Etching window；
4) anti-reflecting layer of etching beneath window is removed to expose substrate, and etches the section substrate to form groove；
5) in etching in window using groove as bottom surface deposited metal, T-type grid is formed；
6) separating process is cutd open using wet type and removes anti-reflecting layer, the first photoresist and the second photoresist, wherein remover is by CLK-
888 are mixed to prepare with hydrogen peroxide, specifically, CLK-888 preparations are the products of JT-baker companies production.
Preferably, after DUO248 preparations coating at 110-140 DEG C soft roasting 1-5min, and it is hard at 180-220 DEG C
Roasting 1-5min is to form the anti-reflecting layer.
Preferably, first photoresist is the positive photoresists of KrF to match with 248nm light, it is exposed through KrF equipment aobvious
Shadow.
Preferably, in step 2), etching critical dimension (CD) is 0.15um.
Preferably, in step 4), the anti-reflecting layer of the etching beneath window is removed by dry-etching, and etching is critical
Size (CD) is 0.16un.
Preferably, second photoresist is that the I-line to match with 365nm light bears photoresist；The upper etching window is institute
State what the second photoresist was formed by I-line equipment exposure imagings, width 0.7-1.1um.
Preferably, the groove of the substrate is formed by wet etching, etch depth 0.02-0.08um, etching solution tool
Body is one kind or combinations thereof in phosphoric acid, oxalic acid, citric acid, succinic acid.
Preferably, the metal for forming T-type grid includes Ti, Ni, Cu, Al, Pt, W, Mo, Cr, Au or above-mentioned metal
Combination layer, be magnetic control sputtering plating, ion vapor deposition, arc ions vapor deposition or chemical vapor deposition by way of be formed in the erosion
It carves in window.
Preferably, in step 6), the temperature of the remover is 55-70 DEG C, and the volume fraction of wherein hydrogen peroxide is
2.5-3.5%.
The beneficial effects of the invention are as follows：
1, the antireflection preparation with high extinction effect that DUO248 is made of siloxane polymer and organic dyestuff, is adopted
Anti-reflecting layer is formed with DUO248, can be effectively reduced during exposure imaging becomes photoresist figure because of photoresist standing wave effect
Difference increases resolving power, and auxiliary KrF lithographic equipments show open region with the photoresist for forming the stabilization of minimum dimension, as T-type grid
Window is etched, the T-type grid of 0.13-0.18um can be made.
2, DUO248 and photoresist can be mixed with hydrogen peroxide to carry out disposable wet type stripping by CLK-888, be avoided
Plasma damage of the dry etching to gallium arsenide substrate.
3, the etching window of 0.13-0.18um small size T-type grid, equipment investment are formed using 248nm KrF lithographic equipments
Low, production capacity is high, can reduce production cost, is suitable for production application.
Description of the drawings
Fig. 1 is the flow chart of production method of the present invention.
Specific implementation mode
Invention is further described in detail with reference to the accompanying drawings and embodiments.The present invention each attached drawing be only illustrate with
It is easier to understand the present invention, specific ratio can be adjusted according to design requirement.Opposed member in figure described in text
Upper and lower relation, will be understood that in those skilled in the art refer to component relative position for, therefore can all overturn and be in
Existing identical component, this should all belong to the range disclosed by this specification.
With reference to the production method flow chart of the a-e present invention in figure 1.As shown in a in Fig. 1, a GaAs base substrate 1 is provided,
In forming an anti-reflecting layer 2 on substrate, and in coating the first photoresist 3 in anti-reflective layer 2.Anti-reflecting layer 2 is by DUO248 preparations
Formed by modes such as spin coating, sprayings, after coating at 110-140 DEG C soft roasting 1-5min, and the hard baking 1- at 180-220 DEG C
5min.As a preferred embodiment, can be specifically soft roasting 3min at 130 DEG C, and at 210 DEG C hard baking 3min with into
Row solidification.Then, in coating the first photoresist 3 on anti-reflecting layer 2, the first photoresist 3 is the positive photoresists of KrF to match with 248nm light.
As shown in b in Fig. 1, using 3 exposure imaging of the first photoresist of 248nm KrF lithographic equipments pair.248nm KrF photoetching is set
Standby is with F2It is exposed for light source with the laser generated after Kr gas ionizations, silicon wafer is being frequently used for using standardization setting
The upper photoresist for making 0.13um line widths retains region, and distance (photoresist shows open region) is 0.18um between line, in DUO248 anti-reflective
It penetrates under the auxiliary of layer, by adjusting etching critical dimension (CD) and luminous energy, formation width can be less than on the first photoresist 3
The lower etching window 31 (being the aobvious open region of the first photoresist 3) of 0.18um, lower etching 31 bottom of window is exposed antireflection
Layer 2.The anti-reflecting layer that DUO248 is formed, can be effectively reduced during exposure imaging makes photoresist figure because of photoresist standing wave effect
It is deteriorated, increases resolving power, the photoresist that auxiliary KrF lithographic equipments form the stabilization of 0.13-0.18um line widths shows open region.Due to
First photoresist 3 is positive photoresist, is formed by the inverted trapezoidal structure that lower etching window 31 is wide at the top and narrow at the bottom.
Then, the second photoresist 4 is coated above above structure, the second photoresist 4 is that the I-line to match with 365nm light is born
Photoresist, concrete model can be AZ companies nLOF5510.It is exposed by the second photoresist of 365nm I-line lithographic equipments pair 4
Etching window 41 (being the aobvious open region of the second photoresist 4) in the part of corresponding lower etching window 41 and formation is got rid of in development,
The width of upper etching window 41 is more than lower etching window 31, and as an implementation, width is specifically as follows 0.7-
1.1um.The etching window of T-type grid is collectively formed in upper etching window 31 and lower etching window 41.Since the second photoresist 4 is negative light
Resistance is formed by the trapezium structure that etching window 41 is up-narrow and down-wide.
As shown in c in Fig. 1, the anti-reflecting layer 2 of etching beneath window is removed to expose substrate 1, and etch the section substrate 1
To form groove 11.The anti-reflecting layer of etching beneath window can be removed by dry-etching, and etching critical dimension (CD) is compared with the
The photoetching of one photoresist increases 0.01um so that the width of groove 11 is slightly larger than the line width of T-type grid, it is ensured that T-type grid are fully located at groove
Within.As a preferred embodiment, the etching critical dimension (CD) of corresponding first photoresist can be 0.15um, groove
Etching critical dimension (CD) can be specifically 0.16um.Groove 11 is formed by wet etching, etching solution can be specifically phosphoric acid,
One kind or combinations thereof in oxalic acid, citric acid, succinic acid.The depth of groove 11 is 0.02-0.08um.
As shown in d in Fig. 1, in etching in window with groove 11 as bottom surface deposited metal, T-type grid 5, T-type are formed
The metal of grid includes the combination layer of Ti, Ni, Cu, Al, Pt, W, Mo, Cr, Au or above-mentioned metal, be by magnetic control sputtering plating, from
The mode of son vapor deposition, arc ions vapor deposition or chemical vapor deposition is formed in etching window.Due to the width of upper etching window 41
Degree is more than the width of lower etching window 31, forms the structure of T-type, the bottom line width contacted with substrate 1 is 0.13-
0.18um。
As shown in e in Fig. 1, stripping anti-reflecting layer 2, the first photoresist 3 and the second photoresist 4.Specifically, anti-reflecting layer 2, first
The synchronous removal of wet type stripping may be used in photoresist 3 and the second photoresist 4, and remover is mixed to prepare by CLK-888 and hydrogen peroxide,
As a preferred embodiment, the volume fraction of hydrogen peroxide is 2.5-3.5% in remover.The temperature in use of remover
It is 55-70 DEG C.Wet type stripping conditions are mild, to GaAs base substrate without effect, avoid dry type stripping to GaAs base substrate 1
Plasma damage.
A kind of making side of the T-type grid for GaAs based transistor that above-described embodiment only is used for further illustrating the present invention
Method, but the invention is not limited in embodiments, it is every according to the technical essence of the invention to any letter made by above example
Single modification, equivalent variations and modification, each fall in the protection domain of technical solution of the present invention.
Claims (6)
1. a kind of production method of the T-type grid of GaAs based transistor, it is characterised in that include the following steps：
1) a GaAs base substrate is provided, in forming an anti-reflecting layer on substrate, wherein the anti-reflecting layer is by DUO248 systems
Agent coats；
2) in coating the first photoresist on anti-reflecting layer, the lower erosion that the exposed development formation width of the first photoresist is 0.13-0.18um
Carve window；First photoresist is the positive photoresists of KrF to match with 248nm light, and development is exposed through KrF equipment；
3) the second photoresist is coated above above structure, the second photoresist of removal corresponds to be etched in the part of lower etching window and formation
Window, wherein the width of upper etching window is more than the erosion of lower etching window, upper etching window and lower etching window-shaped at T-type grid
Carve window；Second photoresist is that the I-line to match with 365nm light bears photoresist；The upper etching window is second light
Resistance is formed by I-line equipment exposure imagings, width 0.7-1.1um；
4) anti-reflecting layer of etching beneath window is removed to expose substrate, and etches the section substrate to form groove；
5) in etching in window using groove as bottom surface deposited metal, T-type grid is formed；
6) separating process is cutd open using wet type and removes anti-reflecting layer, the first photoresist and the second photoresist, wherein remover be by CLK-888 with
Hydrogen peroxide is mixed to prepare, and the temperature of the remover is 55-70 DEG C, and the volume fraction of wherein hydrogen peroxide is 2.5-3.5%.
2. manufacturing method according to claim 1, it is characterised in that：In 110-140 DEG C after the DUO248 preparations coating
Under soft roasting 1-5min, and at 180-220 DEG C hard baking 1-5min to form the anti-reflecting layer.
3. manufacturing method according to claim 1, it is characterised in that：In step 2), etching critical dimension is 0.15um.
4. production method according to claim 3, it is characterised in that：In step 4), the anti-reflective of the etching beneath window
It penetrates layer to remove by dry-etching, etching critical dimension is 0.16un.
5. manufacturing method according to claim 1, it is characterised in that：The groove of the substrate is formed by wet etching,
Etch depth is 0.02-0.08um, and etching solution is specifically one kind or combinations thereof in phosphoric acid, oxalic acid, citric acid, succinic acid.
6. manufacturing method according to claim 1, it is characterised in that：It is described formed T-type grid metal include Ti,
The combination layer of Ni, Cu, Al, Pt, W, Mo, Cr, Au or above-mentioned metal is by magnetic control sputtering plating, ion vapor deposition, arc ions vapor deposition
Or the mode of chemical vapor deposition is formed in the etching window.
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| CN201510206635.1A CN104851788B (en) | 2015-04-28 | 2015-04-28 | A kind of production method of the T-type grid of GaAs based transistor |
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| CN201510206635.1A CN104851788B (en) | 2015-04-28 | 2015-04-28 | A kind of production method of the T-type grid of GaAs based transistor |
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| CN107393959A (en) * | 2017-07-07 | 2017-11-24 | 西安电子科技大学 | GaN hyperfrequencies device and preparation method based on sag |
| WO2019090762A1 (en) * | 2017-11-13 | 2019-05-16 | 吴展兴 | Semiconductor structure and method for forming same |
| CN110211873B (en) * | 2019-04-23 | 2021-04-30 | 福建省福联集成电路有限公司 | Low-linewidth semiconductor device manufacturing method and semiconductor device |
| CN112038400B (en) * | 2020-04-30 | 2023-01-10 | 厦门市三安集成电路有限公司 | Method for manufacturing self-aligned double-groove gallium arsenide field effect transistor |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6268457B1 (en) * | 1999-06-10 | 2001-07-31 | Allied Signal, Inc. | Spin-on glass anti-reflective coatings for photolithography |
| CN1877794A (en) * | 2005-06-06 | 2006-12-13 | 中芯国际集成电路制造(上海)有限公司 | Method for mixed production of 90nm groove etching and 130nm groove etching |
| CN100421217C (en) * | 2004-01-29 | 2008-09-24 | 罗姆及海斯电子材料有限公司 | T-gate formation |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7955782B2 (en) * | 2008-09-22 | 2011-06-07 | Honeywell International Inc. | Bottom antireflective coatings exhibiting enhanced wet strip rates, bottom antireflective coating compositions for forming bottom antireflective coatings, and methods for fabricating the same |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6268457B1 (en) * | 1999-06-10 | 2001-07-31 | Allied Signal, Inc. | Spin-on glass anti-reflective coatings for photolithography |
| CN100421217C (en) * | 2004-01-29 | 2008-09-24 | 罗姆及海斯电子材料有限公司 | T-gate formation |
| CN1877794A (en) * | 2005-06-06 | 2006-12-13 | 中芯国际集成电路制造(上海)有限公司 | Method for mixed production of 90nm groove etching and 130nm groove etching |
Non-Patent Citations (2)
| Title |
|---|
| "An Anthracene-Organosiloxane Spin On Antirefective Coating for KrF Lithography";Joseph Kenndy etal;《Advances in Resist Technology and Processing XX》;20030630;第5039卷;正文第144页至第150页 * |
| "关于多孔MSQ Dual Damascene蚀刻/灰化工艺---为更低损伤和更低k值得多方面损伤评价和化学性质优化";Shin Okamoto etal;《电子工业专用设备》;20030630(第104期);全文 * |
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