CN102543716B - The forming method of blocking layer of metal silicide - Google Patents

The forming method of blocking layer of metal silicide Download PDF

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Publication number
CN102543716B
CN102543716B CN201210061075.1A CN201210061075A CN102543716B CN 102543716 B CN102543716 B CN 102543716B CN 201210061075 A CN201210061075 A CN 201210061075A CN 102543716 B CN102543716 B CN 102543716B
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layer
silicon
metal silicide
substrate
silicon dioxide
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CN102543716A (en
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王卉
康军
令海阳
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Abstract

The present invention relates to a kind of forming method of blocking layer of metal silicide, comprise the following steps:One substrate is provided, there is in described substrate isolation structure, the substrate surface of described isolation structure both sides has first grid structure and second grid structure respectively, in the substrate of described first grid structure both sides, there is lightly-doped source drain implant;Deposition silicon-rich silicon dioxide silicon layer;First grid structure both sides are carried out with ion implanting, forms heavy-doped source drain implant;Deposition silylation layer;Coating photoresist, is lithographically formed first window, exposes described first grid structural region in described first window;Dry etching removes the silylation layer in first window;Wet etching removes the silicon-rich silicon dioxide silicon layer in first window;Remove photoresist.The present invention adopts the blocking layer of metal silicide of silicon-rich silicon dioxide silicon layer and silylation layer, and silicon rich silicon dioxide is compared silicon dioxide and had compared with high extinction coefficient, can reduce the damage to substrate for the plasma ultraviolet, thus improving the uniformity of threshold voltage.

Description

The forming method of blocking layer of metal silicide
Technical field
The present invention relates to semiconductor applications, particularly to a kind of forming method of blocking layer of metal silicide.
Background technology
Manufacture super large-scale integration in Self-Aligned Refractory silicide process, most active areas are by low electricity The refractory metal silicide of resistance covers.But some regions, such as high resistance polysilicon and isolation active area are that to have infusibility gold Belong to silicide, these regions need barrier layer protected, needs first region in this section formation metallic silicon in silicide process Compound barrier layer (salicide block layer, SAB), will not be sent out with metals such as titanium or cobalts using blocking layer of metal silicide The characteristic of raw reaction, to prevent from forming metal silicide in subregion.
In super large-scale integration manufacturing process, refractory metal such as titanium, cobalt, nickel are often used as generating silicide.With When, silicon dioxide and silylation layer are widely used in barrier layer.The forming method of prior art blocking layer of metal silicide includes Following steps:As shown in Figure 1a, a substrate 100 is provided, there is isolation structure 101 adjacent for isolating in described substrate 100 Device cell, described isolation structure 101 both sides are respectively first grid structure 102 and second grid structure 103, the described first grid In the substrate of pole structure 102 both sides, there is lightly-doped source drain implant 104;Described first grid structure 102 includes gate oxidation Layer 1021, the polysilicon gate 1022 on grid oxic horizon 1021 and the side wall being located at polysilicon gate both sides 1023, second grid structure 103 includes grid oxic horizon 1031, the polysilicon gate on grid oxic horizon 1031 1032 and be located at polysilicon gate both sides side wall 1033;As shown in Figure 1 b, deposit a silicon dioxide layer on the substrate 100 105, the step of described deposited silicon dioxide layer 105 adopts N2O and SiH4 as reacting gas, the volume of described N2O and SiH4 Than for 15: 1;As illustrated in figure 1 c, first grid structure 102 both sides are carried out with ion implanting, forms heavy-doped source drain implant 106, and execute rapid thermal treatment;As shown in Figure 1 d, deposit a silylation layer 107;As shown in fig. le, photoresist 108, photoetching are applied Form first window 108a, in described first window 108a, expose described first grid structure 102 and its heavy doping of both sides Source and drain injection region 106;As shown in Figure 1 f, dry etching removes the silylation layer 107 in first window 108a;As shown in Figure 1 g, wet Method etching removes the silica 1 05 in first window 108a, as shown in figure 1h, removes photoresist 108, is formed by silicon dioxide Layer 105 and the blocking layer of metal silicide structure of silylation layer 107 composition.
Silicon dioxide in blocking layer of metal silicide in the plasma etch process of dry etching, reaction chamber internal memory In high-frequency ac voltage, substrate, minority carrier generation speed does not catch up with change in voltage, and device is in deep spent condition.As figure Shown in 1i, the electron-hole pair that plasma generation ultraviolet excites is under AC field to grid oxic horizon taking PMOS as a example Injection, finally makes hole be captured in grid oxic horizon, thus leading to PMOS threshold voltage to become big, and threshold voltage is uneven Even.
Content of the invention
It is an object of the invention to provide a kind of forming method of blocking layer of metal silicide, to improve the uniform of threshold voltage Property.
The technical solution of the present invention is a kind of forming method of blocking layer of metal silicide, comprises the following steps:
One substrate is provided, there is in described substrate isolation structure, difference shape on the substrate surface of described isolation structure both sides Become to have first grid structure and second grid structure, have in the substrate of described first grid structure both sides and source and drain injection is lightly doped Area;
Silicon-rich silicon dioxide silicon layer is deposited on substrate;
First grid structure both sides are carried out with ion implanting, forms heavy-doped source drain implant, and execute rapid thermal treatment;
Deposit a silylation layer;
Coating photoresist, be lithographically formed first window, expose in described first window described first grid structure and its The heavy-doped source drain implant of both sides;
Dry etching removes the silylation layer in first window;
Wet etching removes the silicon-rich silicon dioxide silicon layer in first window;
Remove photoresist, form blocking layer of metal silicide structure.
As preferred:The step of described deposition silicon-rich silicon dioxide silicon layer adopts N2O and SiH4As reacting gas.
As preferred:Described N2O and SiH4Flow-rate ratio be 8.1: 1-8.5: 1.
As preferred:The thickness of described silicon-rich silicon dioxide silicon layer is 315-385 angstrom.
As preferred:The thickness of described silylation layer is 1200 angstroms.
As preferred:The step of described dry etching silylation layer adopts CF gas.
As preferred:Described wet etching silicon-rich silicon dioxide silicon layer adopts HF solution.
Compared with prior art, the present invention adopts the metal silication of ground floor silicon-rich silicon dioxide silicon layer and second layer silylation layer Thing barrier layer, described silicon rich silicon dioxide silicon dioxide compared to existing technology has compared with high extinction coefficient, can reduce dry method and carve The impact to substrate for erosion process plasma ultraviolet (Plasma UV), therefore can effectively stop plasma damage, improve The uniformity of threshold voltage.
Brief description
Fig. 1 a-1h is the profile of each processing step in prior art blocking layer of metal silicide forming method.
Fig. 1 i is schematic diagram in dry etching for the prior art blocking layer of metal silicide.
Fig. 2 is the process chart of blocking layer of metal silicide forming method of the present invention.
Fig. 3 a-3h is the profile of each processing step in blocking layer of metal silicide forming method of the present invention.
Specific embodiment
The present invention is further detailed in conjunction with the accompanying drawings below:
Elaborate a lot of details in order to fully understand the present invention in the following description.But the present invention can be with Much it is different from alternate manner described here to implement, those skilled in the art can be in the situation without prejudice to intension of the present invention Under do similar popularization, therefore the present invention is not embodied as being limited by following public.
Secondly, the present invention is described in detail using schematic diagram, when describing the embodiment of the present invention in detail, for purposes of illustration only, table Show that the profile of device architecture can be disobeyed general ratio and be made partial enlargement, and described schematic diagram is example, its here should not Limit the scope of protection of the invention.Additionally, the three-dimensional space of length, width and depth should be comprised in actual fabrication.
Fig. 2 shows the process chart of blocking layer of metal silicide forming method of the present invention
Refer to shown in Fig. 2, in the present embodiment,
In step 201, as shown in Figure 3 a, a substrate 300 is provided, there is in described substrate 300 isolation structure 301, institute First grid structure 302 and second grid structure 303 are respectively formed with the substrate surface stating isolation structure 301 both sides, described First grid structure 302 both sides have lightly-doped source drain implant 304;Described first grid structure 302 includes grid oxic horizon 3021st, it is located at the polysilicon gate 3022 on grid oxic horizon 3021 and the side wall 3023 being located at grid both sides, described the Two grid structures 303 include grid oxic horizon 3031, the polysilicon gate 3032 on grid oxic horizon 3031, Yi Jiwei In the side wall 3033 of grid both sides, described first grid can be for example control gate, and described second grid can be for example floating boom;
In step 202., as shown in Figure 3 b, silicon-rich silicon dioxide silicon layer (silicon rich is deposited on substrate 300 Oxide, SRO) 305, the step of described deposition silicon-rich silicon dioxide silicon layer 305 adopts N2O and SiH4As reacting gas, described N2O And SiH4Flow-rate ratio be 8.1: 1-8.5: 1, in the present embodiment, described N2O and SiH4Flow-rate ratio be 8.3: 1, described Silicon-rich The thickness of silicon dioxide layer 305 is 315-385 angstrom;
In step 203, as shown in Figure 3 c, first grid structure 302 both sides are carried out with ion implanting, forms heavy-doped source Drain implant 306, and execute rapid thermal treatment;
In step 204, as shown in Figure 3 d, deposit a silylation layer 307, the thickness of described silylation layer 307 is 1200 angstroms;
In step 205, as shown in Figure 3 e, apply photoresist 308, be lithographically formed first window 308a, described first window Described first grid structure 302 and its heavy-doped source drain implant 306 of both sides is exposed in mouth 308a;Photoresist after graphically 308 regions being covered be the region of high resistant it is desirable to its surface can not form metal silicide, for this reason, needing shape on the area Become blocking layer of metal silicide;
In step 206, as illustrated in figure 3f, dry etching removes the silylation layer 307 in first window 308a, described dry method The step of etching silylation layer 307 adopts CF gas;
Compared with prior art, the present invention adopts the gold of ground floor silicon-rich silicon dioxide silicon layer 305 and second layer silylation layer 307 Belong to silicide barrier layer, described silicon rich silicon dioxide is compared silicon dioxide and had compared with high extinction coefficient, can reduce dry etching mistake The impact to substrate for the journey plasma ultraviolet (Plasma UV), therefore can effectively stop plasma damage, improve threshold value The uniformity of voltage.
In step 207, as shown in figure 3g, wet etching removes the silicon-rich silicon dioxide silicon layer 305 in first window 308a, Described wet etching silicon-rich silicon dioxide silicon layer 305 adopts HF solution.
In a step 208, as illustrated in figure 3h, remove photoresist 308, obtain silicon-rich silicon dioxide silicon layer 305 and silylation layer 307 The blocking layer of metal silicide structure of composition.
The foregoing is only presently preferred embodiments of the present invention, all impartial changes done according to scope of the invention as claimed with Modify, all should belong to the covering scope of the claims in the present invention.

Claims (5)

1. a kind of forming method of blocking layer of metal silicide is it is characterised in that comprise the following steps:
One substrate is provided, there is in described substrate isolation structure, the substrate surface of described isolation structure both sides is respectively formed with First grid structure and second grid structure, have lightly-doped source drain implant in the substrate of described first grid structure both sides;
Silicon-rich silicon dioxide silicon layer is deposited on substrate, described deposition silicon-rich silicon dioxide silicon layer adopts N2O and SiH4As reaction gas Body, described N2O and SiH4Flow-rate ratio be 8.1:1-8.5:1;
First grid structure both sides are carried out with ion implanting, forms heavy-doped source drain implant, and execute rapid thermal treatment;
Deposit a silylation layer;
Coating photoresist, is lithographically formed first window, exposes described first grid structure and its both sides in described first window Heavy-doped source drain implant;
Dry etching removes the silylation layer in first window;
Wet etching removes the silicon-rich silicon dioxide silicon layer in first window;
Remove remaining photoresist after the completion of etching, form blocking layer of metal silicide structure.
2. blocking layer of metal silicide according to claim 1 forming method it is characterised in that:Described silicon-rich silicon dioxide The thickness of silicon layer is 315-385 angstrom.
3. blocking layer of metal silicide according to claim 1 forming method it is characterised in that:The thickness of described silylation layer Spend for 1200 angstroms.
4. blocking layer of metal silicide according to claim 1 forming method it is characterised in that:Described dry etching silicon The step of alkane layer adopts CF gas.
5. blocking layer of metal silicide according to claim 1 forming method it is characterised in that:Described wet etching is rich Silicon silicon dioxide layer adopts HF solution.
CN201210061075.1A 2012-03-09 2012-03-09 The forming method of blocking layer of metal silicide Active CN102543716B (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103177956B (en) 2013-03-14 2015-11-25 上海华力微电子有限公司 A kind of deposition process of silica metal barrier layer
CN110534499B (en) * 2019-09-29 2021-05-25 武汉新芯集成电路制造有限公司 Semiconductor device and method for manufacturing the same
CN115377012B (en) * 2021-05-21 2024-04-19 北方集成电路技术创新中心(北京)有限公司 Method for forming semiconductor structure
CN115720479A (en) * 2022-11-23 2023-02-28 惠科股份有限公司 Quantum dot layer preparation method and display panel

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1263356A (en) * 1999-01-04 2000-08-16 国际商业机器公司 Method for forming frame-grid structure without boundary and device formed by using said method
US6900104B1 (en) * 2004-02-27 2005-05-31 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming offset spacer manufacturing for critical dimension precision
CN101064327A (en) * 2006-04-29 2007-10-31 联华电子股份有限公司 Image sensing element and method for making the same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1263356A (en) * 1999-01-04 2000-08-16 国际商业机器公司 Method for forming frame-grid structure without boundary and device formed by using said method
US6900104B1 (en) * 2004-02-27 2005-05-31 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming offset spacer manufacturing for critical dimension precision
CN101064327A (en) * 2006-04-29 2007-10-31 联华电子股份有限公司 Image sensing element and method for making the same

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