CN102054697A - Manufacturing method for device layer of semiconductor device - Google Patents
Manufacturing method for device layer of semiconductor device Download PDFInfo
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- CN102054697A CN102054697A CN2009101980985A CN200910198098A CN102054697A CN 102054697 A CN102054697 A CN 102054697A CN 2009101980985 A CN2009101980985 A CN 2009101980985A CN 200910198098 A CN200910198098 A CN 200910198098A CN 102054697 A CN102054697 A CN 102054697A
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Abstract
The invention discloses a manufacturing method for a device layer of a semiconductor device, which comprises the following steps: forming a grid electrode on a semiconductor device substrate; forming a nitride layer on the side wall of the grid electrode, lightly doping the grid electrode and the semiconductor substrate after depositing the surfaces of the grid electrode and the semiconductor substrate and adding an oxide layer; forming side wall of nitric oxide of the grid electrode, doping the grid electrode and the semiconductor substrate; depositing the semiconductor substrate so as to form a drain electrode and a source electrode; depositing metal on the surface of the grid electrode and the semiconductor substrate through a salicide method so as to form a metalized silicon layer; and quickly annealing and corroding the unreacted metal. The method provided by the invention can eliminate the influence of 'smile' type oxidation phenomenon on the performance change scope of the device and the performance of a switch.
Description
Technical field
The present invention relates to semiconductor fabrication, particularly a kind of device layer manufacture method of semiconductor device.
Background technology
Along with the extensive use of electronic equipment, semi-conductive manufacturing process has obtained development at full speed, and the characteristic size of semiconductor device is also more and more littler, and the device layer in the semiconductor device is made and also become more and more important.The device layer here refers to the making of carrying out source electrode, drain electrode and grid on Semiconductor substrate.
Fig. 1 a～1f is depicted as the sectional structure chart of the device layer making of prior art semiconductor device.The device layer manufacturing process of prior art semiconductor device may further comprise the steps:
Step 1 is carried out twin well process on semiconductor device substrates 101, the active area of definition CMOS as shown in Figure 1a, forms trap 100 on semiconductor device substrates 101.
In this step, two traps comprise a N trap and a P trap, usually adopt the technology of falling the dopant well to carry out, just the N well area of definition injects impurities such as phosphorus in semiconductor device substrates 101, follow-up formation P type complementary metal oxide semiconductors (CMOS) (PMOS), P well area in definition injects impurities such as boron, follow-up formation N type complementary metal oxide semiconductors (CMOS) (NMOS).
Here to describe in detail at P trap and the structure that forms on the P trap, to form NMOS, the structure that forms on the N trap is then ignored introduction, and step is basic identical.
Step 2 is carried out shallow-trench isolation (STI) technology on semiconductor device substrates 101, P trap and N trap are promptly isolated and isolate to the active area of Isolation CMOS in P trap 100, shown in Fig. 1 b, form STI102 in semiconductor device substrates 100.
In this step, the process that forms STI102 is: deposit isolating oxide layer and nitride layer successively in semiconductor device substrates 101 earlier, the photoresist layer that adopts exposure imaging technology to apply on nitride layer defines the STI figure, the photoresist layer that will have the STI figure obtains the STI groove as mask etch silicon nitride layer successively, isolating oxide layer and semiconductor device substrates 101, after then the STI groove being carried out the oxide filling, carry out the polishing of nitride layer and layer of isolation oxide, in semiconductor device substrates 101, obtain STI102.
Step 3 referring to Fig. 1 c, behind heavy successively gate oxide in the surface of the surface of semiconductor device substrates 101 and STI102 and polysilicon layer, adopts 10 pairs of polysilicon layers of ion injection method to mix in advance.
In this step, for NMOMS, the impurity of doping is phosphorus, and purpose is the grid conduction for the feasible final semiconductor device of making, and for PMOS, the impurity of doping is boron.
Step 4 after the employing photoetching process obtains grid 103, is carried out oxidation once more to the surface of grid 103 and Semiconductor substrate 101, forms and reoxidizes layer, does not embody in the drawings.
In this step, the process that adopts photoetching process to obtain grid 103 is: apply behind the photoresist layer light shield by having gate patterns to its exposure imaging, form gate patterns at photoresist layer, be mask with photoresist layer then with gate patterns, etch polysilicon layer and gate oxide form grid 103 successively;
In this step, the process that formation reoxidizes layer is: adopt chemical vapor deposition (CVD) method deposition to obtain oxide layer, obtain reoxidizing layer on the surface of grid 203 surfaces and semiconductor device substrates 101, this effect that reoxidizes layer is in order to repair in forming grid 103 processes the damage to semiconductor device substrates 101 surfaces.
Step 5 after forming the skew side wall on the grid 103 of oxidation once more, is injected 20 methods with ion the trap of semiconductor device substrates 101 is carried out light dope, referring to Fig. 1 d.
In the drawings, omitted the skew side wall, side wall generally adopts nitride to constitute, and the formation of skew side wall is the possibility of electric charge break-through between the source leakage that increases in order to prevent reducing of NMOS channel length in light dope technology.
Certainly, on specific implementation, also can not form the skew side wall.
In this step, for NMOS, the impurity that light dope adopts can be arsenic, makes the upper surface of semiconductor device substrates 101 become amorphous state, reduces the channel leakage stream effect between source-drain electrode.
Step 6 because grid 103 is subjected to injecting the bump of ion in the process of mixing, causes the lattice of silicon structure to damage, and for recovering damage, ion carries out quick thermal annealing process after injecting 20.
Step 7, referring to Fig. 1 e, behind grid 103 formation nitrogen oxide side walls 204, on semiconductor device substrate 101, just define source drain region, method with ion injection 30 is mixed to the semiconductor device substrates 101 of grid 103 and grid 103 both sides, forms drain electrode 301 and source electrode 302.
Step 8 referring to Fig. 1 f, adopts the method titanium deposition of self-aligned silicide (SAB), forms titanizing silicon layer 401, after carrying out short annealing then and handling, adopts chemical method to etch away unreacted titanium.
This step is in order to form contact hole, can be so that active area forms Metal Contact.
Like this, just having finished the device layer of semiconductor device makes.
But after the step 4 of above-mentioned manufacturing process was finished, the gate oxide thickness that obtains than thick at the thickness of its elsewhere of grid, was called " smile " type oxidative phenomena at the gate edge place here.This is because reoxidize in layer process surface of grid 103 and oxygen reaction in formation, make grid 103 surface oxidations, with the contact position of gate oxide, reoxidize layer and gate oxide combination, formed oxide layer thickening has caused the gate oxide thickness under the grid 103 inhomogeneous.After finishing step 4, as shown in Figure 2, Fig. 2 reoxidizes a layer schematic diagram for prior art in making the device layer process of semiconductor device, as can be seen, the gate oxide thickness that obtains than thick at the thickness of its elsewhere of grid, forms " smile " type oxide layer at the gate edge place.
In a processing procedure process, need on a wafer, make the device layer of a plurality of semiconductor device according to said process simultaneously, reason owing to step 4, make that the thickness of the gate oxide of the device layer of a plurality of semiconductor device of making is difficult to control simultaneously, cause in same processing procedure process, the performance range of a plurality of semiconductor device that finally obtain changes greatly and also there is the comparison big-difference in switch performance.For a semiconductor device,, also can influence its performance (main is switch performance) because its gate oxide thickness is inhomogeneous.
In order to overcome this problem, at present, can be in step 5 by reducing energy or the concentration that ion injects, can also be in the step 4 process, reduce the performance range of a plurality of semiconductor device that time that deposition reoxidizes layer reduces finally to obtain and reduce the difference of switch performance, and for the performance that causes because gate oxide thickness the is inhomogeneous reduction of a semiconductor device.But these methods just can be improved the problems referred to above, but can not eliminate fully owing to " smile " type oxidative phenomena cause to device performance excursion and switch performance exert an influence.
Summary of the invention
In view of this, the invention provides a kind of device layer manufacture method of semiconductor device, this method can be eliminated because of " smile " type oxidative phenomena causes device performance excursion and switch performance are exerted an influence.
For achieving the above object, the technical scheme of the embodiment of the invention specifically is achieved in that
A kind of device layer manufacture method of semiconductor device, this method comprises:
After forming grid on the semiconductor device substrates, form nitration case at gate lateral wall;
After described gate surface and semiconductor substrate surface deposition reoxidizes layer, grid and Semiconductor substrate are carried out light dope;
After forming the nitrogen oxide side wall of described grid, grid and semiconductor device substrates are mixed, form drain electrode and source electrode in the semiconductor device deposition;
Adopt the self-aligned silicide method at gate surface and Semiconductor substrate plated metal, form metallised silicon layer, after carrying out short annealing then and handling, etch away unreacted metal.
The nitration case thickness of described formation is 10 dusts～20 dusts.
Described process at gate lateral wall formation nitration case is:
Behind semiconductor device substrates and gate surface employing chemical gaseous phase depositing process cvd nitride layer, the nitration case that etching top portions of gates surface and semiconductor substrate surface form stays silicon nitride layer at gate lateral wall.
The described thickness that reoxidizes layer is 10 dusts～20 dusts.
Described before grid and Semiconductor substrate are carried out light dope, this method also comprises:
On grid, form the skew side wall.
By such scheme as can be seen; the present invention is in the device layer manufacturing process of semiconductor device; before generation reoxidizes layer, form the silicon nitride resilient coating earlier, as the protection of gate lateral wall; like this; when deposition reoxidizes layer, just can not occur because the gate edge around gate oxide and the reaction of oxygen, and cause the gate oxide thickening at this place; thereby the uneven thickness of gate oxide forms " smile " type oxidative phenomena.Like this,, just can not cause the device performance excursion big, can not make the switch performance otherness big yet for a plurality of semiconductor device of making simultaneously.Therefore, method provided by the invention has been eliminated because of " smile " type oxidative phenomena causes device performance excursion and switch performance are exerted an influence.
Description of drawings
Fig. 1 a～1f is the sectional structure chart that the device layer of prior art semiconductor device is made;
Fig. 2 reoxidizes a layer schematic diagram for prior art in making the device layer process of semiconductor device;
Fig. 3 is the device layer manufacture method flow chart of semiconductor device provided by the invention;
Fig. 4 a～4h is the device layer manufacture method sectional structure chart of semiconductor device provided by the invention.
Embodiment
For making purpose of the present invention, technical scheme and advantage clearer, below with reference to the accompanying drawing embodiment that develops simultaneously, the present invention is described in further detail.
From prior art as can be seen, the device performance excursion of the feasible a plurality of semiconductor device made simultaneously of prior art is big and make the switch performance otherness big, and for the former of the degradation of wherein each semiconductor device because: in the device layer process of making semiconductor device, uncontrollablely make that the thickness of gate oxide is even.This problem is more outstanding along with the reducing day by day of CD size of semiconductor device.
In order to overcome this problem; in the device layer manufacturing process of semiconductor device; before generation reoxidizes layer, form the silicon nitride resilient coating earlier, as the protection of gate lateral wall; like this; when deposition reoxidizes layer, just can not occur because the gate edge around gate oxide and the reaction of oxygen, and cause the gate oxide thickening at this place; thereby the uneven thickness of gate oxide forms " smile " type oxidative phenomena.
The silicon nitride resilient coating that forms can also reoxidize in deposition and improve oxygen enhancing diffusion (OED) effect in the process, thereby can not make oxygen atom be diffused in the grid by the fault location of grid; The silicon nitride resilient coating that forms can also reoxidize the alloy that prevents grid and Semiconductor substrate in the process in deposition and be diffused into its surperficial oxide layer (density of oxide layer is less than the density of nitration case, so alloy is difficult for being diffused in the nitration case), and the concentration loss who causes.Can learn by analyzing, pass through method provided by the invention and can improve follow-up shallow doping process performance, this method has also reduced alloy (because the alloy diffusion when the reoxidizing layer causes) concentration of semiconductor substrate surface simultaneously, especially near source electrode and drain electrode place, thereby make reverse junction depth (Cj0) and switching frequency all be improved.
Fig. 3 is the device layer manufacture method flow chart of semiconductor device provided by the invention, and in conjunction with the profile of the device layer manufacturing process of the semiconductor device provided by the invention shown in Fig. 4 a～Fig. 4 h, the present invention is described in detail.
In this step, two traps comprise a N trap and a P trap, usually adopt the technology of falling the dopant well to carry out, just the N well area of definition injects impurities such as phosphorus in semiconductor device substrates 101, follow-up formation PMOS, P well area in definition injects impurities such as boron, follow-up formation N type NMOS.
Here to describe in detail at P trap and the structure that forms on the P trap, to form NMOS, the structure that forms on the N trap is then ignored introduction, and step is basic identical.
In this step, the process that forms STI102 is: deposit isolating oxide layer and nitride layer successively in semiconductor device substrates 101 earlier, the photoresist layer that adopts exposure imaging technology to apply on nitride layer defines the STI figure, the photoresist layer that will have the STI figure obtains the STI groove as mask etch silicon nitride layer successively, isolating oxide layer and semiconductor device substrates 101, after then the STI groove being carried out the oxide filling, carry out the polishing of nitride layer and layer of isolation oxide, in semiconductor device substrates 101, obtain STI102.
In this step, for NMOMS, the impurity of doping is phosphorus, and purpose is the grid conduction for the feasible final semiconductor device of making, and for PMOS, the impurity of doping is boron.
In this step, deposition adopts chemical gaseous phase depositing process, and the nitration case thickness of deposition is 10 dusts～20 dusts.
In this step, the process that adopts photoetching process to obtain grid 103 is: apply behind the photoresist layer light shield by having gate patterns to its exposure imaging, form gate patterns at photoresist layer, be mask with photoresist layer then with gate patterns, etch polysilicon layer and gate oxide form grid 103 successively.
Step 305 adopts etching technics, and the nitration case of grid 103 top layers and the nitration case on Semiconductor substrate 101 surfaces are etched away, and only the sidewall at grid 103 stays nitration case 201, shown in Fig. 4 d.
In this step, guarantee that the nitration case 201 that grid 103 sidewalls stay can protect grid 103, reoxidize in the process follow-up, can be with the grid 103 edge oxidations around the gate oxide.
In this step, form the process reoxidize layer and be: adopt the chemical gaseous phase depositing process deposition to obtain reoxidizing layer 202, this effect that reoxidizes layer is in order to repair in forming grid 103 processes the damage to semiconductor device substrates 101 surfaces.
In this step, the layer thickness that reoxidizes of formation is 10 dusts～20 dusts.
After step 307, grid in the structure shown in Fig. 4 e form the skew side wall, inject 20 methods with ion the trap of semiconductor device substrates 101 is carried out light dope, referring to Fig. 4 f.
In the drawings, omitted the skew side wall, the skew side wall generally adopts nitride to constitute, and the formation of skew side wall is the possibility of electric charge break-through between the source leakage that increases in order to prevent reducing of NMOS channel length in light dope technology.
Certainly, on specific implementation, also can not form the skew side wall.
In this step, for NMOS, the impurity that light dope adopts can be arsenic, makes the upper surface of semiconductor device substrates 101 become amorphous state, reduces the channel leakage stream effect between source-drain electrode.
Step 308 because grid 103 is subjected to injecting the bump of ion in the process of mixing, causes the lattice of silicon structure to damage, and for recovering damage, ion carries out quick thermal annealing process after injecting 20.
Step 309, referring to Fig. 4 g, behind grid 103 formation nitrogen oxide side walls 204, on semiconductor device substrate 101, just define source drain region, method with ion injection 30 is mixed to the semiconductor device substrates 101 of grid 103 and grid 103 both sides, forms drain electrode 301 and source electrode 302.
In the drawings, represent, omitted nitration case 201 and reoxidized layer 202, because oxide layer and nitrogen oxide layer can be used as the part of nitride side wall in order to make to simplify and be easy to.
Step 310 referring to Fig. 4 h, adopts the method titanium deposition of SAB, forms titanizing silicon layer 401, after carrying out short annealing then and handling, adopts chemical method to etch away unreacted titanium.
This step is in order to form contact hole, can be so that active area forms Metal Contact.
In this step, also can adopt other metals to carry out this reaction.
Like this, just having finished the device layer of semiconductor device makes.
From Fig. 4 e as can be seen; because nitration case can be protected grid 103 in the existence of gate lateral wall, reoxidizes in the process follow-up; can be with the grid 103 edge oxidations around the gate oxide, thus make the semiconductor device that finally obtains gate oxide thickness evenly and controlled.
More than lift preferred embodiment; the purpose, technical solutions and advantages of the present invention are further described; institute is understood that; the above only is preferred embodiment of the present invention; not in order to restriction the present invention; within the spirit and principles in the present invention all, any modification of being done, be equal to and replace and improvement etc., all should be included within protection scope of the present invention.
Claims (5)
1. the device layer manufacture method of a semiconductor device, this method comprises:
After forming grid on the semiconductor device substrates, form nitration case at gate lateral wall;
After described gate surface and semiconductor substrate surface deposition reoxidizes layer, grid and Semiconductor substrate are carried out light dope;
After forming the nitrogen oxide side wall of described grid, grid and semiconductor device substrates are mixed, form drain electrode and source electrode in the semiconductor device deposition;
Adopt the self-aligned silicide method at gate surface and Semiconductor substrate plated metal, form metallised silicon layer, after carrying out short annealing then and handling, etch away unreacted metal.
2. the method for claim 1 is characterized in that, the nitration case thickness of described formation is 10 dusts～20 dusts.
3. method as claimed in claim 1 or 2 is characterized in that, described process at gate lateral wall formation nitration case is:
Behind semiconductor device substrates and gate surface employing chemical gaseous phase depositing process cvd nitride layer, the nitration case that etching top portions of gates surface and semiconductor substrate surface form stays silicon nitride layer at gate lateral wall.
4. method as claimed in claim 1 or 2 is characterized in that, the described thickness that reoxidizes layer is 10 dusts～20 dusts.
5. the method for claim 1 is characterized in that, described before grid and Semiconductor substrate are carried out light dope, this method also comprises:
On grid, form the skew side wall.
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| CN2009101980985A CN102054697A (en) | 2009-10-29 | 2009-10-29 | Manufacturing method for device layer of semiconductor device |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102709314A (en) * | 2012-05-22 | 2012-10-03 | 上海华力微电子有限公司 | Physically-isolated silicon nanocrystalline double-bit storage structure and preparation method thereof |
| CN104681420A (en) * | 2013-11-26 | 2015-06-03 | 中芯国际集成电路制造(上海)有限公司 | Forming method of semiconductor device |
| CN104701319A (en) * | 2013-12-10 | 2015-06-10 | 中芯国际集成电路制造(上海)有限公司 | CMOS (complementary metal oxide semiconductor) device and production method thereof |
| CN106158664A (en) * | 2016-09-30 | 2016-11-23 | 上海华力微电子有限公司 | MOSFET element manufacture method and MOSFET element |
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2009
- 2009-10-29 CN CN2009101980985A patent/CN102054697A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102709314A (en) * | 2012-05-22 | 2012-10-03 | 上海华力微电子有限公司 | Physically-isolated silicon nanocrystalline double-bit storage structure and preparation method thereof |
| CN104681420A (en) * | 2013-11-26 | 2015-06-03 | 中芯国际集成电路制造(上海)有限公司 | Forming method of semiconductor device |
| CN104681420B (en) * | 2013-11-26 | 2018-06-01 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor devices |
| CN104701319A (en) * | 2013-12-10 | 2015-06-10 | 中芯国际集成电路制造(上海)有限公司 | CMOS (complementary metal oxide semiconductor) device and production method thereof |
| CN106158664A (en) * | 2016-09-30 | 2016-11-23 | 上海华力微电子有限公司 | MOSFET element manufacture method and MOSFET element |
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Effective date of registration: 20121116 Address after: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Applicant after: Semiconductor Manufacturing International (Shanghai) Corporation Applicant after: Semiconductor Manufacturing International (Beijing) Corporation Address before: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Applicant before: Semiconductor Manufacturing International (Shanghai) Corporation |
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Application publication date: 20110511 |