CN102097382B - Method for manufacturing semiconductor device - Google Patents
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- CN102097382B CN102097382B CN 200910201494 CN200910201494A CN102097382B CN 102097382 B CN102097382 B CN 102097382B CN 200910201494 CN200910201494 CN 200910201494 CN 200910201494 A CN200910201494 A CN 200910201494A CN 102097382 B CN102097382 B CN 102097382B
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Abstract
The invention discloses a method for manufacturing a semiconductor device, which comprises the following steps of: forming a shallow trench isolation region for isolating an active region in a substrate; forming a high dielectric constant grid oxide layer, a titanium nitride blocking layer and a temporary polycrystalline silicon grid, sequentially positioned on the substrate, of an N-type metal oxide semiconductor (NMOS) tube and a P-type metal oxide semiconductor (PMOS) tube in the active region respectively; and then forming auxiliary side wall layers on two sides of the temporary polycrystalline silicon grids of the NMOS tube and the PMOS tube. The method can improve the performance of the semiconductor device and reduce the performance difference between the semiconductor devices at the same time.
Description
Technical field
The present invention relates to semiconductor technology, particularly a kind of manufacture method of semiconductor device.
Background technology
In order to control short-channel effect, littler scale device further requires to improve grid capacitance.This can realize by the thickness that constantly reduces gate oxide, but the thing followed is the lifting of grid leakage current.Especially work as silicon dioxide as gate oxide, when thickness was lower than 1 nanometer, leakage current just became and can't stand.The effective ways that address the above problem just are to use high dielectric constant insulating material to replace silicon dioxide, high dielectric constant insulating material can be hafnium silicate, hafnium silicon oxygen nitrogen compound, hafnium oxide etc., dielectric constant is generally all greater than 15, adopt this material can further improve gate capacitance, grid leakage current can be significantly improved again simultaneously.For identical gate oxide thickness, adopt metal gates to replace polysilicon gate, that is to say, with high dielectric constant insulating material and metal gates collocation, grid leakage current will reduce several magnitude, and has solved problem incompatible between high dielectric constant insulating material and the polysilicon with metal gates replacement polysilicon gate.
Below the manufacture method based on the semiconductor device of the gate oxide of high dielectric constant insulating material and metal gates is described in detail.
Semiconductor device is made and is meant chemistry or the physical operations of carrying out a series of complexity on substrate, to form the process of semiconductor device.Fig. 1～Figure 12 is the process generalized section of the manufacture method of semiconductor device in the prior art, and this method mainly comprises:
Step 101 referring to Fig. 1, provides a substrate, is formed for isolating shallow trench isolation region (STI), N trap and the P trap of active area in substrate.
Adopt twin well process to define the active area of N type metal oxide semiconductor (NMOS) pipe and P-type mos (PMOS) pipe, thereby obtain N trap and P trap.
Then, by technologies such as photoetching and etchings, in substrate, be formed for isolating the STI of active area.
Step 102 referring to Fig. 2, at substrate surface growth gate oxide, and the deposit polysilicon, utilizes technologies such as photoetching and etching to form the polysilicon gate construction of NMOS pipe, the polysilicon gate construction of formation PMOS pipe above the N trap above the P trap.
In this step, at first carry out the growth of gate oxide, gate oxide is a high dielectric constant insulating material; Also form one deck barrier layer on gate oxide, the composition on barrier layer is titanium nitride (TiN), can be used as the diaphragm of gate oxide, and thickness is about 5～50 dusts; Then, by chemical vapor deposition (CVD) technology, at crystal column surface deposit one deck polysilicon, thickness is about 500～2000 dusts; Afterwards, by technologies such as photoetching and etchings, produce the polysilicon gate construction of NMOS pipe and PMOS pipe.
Polysilicon gate construction of the present invention comprises the polysilicon gate that is made of polysilicon and is positioned at the gate oxide and the barrier layer of polysilicon gate below.
So far, finished the making of the polysilicon gate construction of NMOS pipe and PMOS pipe.
Need to prove that in subsequent step, polysilicon gate can be removed, therefore, polysilicon gate involved in the present invention also can be described as interim polysilicon gate.
Step 103 referring to Fig. 3, is carried out lightly doped drain (LDD) and is injected on the substrate of the polysilicon gate construction both sides of NMOS pipe, carry out LDD and inject on the substrate of PMOS pipe polysilicon gate construction both sides.
Under the promotion of demands such as semiconductor device miniatureization, densification, high speed and system integration, the width of grid structure constantly reduces, the channel length of its below also constantly reduces, yet the voltage of drain terminal does not significantly reduce, this has just caused the increase at the electric field of drain terminal, near making electric charge has bigger energy, these hot carriers might be passed through gate oxide, caused the increase of leakage current, therefore, need to adopt some means to reduce the possibility that leakage current occurs, inject as LDD.
Before LDD injects, need at first utilize lithographic definition to go out and to carry out the zone that LDD injects; Then, utilize dopant material to carry out LDD and inject, thereby make the upper surface of substrate become amorphous state, big quality materials and surface amorphously help to keep shallow junction, shallow junction helps to reduce leakage current.
Step 104 is referring to Fig. 4, at substrate surface deposit silicon dioxide (SiO successively
2) and silicon nitride (Si
3N
4), and adopt dry etch process that silicon dioxide and silicon nitride are carried out etching, form the side wall layer of the polysilicon gate construction of NMOS pipe and PMOS pipe.
Wherein, side wall layer comprises the first side wall layer and second side wall layer, and the first side wall layer is to be silicon dioxide after the etching, and second side wall layer is the silicon nitride after the etching.
Side wall layer can be used for preventing that follow-up carrying out from too leaking break-through near raceway groove so that generation source when the source leak to be injected, and produces leakage current thereby diffusion takes place the impurity that promptly injects.
So far, finished the making of side wall layer.
Step 105 referring to Fig. 5, is carried out ion and is injected on the Semiconductor substrate of the side wall layer both sides of NMOS pipe polysilicon gate construction, thereby forms the drain electrode and the source electrode of NMOS pipe.
At first utilize lithographic definition to go out and to carry out the NMOS source and drain areas that ion injects; Then, carry out the injection of N type ion according to the zone that defines, the side wall layer that forms in the step 104 can be used in the protection raceway groove.
The junction depth that the junction depth that N type ion injection back forms carries out LDD injection back formation than step 103 is bigger.
Step 106 referring to Fig. 6, is carried out ion and is injected on the Semiconductor substrate of the side wall layer both sides of PMOS pipe polysilicon gate construction, thereby forms the drain electrode and the source electrode of PMOS pipe.
Utilize lithographic definition to go out equally, earlier and will carry out the PMOS pipe source and drain areas that ion injects; Then, carry out the injection of P type ion according to the zone that defines, the side wall layer that forms in the step 104 can be used in the protection raceway groove.
The junction depth that the junction depth that P type ion injection back forms carries out LDD injection back formation than step 103 is bigger.
So far, the NMOS pipe and the drain electrode of PMOS pipe, the making of source electrode have been finished.
Step 107 referring to Fig. 7, in the substrate surface metallization medium layer, and adopts chemical mechanical milling tech (CMP) dielectric layer to be ground to the surface of polysilicon gate.
In actual applications, before metallization medium layer, also can further deposit one deck platinum nickel (NiPt), because the main material of substrate is a silicon, nickel ion and silicon generation chemical reaction can generate the tantnickel compound, thereby reduce the resistance of substrate surface.
Step 108 referring to Fig. 8, is removed the polysilicon gate of NMOS pipe and PMOS pipe.
Adopt tetramethyl ammonium hydroxide (TMAH) that polysilicon gate is carried out etching, thereby the polysilicon gate of NMOS pipe and PMOS pipe is removed.
Step 109 referring to Fig. 9, deposits the first work function NMOS gate metal, and adopts CMP the first work function NMOS gate metal to be ground to the surface of dielectric layer.
Wherein, deposition along with the first work function NMOS gate metal, the first work function NMOS gate metal is filled in NMOS pipe and the PMOS pipe and removes in the groove that exposes behind the polysilicon gate, and the first work function NMOS gate metal is a titanium nitride, is used for forming at subsequent step the metal gates of NMOS pipe.
Step 110 referring to Figure 10, applies first mask (scheming not shown) above the NMOS pipe, the first work function NMOS gate metal of being filled in the PMOS pipe is carried out etching.
Wherein, because the NMOS top is applied with first mask, adopt standard cleaning solution (SC1) the first work function NMOS gate metal of being filled in the PMOS pipe can be removed, and the first work function NMOS gate metal in the reservation NMOS pipe, need to prove, SC1 is the title of standard cleaning solution, and it is ammoniacal liquor (NH
4OH), hydrogen peroxide (H
2O
2) and water (H
2O) mixture.
Step 111 referring to Figure 11, deposits the second work function PMOS gate metal, and adopts CMP the second work function PMOS gate metal to be ground to the surface of dielectric layer.
The second work function PMOS gate metal is the tantalum aluminium compound, is used for forming at subsequent step the metal gates of PMOS pipe.
Step 112, referring to Figure 12, deposition gate electrode (gate electrode) metal, and adopt CMP gate electrode metal to be ground to the surface of dielectric layer.
Wherein, gate electrode metal is metallic aluminium (Al), and the gate electrode metal and the first work function NMOS gate metal constitute the metal gates of NMOS pipe jointly, and the gate electrode metal and the second work function PMOS gate metal constitute the metal gates of PMOS pipe jointly.
Need to prove, in step 109, also can deposit the second work function PMOS gate metal, be used for forming the metal gates of PMOS pipe, in step 110, above the PMOS pipe, apply mask then at subsequent step, adopt SC1 that the second work function PMOS gate metal of being filled in the NMOS pipe is carried out etching, in step 111, deposit the first work function NMOS gate metal then, be used for forming the metal gates of NMOS pipe at subsequent step.
So far, finished the making of the metal gates of NMOS pipe and PMOS pipe.
Yet, in above-mentioned steps 108, after the polysilicon gate removal with NMOS pipe and PMOS pipe, barrier layer under the polysilicon gate is exposed in the air, because the composition on barrier layer is a titanium nitride, and titanium nitride is easily by the oxidation of airborne oxygen institute, can shrink phenomenon after titanium nitride is oxidized, when and after forming metal gates at deposition work function gate metal and metallic aluminium on the titanium nitride, the bottom width of metal gates is less than upper width, thereby reduced the performance of semiconductor device, further, because the bottom width and the upper width of metal gates there are differences, thereby be difficult to the width of the metal gates of semiconductor device is accurately controlled, might make that the performance difference between the semiconductor device is bigger.
Summary of the invention
In view of this, the invention provides a kind of manufacture method of semiconductor device, can improve the performance of semiconductor device, and reduce the performance difference between the semiconductor device.
For solving the problems of the technologies described above, technical scheme of the present invention is achieved in that
A kind of manufacture method of semiconductor device, in substrate, be formed for isolating the shallow channel isolation area STI of active area, and active area form respectively N type metal oxide semiconductor NMOS pipe, P-type mos PMOS pipe be positioned at high-k gate oxide, titanium nitride barrier layer and interim polysilicon gate on the substrate successively after, this method comprises:
Formation is positioned at the secondary side parietal layer of the interim polysilicon gate both sides of NMOS pipe and PMOS pipe;
On the substrate of the secondary side parietal layer both sides of the interim polysilicon gate of NMOS pipe and PMOS pipe, carry out lightly doped drain LDD injection:
Formation is positioned at the secondary side parietal layer side walls layer of NMOS pipe and PMOS pipe;
On the substrate of the side wall layer both sides of NMOS pipe and PMOS pipe, carry out ion respectively and inject, form that NMOS manages and the drain electrode and the source electrode of PMOS pipe;
On substrate, form the identical dielectric layer of apparent height surperficial and interim polysilicon gate;
Remove the interim polysilicon gate of NMOS pipe and PMOS pipe;
The deposition first work function NMOS gate metal on the titanium nitride barrier layer of NMOS pipe;
The deposition second work function PMOS gate metal on the titanium nitride barrier layer of PMOS pipe;
On dielectric layer, deposit gate electrode metal, and adopt CMP gate electrode metal to be ground to the surface of dielectric layer.
Described gate electrode metal is the metal aluminum or aluminum alloy.
The method of described formation secondary side parietal layer comprises: at substrate surface depositing titanium nitride or tantalum nitride, and titanium nitride or tantalum nitride carried out etching.
The method of described depositing titanium nitride or tantalum nitride comprises: adopt chemical vapor deposition method CVD, atom layer deposition process ALD or physical gas-phase deposition PVD that titanium nitride or tantalum nitride are deposited.
The thickness of the secondary side parietal layer of the interim polysilicon gate both sides of NMOS pipe and PMOS pipe is 10 dust to 100 dusts.
The method of described formation side wall layer comprises: at substrate surface deposition of silica successively and/or silicon nitride, and silicon dioxide and/or silicon nitride carried out etching.
Adopt technical scheme of the present invention, in substrate, be formed for isolating the STI of active area, and form NMOS pipe respectively at active area, the PMOS pipe be positioned at high-k gate oxide on the substrate successively, behind titanium nitride barrier layer and the interim polysilicon gate, form the secondary side parietal layer of the interim polysilicon gate both sides of NMOS pipe and PMOS pipe, owing to barrier layer and secondary side parietal layer can be shunk phenomenon by the oxidation of airborne oxygen institute, when in subsequent step and after forming metal gates in deposition work function gate metal and gate electrode metal on the barrier layer, the contraction of identical or close degree can take place in the bottom of metal gates and top, that is to say, the bottom width and the upper width of metal gates do not have difference, thereby improved the performance of semiconductor device, simultaneously, reduced performance difference between the semiconductor device.
Description of drawings
Fig. 1～Figure 12 is the process generalized section of the manufacture method of semiconductor device in the prior art.
Figure 13 is the flow chart of the manufacture method of a kind of semiconductor device provided by the present invention.
The process generalized section of the embodiment of the manufacture method of semiconductor device among Figure 14～Figure 26 the present invention.
Embodiment
For making purpose of the present invention, technical scheme and advantage clearer, below with reference to the accompanying drawing embodiment that develops simultaneously, scheme of the present invention is described in further detail.
Figure 13 is the flow chart of the manufacture method of a kind of semiconductor device provided by the present invention.As shown in figure 13, this method may further comprise the steps:
Step 202 is carried out the LDD injection on the substrate of the interim polysilicon gate both sides of NMOS pipe and PMOS pipe.
Step 203 forms the secondary side parietal layer side walls layer that is positioned at NMOS pipe and PMOS pipe.
Step 204 is carried out ion respectively and is injected on the substrate of the side wall layer both sides of NMOS pipe and PMOS pipe, form that NMOS manages and the drain electrode and the source electrode of PMOS pipe.
Step 205 forms the identical dielectric layer of apparent height surperficial and interim polysilicon gate on substrate.
Step 209 deposits gate electrode metal on dielectric layer, and adopts CMP gate electrode metal to be ground to the surface of dielectric layer.
So far, this flow process finishes.
The present invention is described in detail below by an embodiment.
Figure 14～Figure 26 is the process generalized section of the embodiment of the manufacture method of semiconductor device among the present invention, and this method mainly comprises:
Step 301 referring to Figure 14, provides a substrate, forms N trap, P trap and STI on substrate.
Step 302, referring to Figure 15, grow high dielectric constant insulating material as gate oxide at substrate surface, deposited barrier layer on gate oxide, the composition titanium nitride on barrier layer, deposit spathic silicon on the barrier layer then utilizes technologies such as photoetching, etching and ion injection to form the polysilicon gate construction of NMOS pipe above the P trap, forms the polysilicon gate construction of PMOS pipe above the N trap.
Gate oxide and barrier layer that polysilicon gate construction of the present invention comprises the polysilicon gate that is made of polysilicon and is positioned at the polysilicon gate below.
So far, finished the making of the polysilicon gate construction of NMOS pipe and PMOS pipe.
Need to prove that in subsequent step, polysilicon gate can be removed, therefore, polysilicon gate involved in the present invention also can be described as interim polysilicon gate.
Step 303 referring to Figure 16, at substrate surface depositing titanium nitride or tantalum nitride, and is carried out etching to titanium nitride or tantalum nitride, forms the secondary side parietal layer of the polysilicon gate construction of NMOS pipe and PMOS pipe.
In actual applications, generally adopt chemical vapor deposition method (CVD), atom layer deposition process (ALD) or physical gas-phase deposition (PVD) that titanium nitride or tantalum nitride are deposited.
The titanium nitride that is deposited or the thickness of tantalum nitride are 10 dust to 100 dusts.
Need to prove, compared with prior art, increased the secondary side parietal layer, the composition on secondary side parietal layer and barrier layer is identical or close, the secondary side parietal layer also can be shunk phenomenon by airborne oxygen institute's oxidation, when and after forming metal gates at deposition work function gate metal and metallic aluminium on the barrier layer, the contraction of identical or close degree can take place in the bottom of metal gates and top, that is to say, the bottom width and the upper width of metal gates do not have difference, like this, just can be subjected to shrinkage character after the oxidation according to secondary side parietal layer and barrier layer, the width to defined metal gates suitably increases in advance, thereby improved the performance of semiconductor device, simultaneously, all controlled with the width of the metal gates of each semiconductor device in a collection of product, reduced the performance difference between the semiconductor device.
Even the width to metal gates does not increase with carrying out in advance, because the upper width and the lower width of metal gates do not have difference, the performance of semiconductor device is not substantially received influence yet.
Step 304 referring to Figure 17, is carried out LDD and is injected on the Semiconductor substrate of the polysilicon gate construction both sides of NMOS pipe, carry out LDD and inject on the Semiconductor substrate of PMOS pipe polysilicon gate construction both sides.
Step 305 referring to Figure 18, at substrate surface deposition of silica successively and/or silicon nitride, and is carried out etching to silicon dioxide and/or silicon nitride, forms the side wall layer of the polysilicon gate construction of NMOS pipe and PMOS pipe.
Wherein, side wall layer comprises the first side wall layer and second side wall layer, and the first side wall layer is a silicon dioxide, and second side wall layer is the silicon nitride after the etching.
So far, finished the making of side wall layer.
Step 306 referring to Figure 19, is carried out ion and is injected on the Semiconductor substrate of the side wall layer both sides of the polysilicon gate construction of NMOS pipe, thereby forms the drain electrode and the source electrode of NMOS pipe.
Step 307 referring to Figure 20, is carried out ion and is injected on the Semiconductor substrate of the side wall layer both sides of the polysilicon gate construction of PMOS pipe, thereby forms the drain electrode and the source electrode of PMOS pipe.
So far, the NMOS pipe and the drain electrode of PMOS pipe, the making of source electrode have been finished.
Step 308 referring to Figure 21, in the substrate surface metallization medium layer, and adopts CMP dielectric layer to be ground to the surface of polysilicon gate.
Step 309 referring to Figure 22, adopts TMAH simultaneously the polysilicon gate of NMOS pipe PMOS pipe to be carried out etching.
Step 310 referring to Figure 23, deposits the first work function NMOS gate metal, and adopts CMP the first work function NMOS gate metal to be ground to the surface of dielectric layer.
The first work function NMOS gate metal is a titanium nitride, is used for forming at subsequent step the metal gates of NMOS.
Step 311 referring to Figure 24, applies second mask (scheming not shown) above NMOS, the first work function NMOS gate metal of being filled among the PMOS is carried out etching.
Wherein, adopt SC1 that the first work function NMOS gate metal is carried out etching.
Step 312 referring to Figure 25, deposits the second work function PMOS gate metal, and adopts CMP the second work function PMOS gate metal to be ground to the surface of dielectric layer.
The second work function PMOS gate metal is the tantalum aluminium compound, is used for forming at subsequent step the metal gates of PMOS pipe.
Step 313, referring to Figure 26, the deposition gate electrode metal, and adopt CMP gate electrode metal to be ground to the surface of dielectric layer.
Wherein, gate electrode metal is the metal aluminum or aluminum alloy, when gate electrode metal was metallic aluminium, the metallic aluminium and the first work function NMOS gate metal constituted the metal gates of NMOS jointly, and the metallic aluminium and the second work function PMOS gate metal constitute the metal gates of PMOS pipe jointly.
Above step 305 does not repeat them here to 303 same as the prior art.
So far, this flow process finishes.
As seen, in the present invention, in substrate, be formed for isolating the STI of active area, and form NMOS pipe respectively at active area, the PMOS pipe be positioned at high-k gate oxide on the substrate successively, behind titanium nitride barrier layer and the interim polysilicon gate, form the secondary side parietal layer of the interim polysilicon gate both sides of NMOS pipe and PMOS pipe, owing to barrier layer and secondary side parietal layer can be shunk phenomenon by the oxidation of airborne oxygen institute, when in subsequent step and after forming metal gates in deposition workfunction metal and gate electrode metal on the barrier layer, the contraction of identical or close degree can take place in the bottom of metal gates and top, that is to say, the bottom width and the upper width of metal gates do not have difference, thereby improved the performance of semiconductor device, simultaneously, reduced performance difference between the semiconductor device.
The above is preferred embodiment of the present invention only, is not to be used to limit protection scope of the present invention.Within the spirit and principles in the present invention all, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (5)
1. the manufacture method of a semiconductor device, in substrate, be formed for isolating the shallow channel isolation area STI of active area, and active area form respectively N type metal oxide semiconductor NMOS pipe, P-type mos PMOS pipe be positioned at high-k gate oxide, titanium nitride barrier layer and interim polysilicon gate on the substrate successively after, it is characterized in that this method comprises:
Form the secondary side parietal layer of the interim polysilicon gate both sides of NMOS pipe and PMOS pipe;
On the substrate of the secondary side parietal layer both sides of the interim polysilicon gate of NMOS pipe and PMOS pipe, carry out lightly doped drain LDD injection:
Formation is positioned at the secondary side parietal layer side walls layer of NMOS pipe and PMOS pipe;
On the substrate of the side wall layer both sides of NMOS pipe and PMOS pipe, carry out ion respectively and inject, form that NMOS manages and the drain electrode and the source electrode of PMOS pipe;
On substrate, form the identical dielectric layer of apparent height surperficial and interim polysilicon gate;
Remove the interim polysilicon gate of NMOS pipe and PMOS pipe;
The deposition first work function NMOS gate metal on the titanium nitride barrier layer of NMOS pipe;
The deposition second work function PMOS gate metal on the titanium nitride barrier layer of PMOS pipe;
On dielectric layer, deposit gate electrode metal, and adopt chemical mechanical milling tech CMP gate electrode metal to be ground to the surface of dielectric layer;
The method of described formation secondary side parietal layer comprises: at substrate surface depositing titanium nitride or tantalum nitride, and titanium nitride or tantalum nitride carried out etching.
2. method according to claim 1 is characterized in that, described gate electrode metal is the metal aluminum or aluminum alloy.
3. method according to claim 1, it is characterized in that the method for described depositing titanium nitride or tantalum nitride comprises: adopt chemical vapor deposition method CVD, atom layer deposition process ALD or physical gas-phase deposition PVD that titanium nitride or tantalum nitride are deposited.
4. method according to claim 3 is characterized in that, the thickness of the secondary side parietal layer of the interim polysilicon gate both sides of NMOS pipe and PMOS pipe is 10 dust to 100 dusts.
5. method according to claim 1 is characterized in that, the method for described formation side wall layer comprises: at substrate surface deposition of silica successively and/or silicon nitride, and silicon dioxide and/or silicon nitride carried out etching.
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| CN103107073B (en) * | 2011-11-11 | 2016-08-10 | 中芯国际集成电路制造(上海)有限公司 | The forming method of metal gates |
| CN103107075B (en) * | 2011-11-11 | 2015-12-09 | 中芯国际集成电路制造(上海)有限公司 | The formation method of metal gates |
| CN103531538B (en) * | 2012-07-02 | 2016-01-06 | 中芯国际集成电路制造(上海)有限公司 | The formation method of CMOS (Complementary Metal Oxide Semiconductor) pipe |
| CN103779275A (en) * | 2012-10-17 | 2014-05-07 | 中国科学院微电子研究所 | CMOS manufacturing method |
| CN103779198B (en) * | 2012-10-22 | 2016-04-20 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and forming method thereof |
| CN108538833B (en) * | 2017-03-01 | 2021-04-02 | 中芯国际集成电路制造(上海)有限公司 | Resistor structure, semiconductor device and forming method thereof |
| CN109037046B (en) * | 2017-06-08 | 2021-04-02 | 中芯国际集成电路制造（天津）有限公司 | Metal gate, semiconductor device and manufacturing method thereof |
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| CN1846313A (en) * | 2003-09-09 | 2006-10-11 | 国际商业机器公司 | Structure and method for metal replacement gate of high performance device |
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