CN1815693A - Wafer washing method and grid structure mfg. method - Google Patents
Wafer washing method and grid structure mfg. method Download PDFInfo
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- CN1815693A CN1815693A CN 200510008130 CN200510008130A CN1815693A CN 1815693 A CN1815693 A CN 1815693A CN 200510008130 CN200510008130 CN 200510008130 CN 200510008130 A CN200510008130 A CN 200510008130A CN 1815693 A CN1815693 A CN 1815693A
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- acid solution
- hydrofluoric acid
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Abstract
The method is applicable after gate structure is defined. The gate structure includes gate dielectric layer, barrier layer of containing nitrogen, and gate electrode layer of containing silicon. Cleaning method carries out cleaning for substrate by using solution of phosphoric acid and solution of hydrofluoric acid. The cleaning method can remove residue of silicon nitride generated by barrier layer of containing nitrogen and gate electrode layer of containing silicon, and reduces adherence of contaminant and small particles so as to raise rate of finished products and quality and reliability of components.
Description
Technical field
The present invention relates to a kind of semiconductor technology, particularly relate to a kind of manufacture method of cleaning method and grid structure of wafer.
Background technology
In semiconductor technology now, it is one of frequent and important step that wafer cleans.The purpose of cleaning mainly is the residue that is used for removing wafer surface, as particulate (Particle), organic substance (Organic) and inorganic matter metal ion (Metal Ions) etc.Therefore, the wafer cleaning technology is one of key factor that influences process yield (Yield), element quality and reliability.
On the other hand, the making of grid structure is one of processing step important in the semiconductor technology, and its quality also affects process yield, element quality and reliability etc.Therefore, how in the process of making grid structure, the requirement that makes wafer reach high-cleanness, high is the problem of significant to produce the good grid structure of quality.
In the prior art, for a grid structure with gate dielectric layer of high-k (high-K), its manufacture method provides a substrate earlier, and forms gate dielectric layer, titanium nitride barrier layer and the polysilicon gate layer with high-k successively in this substrate.Afterwards, these retes are defined, to form a grid structure.Then, use the mixed solution (HF/H of hydrofluoric acid (HF), hydrofluoric acid and hydrogen peroxide
2O
2) or fluorine-containing organic solvent wait the residue that cleans substrate surface.
Yet in the process of definition grid structure, except meeting produced some particulates or pollutant, the polysilicon gate layer that is removed and the residue of titanium nitride barrier layer also may react the generation silicon nitride leftover, and drop on the surface of gate dielectric layer.So when when defining gate dielectric layer, these silicon nitride leftovers can become the mask of the subregion of gate dielectric layer, to such an extent as to covered zone is can't etching complete, and stay the residue of gate dielectric layer.It should be noted that and substrate is being utilized above-mentioned cleaning fluid clean, because of it is coated with silicon nitride leftover, therefore still can't remove on the residue of these gate dielectric layers.Fig. 3 is the photo figure that utilizes scanning type electron microscope (SEM) captured, and it is the photo figure of the part wafer of gained after defining and clean at grid structure.Can find many white points in Fig. 3, it is the residue 301 that residues on the wafer.That is to say that after cleaning, the residue of silicon nitride leftover and gate dielectric layer still exists.Thus, these residues on wafer surface will produce adverse influence to element quality and reliability.
Summary of the invention
In view of this, purpose of the present invention is exactly that a kind of cleaning method of wafer is being provided, and to remove the residue of wafer surface, improves the process yield of wafer.
A further object of the present invention provides a kind of manufacture method of grid structure, with in the process of making grid structure, effectively removes the residue of wafer surface, and then improves element quality and reliability.
Based on above-mentioned and other purpose, the present invention proposes a kind of cleaning method of wafer, and the method is suitable for defining after the grid structure.Wherein, this grid structure from bottom to top is followed successively by gate dielectric layer, nitrogenous barrier layer and siliceous grid layer from substrate surface.And cleaning method of the present invention uses phosphoric acid solution and hydrofluoric acid solution that substrate is cleaned.
The present invention reintroduces a kind of manufacture method of grid structure, and it forms nitrogenous barrier layer then prior to forming gate dielectric layer in the substrate on this gate dielectric layer, forms siliceous grid layer afterwards again on this nitrogenous barrier layer.Then, define above-mentioned siliceous grid layer, nitrogenous barrier layer and gate dielectric layer forming a stack architecture, and use phosphoric acid solution and hydrofluoric acid solution that a cleaning step is carried out in substrate.
Described according to the preferred embodiments of the present invention, in the manufacture method of the cleaning method of above-mentioned wafer and grid structure, its cleaning method uses the mixed solution of phosphoric acid solution and hydrofluoric acid solution mixing gained, or use phosphoric acid solution and hydrofluoric acid solution successively, or be to use hydrofluoric acid solution, phosphoric acid solution and hydrofluoric acid solution that substrate is cleaned successively.Wherein, in hydrofluoric acid solution, the mixed proportion of water and hydrofluoric acid is approximately between 1000: 1 to 10000: 1.In addition, the temperature of phosphoric acid solution is about 160 degree Celsius.In addition, the material of above-mentioned gate dielectric layer for example is to have high dielectric constant materials.Wherein, aforesaid material for example is hafnium oxide (HfO
2), be mixed with nitrogen hafnium oxide, be mixed with the hafnium oxide of nitrogen and silicon or be mixed with the hafnium oxide of silicon.In addition, the formation method of this gate dielectric layer for example be carry out atom layer deposition process (Atomic Layer Deposition, ALD) or metal organic chemical vapor deposition technology (Metal OrganicChemical Vapor Deposition, MOCVD).In addition, the material on nitrogenous barrier layer for example is a titanium nitride, and the material of siliceous grid layer for example is polysilicon or doped polycrystalline silicon.
Because cleaning method of the present invention uses phosphoric acid solution and hydrofluoric acid solution that substrate is cleaned, particularly, phosphoric acid solution can effectively be removed by nitrogenous barrier layer and the siliceous silicon nitride leftover that grid layer generated.Therefore, can solve and existing can't remove because of silicon nitride leftover, and the problem that causes the residue of gate dielectric layer thereunder to remove fully.Thus, just help to improve process yield, element quality and the reliability of wafer.
For above and other objects of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. is described in detail below.
Description of drawings
Figure 1A is a manufacturing process generalized section according to a kind of grid structure of the preferred embodiments of the present invention to Fig. 1 D.
Fig. 2 is the flow chart of steps of Figure 1A to Fig. 1 D.
Fig. 3 utilizes the captured photo figure of sweep electron microscope (SEM) after being existing the cleaning.
Fig. 4 utilizes the captured photo figure of sweep electron microscope (SEM) for after using cleaning method of the present invention.
The simple symbol explanation
100: substrate
102: gate dielectric layer
102a, 108,110,301: residue
104: the barrier layer
106: grid layer
107,109: stack architecture
200,202,204,206,208: step
Embodiment
Figure 1A is the manufacturing process generalized section that illustrates according to a kind of grid structure of the preferred embodiments of the present invention to Fig. 1 D.Fig. 2 illustrates the flow chart of steps of Figure 1A to Fig. 1 D.
Please at first, in substrate 100, form gate dielectric layer 102 (step 200) simultaneously with reference to Figure 1A and Fig. 2.Wherein, the material of gate dielectric layer 102 for example is to have high dielectric constant materials, and it for example is hafnium oxide, is mixed with the hafnium oxide of nitrogen, is mixed with the hafnium oxide of nitrogen and silicon, the hafnium oxide that is mixed with silicon or other suitable material.In addition, the formation method of gate dielectric layer 102 for example is to carry out atom layer deposition process, metal organic chemical vapor deposition technology or other suitable technology.
Then, on gate dielectric layer 102, form nitrogenous barrier layer 104 (step 202).The material on this nitrogenous barrier layer 104 for example is titanium nitride or other suitable nitrogenous material, and its formation method for example be carry out chemical vapor deposition method (Chemical Vapor Deposition, CVD), sputter (Sputtering) or other suitable technology.
Afterwards, on nitrogenous barrier layer 104, form siliceous grid layer 106 (step 204).Wherein, the material of this siliceous grid layer 106 for example is polysilicon, doped polycrystalline silicon or other suitable siliceous material.In addition, its formation method for example is to carry out chemical vapor deposition method or other suitable technology.
Then, define siliceous grid layer 106, nitrogenous barrier layer 104 and gate dielectric layer 102, to form a stack architecture (step 206), it is described in detail as follows.
Please refer to Figure 1B, define siliceous grid layer 106 and nitrogenous barrier layer 104, to form stack architecture 107 earlier.Yet; carry as prior art; in the process on definition siliceous grid layer 106 and nitrogenous barrier layer 104; except meeting produces some particulates or pollutant; the siliceous grid layer 106 that is removed also may react generation silicon nitride leftover 110 with the residue 108 on nitrogenous barrier layer 104, and drops on the surface of gate dielectric layer 102.Afterwards, continue definition gate dielectric layer 102 with formation stack architecture 109 (shown in Fig. 1 C), and this stack architecture 109 is made of above-mentioned stack architecture 107 and gate dielectric layer 102.Yet, carry as prior art equally, because silicon nitride leftover 110 drops on the surface of gate dielectric layer 102, cause when definition gate dielectric layer 102, these silicon nitride leftovers 110 can become the mask of the subregion of gate dielectric layer 102, to such an extent as to the zone that mask hid is can't etching complete, and stay the residue 102a of gate dielectric layer 102.
Continue it, please after stack architecture 109 forms, use phosphoric acid solution and hydrofluoric acid solution that cleaning step (step 208) is carried out in substrate 100, to remove the residue 102a, 110 in the substrate 100 simultaneously with reference to Fig. 1 D and Fig. 2.Wherein, above-mentioned cleaning step for example is to use phosphoric acid solution with the mixed solution of hydrofluoric acid solution mixing gained, use hydrofluoric acid solution, phosphoric acid solution and hydrofluoric acid solution or use phosphoric acid solution and hydrofluoric acid solution to clean substrate successively successively.Particularly, except aforesaid method, the present invention still can clean phosphoric acid solution with other different use with hydrofluoric acid solution in proper order, and promptly cleaning sequence is not limited to above-mentioned cleaning way.In addition, in above-mentioned hydrofluoric acid solution, the mixed proportion of water and hydrofluoric acid is approximately between 1000: 1 to 10000: 1.In addition, the temperature of phosphoric acid solution is about 160 degree Celsius.
What is particularly worth mentioning is that, in above-mentioned cleaning step (step 208), use phosphoric acid solution can effectively remove the silicon nitride leftover 110 that is generated by nitrogenous barrier layer 104 and siliceous grid layer 106.In other words, because silicon nitride leftover 110 can clean be removed by phosphoric acid solution, the therefore existing residue 102a that can't remove the gate dielectric layer 102 that causes its below because of silicon nitride leftover 110 can't also can solve in the lump by the problem that hydrofluoric acid is removed fully.
In addition, at above-mentioned cleaning step (step 208) afterwards, utilize the resulting photo figure of sweep electron microscope (SEM) photographing section wafer as shown in Figure 4.As shown in Figure 4, the photo figure (Fig. 3) in the prior art, original white point (residue 301) in substrate 100 disappeared.That is to say, utilize after the cleaning method clean wafers of the present invention that the residue 102a of silicon nitride leftover 110 and gate dielectric layer can be removed fully.
In sum, the cleaning method of wafer of the present invention is suitable for defining after the grid structure, and it is by using phosphoric acid solution and hydrofluoric acid solution that substrate is cleaned.Particularly, the existing silicon nitride leftover that can't effectively remove and the residue of gate dielectric layer can utilize cleaning method of the present invention to solve, and so can improve process yield, element quality and the reliability of wafer.
Though the present invention discloses as above with preferred embodiment; yet it is not in order to limit the present invention; those skilled in the art can do a little change and retouching without departing from the spirit and scope of the present invention, thus protection scope of the present invention should with accompanying Claim the person of being defined be as the criterion.
Claims (21)
1, a kind of cleaning method of wafer, be suitable for defining after the grid structure, this grid structure from bottom to top is followed successively by a gate dielectric layer, a nitrogenous barrier layer and a siliceous grid layer from a substrate surface, and this cleaning method uses phosphoric acid solution and hydrofluoric acid solution that this substrate is cleaned.
2, the cleaning method of wafer as claimed in claim 1, wherein this cleaning method uses a mixed solution of phosphoric acid solution and hydrofluoric acid solution mixing gained.
3, the cleaning method of wafer as claimed in claim 1, wherein this cleaning method uses phosphoric acid solution and hydrofluoric acid solution successively.
4, the cleaning method of wafer as claimed in claim 1, wherein this cleaning method uses hydrofluoric acid solution, phosphoric acid solution and hydrofluoric acid solution successively.
5, the cleaning method of wafer as claimed in claim 1, wherein in this hydrofluoric acid solution, the mixed proportion of water and hydrofluoric acid was between 1000: 1～10000: 1.
6, the cleaning method of wafer as claimed in claim 1, wherein the temperature of this phosphoric acid solution is 160 degree Celsius.
7, the cleaning method of wafer as claimed in claim 1, wherein the material of this gate dielectric layer comprises that one has the material of high-k (high K).
8, the cleaning method of wafer as claimed in claim 7, wherein this has high dielectric constant materials and comprises hafnium oxide (HfO
2), be mixed with nitrogen hafnium oxide, be mixed with the hafnium oxide of nitrogen and silicon or be mixed with the hafnium oxide of silicon.
9, the cleaning method of wafer as claimed in claim 1, wherein the material on this nitrogenous barrier layer comprises titanium nitride.
10, the cleaning method of wafer as claimed in claim 1, wherein the material of this siliceous grid layer comprises polysilicon or doped polycrystalline silicon.
11, a kind of manufacture method of grid structure comprises:
In a substrate, form a gate dielectric layer;
Form a nitrogenous barrier layer in this gate dielectric layer;
Form a siliceous grid layer in this nitrogenous barrier layer;
Define this siliceous grid layer, this nitrogenous barrier layer and this gate dielectric layer, to form a stack architecture; And
Use phosphoric acid solution and hydrofluoric acid solution that a cleaning step is carried out in this substrate.
12, the manufacture method of grid structure as claimed in claim 11, wherein this cleaning step uses a mixed solution of phosphoric acid solution and hydrofluoric acid solution mixing gained.
13, the manufacture method of grid structure as claimed in claim 11, wherein this cleaning step uses phosphoric acid solution and hydrofluoric acid solution successively.
14, the manufacture method of grid structure as claimed in claim 11, wherein this cleaning step uses hydrofluoric acid solution, phosphoric acid solution and hydrofluoric acid solution successively.
15, the manufacture method of grid structure as claimed in claim 11, wherein in this hydrofluoric acid solution, the mixed proportion of water and hydrofluoric acid was between 1000: 1～10000: 1.
16, the manufacture method of grid structure as claimed in claim 11, wherein the temperature of this phosphoric acid solution is 160 degree Celsius.
17, the manufacture method of grid structure as claimed in claim 11, wherein the material of this gate dielectric layer comprises that one has high dielectric constant materials.
18, the manufacture method of grid structure as claimed in claim 17, wherein this has that high dielectric constant materials comprises hafnium oxide, is mixed with the hafnium oxide of nitrogen, the hafnium oxide that is mixed with the hafnium oxide of nitrogen and silicon or is mixed with silicon.
19, the manufacture method of grid structure as claimed in claim 18, wherein the formation method of this gate dielectric layer comprises and carries out an atom layer deposition process or a metal organic chemical vapor deposition technology.
20, the manufacture method of grid structure as claimed in claim 11, wherein the material on this nitrogenous barrier layer comprises titanium nitride.
21, the manufacture method of grid structure as claimed in claim 11, wherein the material of this siliceous grid layer comprises polysilicon or doped polycrystalline silicon.
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| CNB2005100081300A CN100378922C (en) | 2005-02-05 | 2005-02-05 | Wafer washing method and grid structure mfg. method |
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| CNB2005100081300A CN100378922C (en) | 2005-02-05 | 2005-02-05 | Wafer washing method and grid structure mfg. method |
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| CN100378922C CN100378922C (en) | 2008-04-02 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102097382B (en) * | 2009-12-15 | 2013-07-24 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0641770A (en) * | 1992-07-27 | 1994-02-15 | Daikin Ind Ltd | Treatment for surface of silicon wafer |
| JP2857042B2 (en) * | 1993-10-19 | 1999-02-10 | 新日本製鐵株式会社 | Cleaning liquid for silicon semiconductor and silicon oxide |
| JP3365980B2 (en) * | 1999-08-03 | 2003-01-14 | 花王株式会社 | Detergent composition |
| US7067015B2 (en) * | 2002-10-31 | 2006-06-27 | Texas Instruments Incorporated | Modified clean chemistry and megasonic nozzle for removing backside CMP slurries |
| KR100536593B1 (en) * | 2002-12-05 | 2005-12-14 | 삼성전자주식회사 | Cleaning solution for selectively removing a layer and method for selectively removing the layer in silicide process using the cleaning solution |
| CN1278394C (en) * | 2003-05-12 | 2006-10-04 | 旺宏电子股份有限公司 | Equipment and method for etching silicon nitride thin film |
| CN100352062C (en) * | 2003-10-30 | 2007-11-28 | 上海集成电路研发中心有限公司 | Grid structure from material with high dielectric constant and preparing technique |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102097382B (en) * | 2009-12-15 | 2013-07-24 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
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