CN1674215A - Method for producing blocking-layer - Google Patents
Method for producing blocking-layer Download PDFInfo
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- CN1674215A CN1674215A CN 200410031228 CN200410031228A CN1674215A CN 1674215 A CN1674215 A CN 1674215A CN 200410031228 CN200410031228 CN 200410031228 CN 200410031228 A CN200410031228 A CN 200410031228A CN 1674215 A CN1674215 A CN 1674215A
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- carry out
- barrier layer
- layer
- semiconductor substrate
- acid
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- 238000004519 manufacturing process Methods 0.000 title description 3
- 238000000034 method Methods 0.000 claims abstract description 57
- 239000004065 semiconductor Substances 0.000 claims abstract description 35
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 10
- 230000004888 barrier function Effects 0.000 claims description 56
- 238000005516 engineering process Methods 0.000 claims description 47
- 229910052751 metal Inorganic materials 0.000 claims description 25
- 239000002184 metal Substances 0.000 claims description 25
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 23
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 22
- 239000012528 membrane Substances 0.000 claims description 22
- 239000010936 titanium Substances 0.000 claims description 22
- 229910052719 titanium Inorganic materials 0.000 claims description 22
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 claims description 18
- 229910021332 silicide Inorganic materials 0.000 claims description 17
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 15
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 9
- 229920005591 polysilicon Polymers 0.000 claims description 9
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 claims description 6
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 claims description 6
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 6
- 229910017604 nitric acid Inorganic materials 0.000 claims description 6
- 238000005201 scrubbing Methods 0.000 claims description 6
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 6
- 238000004140 cleaning Methods 0.000 claims description 5
- 239000002253 acid Substances 0.000 claims 6
- 239000002245 particle Substances 0.000 abstract description 4
- 230000000903 blocking effect Effects 0.000 abstract 3
- 230000015572 biosynthetic process Effects 0.000 description 8
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 238000000151 deposition Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 239000010941 cobalt Substances 0.000 description 3
- 229910017052 cobalt Inorganic materials 0.000 description 3
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- 150000001869 cobalt compounds Chemical class 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000008187 granular material Substances 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000006911 nucleation Effects 0.000 description 1
- 238000010899 nucleation Methods 0.000 description 1
- 230000035484 reaction time Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- WNUPENMBHHEARK-UHFFFAOYSA-N silicon tungsten Chemical compound [Si].[W] WNUPENMBHHEARK-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- XJDNKRIXUMDJCW-UHFFFAOYSA-J titanium tetrachloride Chemical compound Cl[Ti](Cl)(Cl)Cl XJDNKRIXUMDJCW-UHFFFAOYSA-J 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
A method for preparing the blocking layer includes providing an semiconductor substrate with at least one conduction layer on it first, then applying chemical vapor deposition process to form Ti / Ti N blocking layer on the conduction layer, finally carrying out detection program and repeating above steps if particle is detected out in Ti / Ti N blocking layer.
Description
Technical field
The invention provides a kind of method of making the barrier layer, particularly a kind of method of utilizing trace routine and recast (rework) technology to make the barrier layer of a high finished product rate.
Background technology
In semiconductor technology, regular meeting produces many particulates (particles) because of many unavoidable factors, and the existence of these particulates, gently the electrical performance of the semiconductor element of then influence part tube core (die) then must be scrapped chip by the gross when serious.Wet-type etching or liquid state (1iquid type scrubber) methods of scrubbing of adopting remove particulate more on the general semiconductor technology; yet this mode only can be removed the particulate that adheres on the semiconductor chip surface film; in case particulate forms in film deposition process simultaneously; or be present in last time on the film surface; that is particulate can be coated when layer film; then liquid state is scrubbed mode and also can't effectively be removed particulate, thereby has a strong impact on the semiconductor technology rate of finished products.
In addition, under the situation that the semiconductor technology live width descends day by day and the element integrated level improves constantly, physical vapor deposition (physical vapor deposition, PVD) technology, as evaporation (evaporation) or sputter (sputtering), can't solve the difficulty that semiconductor technology meets with, particularly when depositing, be easy to the less or depth-width ratio (aspect ratio) of live width and cross the problem that general goal forms hole (voids).Therefore cover (step coverage) good film in order to improve ladder, (chemical vapor deposition, CVD) method is made film, and is good to guarantee film forming shape generally all to adopt chemical vapor deposition.
Though thisly utilize chemical vapor deposition to form film can to obtain ladder and cover preferred film, yet it is easy in the CVD technology because vapour phase forming core (gas phase nucleation) phenomenon, or peel off (peeling) because of the reactor wall residual film, perhaps react incomplete particle and drop and cause particulate to produce, and then influence the rate of finished products of depositing operation.Below common barrier deposition technology is example in the act semiconductor technology, and the reason of particulate formation and the influence electrical to the barrier layer thereof are described.
Please refer to Fig. 1 and Fig. 2, Fig. 1 and Fig. 2 are the schematic diagram of the method on known formation barrier layer.As shown in Figure 1, semi-conductive substrate 10 at first is provided, comprise at least one grid structure 12 on it, sidewall comprises sidewall 14 around the grid structure 12, and also comprises a drain doping region 16 and one source pole doped region 18 in the Semiconductor substrate 10 of grid structure 12 sides.Then on Semiconductor substrate 10, form a dielectric layer 20, and utilize a photoresist pattern (not shown) to remove the dielectric layer 20 of part drain doping region 16 tops, to form a jack 22.
Subsequently as shown in Figure 2, carry out a CVD technology, to form a barrier layer 24 in jack 22 inwalls.Wherein, barrier layer 24 generally is made up of titanium/titanium nitride, and the metal bit line connector (not shown) that is used for improving follow-up formation is to ohmic contact (ohmic contact) ability of Semiconductor substrate 10 and suppress the situation of metallic atom diffusion.As previously mentioned, in CVD technology, in a single day drop, or cause the barrier layer of desire deposition to produce tube core not of uniform size, all can cause particulate 26 as shown in Figure 2 because of vapour phase forming core phenomenon because of the particulate in the reactor.
Be after finishing metal connecting line technology, just can carry out electrical detection at present mostly, and do not reach the expection electrical standard semiconductor element, after utilizing electron microscope observation, can find often because particulate caused, and these tube cores that do not reach electrical standard also can only be handled in the mode of scrapping because of using, and have a strong impact on rate of finished products.Therefore, how to solve particulate and be the important topic in the present semiconductor technology the influence of semiconductor yield is real.
Summary of the invention
Therefore, main purpose of the present invention is to provide a kind of formation method that comprises the barrier layer of trace routine and recast technology, solving the particle issues that known technology can't overcome, and then improves process yield.
The method according to this invention at first provides semi-conductive substrate, and comprises at least one conductive layer on the Semiconductor substrate, then carries out a CVD technology, to form a barrier layer on conductive layer, carries out a trace routine subsequently again.Comprise particulate in the barrier layer if detect, then carry out a recast technology.This recast technology is to carry out an etch process earlier, to remove previous formed barrier layer, then utilize a scrubbing unit (scrubber) to scrub Semiconductor substrate, clean semiconductor substrate surface with cleaning solution then, carry out another CVD technology at last again, on conductive layer, to form another barrier layer.And do not comprise particulate in the barrier layer as if detecting, then omit above-mentioned recast technology.
Because the present invention just carries out a trace routine after forming the barrier layer, and when finding excessive particulate, carry out a recast technology immediately to form the barrier layer again, be different from known technology and take the practice of scrapping, so can significantly improve rate of finished products in finding electrically not good.
Description of drawings
Fig. 1 and Fig. 2 are the schematic diagram of the method on known formation barrier layer;
Fig. 3 to Fig. 6 makes the schematic diagram of the method on barrier layer for the preferred embodiment of the present invention;
Fig. 7 makes the flow chart of barrier layer process for the present invention.
Description of reference numerals
10 Semiconductor substrate, 12 grid structures
14 sidewalls, 16 drain doping region
18 source doping region, 20 dielectric layers
22 jacks, 24 barrier layers
26 particulates, 50 Semiconductor substrate
52 grid structures, 54 drain doping region
56 source doping region, 58 cover layers
60 sidewalls, 62 dielectric layers
64 polysilicon layers, 66 metal silicides
68 dielectric layers, 69 jacks
70 titaniums/titanium nitride membrane 72 particulates
74 titaniums/titanium nitride membrane 76 bit line connectors
78 bit lines 100 form a barrier layer
110 carry out a trace routine 120 carries out a recast technology
130 carry out subsequent technique
Embodiment
For further specifying the inventive method, the barrier layer technology of below lifting metal bit line connector in the semiconductor technology illustrates that the present invention makes the method on barrier layer.Please refer to Fig. 3 to Fig. 6, Fig. 3 to Fig. 6 makes the schematic diagram of the method on barrier layer for the preferred embodiment of the present invention.As shown in Figure 3, at first provide semi-conductive substrate 50, comprise at least one grid structure 52 on it, and comprise a drain doping region 54 and one source pole doped region 56 in the Semiconductor substrate 50 of each grid structure 52 side.In addition, each grid structure 52 includes a cover layer 58 and is positioned at grid structure 52 tops, and sidewall 60 is surrounded on the sidewall of grid structure 52.Wherein, cover layer 58 is made up of silicon nitride usually with sidewall 60, is used for avoiding the contingent short circuit problem of subsequent technique.
Then on Semiconductor substrate 50, form a dielectric layer 62, and utilize a photoresist pattern (not shown) to carry out an etch process, remove part dielectric layer 62, remove photoresist pattern (not shown) subsequently again to form a contact hole (not shown).In the contact hole (not shown), deposit a polysilicon layer 64 then, and form metal silicides (silicide) 66 in polysilicon layer 64 surfaces.Wherein, polysilicon layer 64 is as the usefulness of a switching pad (landing pad), metal silicide 66 is then in order to increase the conductivity on the barrier layer that forms with follow-up desire, in the present embodiment, utilize 64 layers of autoregistration metal silication of cobalt or cobalt compound and polysilicon (salicide) reaction, to form a cobalt silicide (CoSi) layer, as metal silicide 66 in polysilicon layer 64 surfaces.
As shown in Figure 4, then on dielectric layer 62 and metal silicide 66, deposit another dielectric layer 68, and utilize a photoresist pattern (not shown) to come etching part dielectric layer 68, to form a jack 69, remove photoresist pattern (not shown) then in metal silicide 66 tops.Then carry out a chemical vapor deposition process, form one titanium/titanium nitride membrane 70 in metal silicide 66 surfaces and dielectric layer 68 surfaces, as the usefulness on barrier layer.The method that wherein forms titanium/titanium nitride membrane 70 comprises utilizes titanium tetrachloride (TiCl earlier
4) and hydrogen (H
2) in high temperature reaction down,, then feed ammonia (NH down in high temperature again to form a titanium film (not shown) in metal silicide 66 surfaces and dielectric layer 68 surfaces
3) to form the titanium nitride membrane (not shown), to form titanium/titanium nitride membrane 70, as the usefulness on barrier layer in titanium film (not shown) surface.As previously mentioned, in case there is excessive particulate to occur in the barrier layer, can have a strong impact on the electrical performance of semiconductor element.Therefore the present invention is after forming titanium/titanium nitride membrane 70, utilize electron microscope to carry out a trace routine immediately, detecting in titanium/titanium nitride membrane 70 whether comprise excessive and excessive particulate 72, and then judge by the mode in comparison information storehouse whether these particulates 72 can influence conductivity.If influence the technology that conductivity is then carried out follow-up formation bit line through judging that particulate 72 is unlikely, if may influence electrical performance through judging that particulate 72 is excessive, carry out a recast technology immediately with removal particulate 72 and titanium/titanium nitride membrane 70, and form another titanium/titanium nitride membrane again.
As shown in Figure 5, recast technology of the present invention is carried out a wet etch process earlier and is removed particulate (not shown) and titanium/titanium nitride membrane (not shown), and uses phosphoric acid (H in a preferred embodiment of the invention
3PO
4), nitric acid (HNO
3), acetic acid (CH
3COOH) remove particulate 72 and titanium/titanium nitride membrane 70 with the etching solution that mixes of water, phosphoric acid wherein: nitric acid: acetic acid: the preferred volume ratio of water is between (38～41): (1～1.5): (1.8～2.1): between (2.8～3.2), and, be more preferably 40: 1: 2: 3 through the result of practical operation.Utilize above-mentioned etching solution,, particulate 72 and titanium/titanium nitride membrane 70 can be removed fully through about 1400～2000 seconds technological reaction time.Then utilize a scrubbing unit (scrubber) to carry out scrubbing step to remove the particulate (not shown) of metal silicide 66 and dielectric layer 68 remained on surface.Utilize a sulfuric acid solution clean metal silicide 66 and dielectric layer 68 surfaces then, with the titanium/titanium nitride membrane (not shown) of further removing metal silicide 66 remained on surface.Carry out another chemical vapor deposition process at last again, to form another titanium/titanium nitride membrane 74 in metal silicide 66 and dielectric layer 68 surfaces.
Forming titanium/titanium nitride membrane 74 and, can proceed to form the technology of bit line connector by after the trace routine.As shown in Figure 6, prior to depositing a metal level on titanium/titanium nitride membrane 74 and filling up jack 69 (as shown in Figure 5), then carry out a planarization technology, in jack shown in Figure 5 69, to form a bit line connector 76, perhaps directly utilize a photoresist pattern (not shown) to come above-mentioned metal level is carried out an etch process, form required bit line 78 and bit line connector 76 simultaneously to remove the part metals layer.In the present embodiment, bit line connector 76 is a tungsten with the material of bit line 78, uses electric conducting materials such as polysilicon yet the also visual semiconductor element design of bit line 78 is different.
Letter, the present invention just carries out a trace routine in formation behind the barrier layer, and carries out a recast technology when comprising particulate in the barrier layer and form the barrier layer again.Please refer to Fig. 7.Fig. 7 makes the flow chart of barrier layer process for the present invention.The inventive method comprises the following steps:
100: form a barrier layer in semiconductor substrate surface;
110: carry out a trace routine, judge the particulate that whether barrier layer comprises can influence conductivity, carry out step 120, then carry out step 130 if do not have if having then;
120: carry out a recast technology, remove the barrier layer according to above-mentioned step, and form a new barrier layer in addition; And
130: the technology of carrying out follow-up formation bit line connector.
Show according to experimental result, significantly reduce through the included granule amount of formed titanium/titanium nitride membrane after the recast technology, and the semiconductor element of finishing all has the excellent electrical property performance, therefore recast technology of the present invention can effectively improve rate of finished products.It should be noted that, the preferred embodiments of the present invention are with a technology that is used for connecting switching pad and the titanium/titanium nitride membrane of bit line connector method of the present invention to be described, yet the present invention is not limited thereto, in the general semiconductor technology for the demanding barrier layer of electrical performance technology, for example metal plug technology, metal interconnecting technology, dual-damascene technics etc., and the barrier layer of different materials, as cobalt silicide (tungsten silicon), all can utilize the disclosed method of the present invention.Under the prerequisite that does not cause conductive layer (can be a polysilicon layer, a metal level or a metal silicide) to damage, remove original barrier layer, and carry out a recast technology to form a new barrier layer in going up of conductive layer.
Compared to known technology, the method that the present invention forms the barrier layer is utilized a trace routine to judge whether to comprise in the barrier layer that the particulate that influences electrical performance exists, and utilize a recast technology to remove the barrier layer that comprises particulate, form a new barrier layer then, guaranteeing that the barrier layer has preferred conductivity, and then effectively reduce manufacturing cost and increase rate of finished products.
The above only is the preferred embodiments of the present invention, and all equal variation and modifications of doing according to claims of the present invention all should belong to the covering scope of patent of the present invention.
Claims (15)
1. method that forms the barrier layer comprises:
(a) provide semi-conductive substrate, and comprise a jack at least on this Semiconductor substrate;
(b) carry out a chemical vapor deposition process, on this semiconductor substrate surface and this jack inner wall surface, form one titanium/titanium nitride membrane as this barrier layer;
(c) carry out a trace routine, wherein comprise particulate, then carry out step (d) as if detecting in this barrier layer; And
(d) carry out a recast technology, comprising:
Carry out an etch process, remove this barrier layer;
Utilize a scrubbing unit to scrub this Semiconductor substrate, to remove particulate;
Utilize a cleaning solution to clean this semiconductor substrate surface; And
Carry out another chemical vapor deposition process, in this jack, to form another titanium/titanium nitride membrane.
2. the method for claim 1, wherein this etch process is a wet etch process.
3. method as claimed in claim 2, wherein this wet etch process utilizes an acid solution to carry out etching, and this acid solution is by phosphoric acid (H
3PO
4): nitric acid (HNO
3): acetic acid (CH
3COOH): water (H
2O) form.
4. method as claimed in claim 3, wherein phosphoric acid in this acid solution: nitric acid: acetic acid: the volume ratio of water is between (38～41): (1～1.5): (1.8～2.1): between (2.8～3.2).
5. the method for claim 1, wherein this cleaning solution is a sulfuric acid solution.
6. the method for claim 1, wherein this trace routine is used to detect the particulate that influences electrical performance.
7. method that forms the barrier layer comprises:
(a) provide semi-conductive substrate, and comprise a conductive layer at least on this Semiconductor substrate;
(b) carry out a chemical vapor deposition process, on this conductive layer, form a barrier layer;
(c) carry out a trace routine, wherein comprise particulate, then carry out step (d) as if detecting in this barrier layer; And
(d) carry out a recast technology, comprising:
Carry out an etch process, remove this barrier layer;
Utilize a scrubbing unit to scrub this Semiconductor substrate, to remove particulate;
Utilize a cleaning solution to clean this semiconductor substrate surface; And
Carry out another chemical vapor deposition process, on this conductive layer, to form another barrier layer.
8. method as claimed in claim 7, wherein this barrier layer is one titanium/titanium nitride membrane.
9. method as claimed in claim 7, wherein this conductive layer is a polysilicon layer.
10. method as claimed in claim 7, wherein this conductive layer is a metal silicide layer.
11. method as claimed in claim 7, wherein this conductive layer is a metal level.
12. method as claimed in claim 7, wherein this etch process is a wet etch process.
13. method as claimed in claim 12, wherein this wet etch process utilizes an acid solution to carry out etching, and this acid solution is by phosphoric acid (H
3PO
4): nitric acid (HNO
3): acetic acid (CH
3COOH): water (H
2O) form.
14. method as claimed in claim 13, wherein phosphoric acid in this acid solution: nitric acid: acetic acid: the volume ratio of water is between (38～41): (1～1.5): (1.8～2.1): between (2.8～3.2).
15. method as claimed in claim 7, wherein this cleaning solution is a sulfuric acid solution.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100312283A CN100367450C (en) | 2004-03-26 | 2004-03-26 | Method for producing blocking-layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100312283A CN100367450C (en) | 2004-03-26 | 2004-03-26 | Method for producing blocking-layer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1674215A true CN1674215A (en) | 2005-09-28 |
| CN100367450C CN100367450C (en) | 2008-02-06 |
Family
ID=35046644
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2004100312283A Expired - Fee Related CN100367450C (en) | 2004-03-26 | 2004-03-26 | Method for producing blocking-layer |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100367450C (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100435316C (en) * | 2006-05-15 | 2008-11-19 | 中芯国际集成电路制造(上海)有限公司 | Method for forming connecting hole with high depth and width ratio |
| CN101466863B (en) * | 2006-04-11 | 2011-08-10 | 应用材料股份有限公司 | Process for forming cobalt-containing materials |
| CN104183481A (en) * | 2014-08-27 | 2014-12-03 | 上海华力微电子有限公司 | Method for improving deposition quality of metal barrier layer |
| CN104465357A (en) * | 2014-12-31 | 2015-03-25 | 上海华虹宏力半导体制造有限公司 | Schottky diode blocking layer forming method |
| CN110112119A (en) * | 2018-02-01 | 2019-08-09 | 联华电子股份有限公司 | The production method of bit line |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4822753A (en) * | 1988-05-09 | 1989-04-18 | Motorola, Inc. | Method for making a w/tin contact |
| TW406317B (en) * | 1997-06-27 | 2000-09-21 | Siemens Ag | Method to produce a barrier-layer in a semiconductor-body and semiconductor component with such a barrier-layer |
| US6369410B1 (en) * | 1997-12-15 | 2002-04-09 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of manufacturing the semiconductor device |
| US6140224A (en) * | 1999-04-19 | 2000-10-31 | Worldiwide Semiconductor Manufacturing Corporation | Method of forming a tungsten plug |
-
2004
- 2004-03-26 CN CNB2004100312283A patent/CN100367450C/en not_active Expired - Fee Related
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101466863B (en) * | 2006-04-11 | 2011-08-10 | 应用材料股份有限公司 | Process for forming cobalt-containing materials |
| CN100435316C (en) * | 2006-05-15 | 2008-11-19 | 中芯国际集成电路制造(上海)有限公司 | Method for forming connecting hole with high depth and width ratio |
| CN104183481A (en) * | 2014-08-27 | 2014-12-03 | 上海华力微电子有限公司 | Method for improving deposition quality of metal barrier layer |
| CN104183481B (en) * | 2014-08-27 | 2019-12-13 | 上海华力微电子有限公司 | Method for improving deposition quality of metal barrier layer |
| CN104465357A (en) * | 2014-12-31 | 2015-03-25 | 上海华虹宏力半导体制造有限公司 | Schottky diode blocking layer forming method |
| CN104465357B (en) * | 2014-12-31 | 2017-08-08 | 上海华虹宏力半导体制造有限公司 | The forming method of Schottky diode barrier |
| CN110112119A (en) * | 2018-02-01 | 2019-08-09 | 联华电子股份有限公司 | The production method of bit line |
| US11239241B2 (en) | 2018-02-01 | 2022-02-01 | United Microelectronics Corp. | Bit line utilized in DRAM |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100367450C (en) | 2008-02-06 |
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