CN100435316C - Method for forming connecting hole with high depth and width ratio - Google Patents
Method for forming connecting hole with high depth and width ratio Download PDFInfo
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- CN100435316C CN100435316C CNB2006100265629A CN200610026562A CN100435316C CN 100435316 C CN100435316 C CN 100435316C CN B2006100265629 A CNB2006100265629 A CN B2006100265629A CN 200610026562 A CN200610026562 A CN 200610026562A CN 100435316 C CN100435316 C CN 100435316C
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Abstract
This is a process method for connecting spout plug of high depth/width ratio. First make a Ti layer by IMP technology, and a TiN layer by MOCVD technology, then rapid thermal anneal the Ti/TiN layer to upgrade its performance, then fill in tungsten by PNL technology to form spout plug of depth/width ratio over 10:1.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of method that forms the connecting hole with high depth and width ratio in the integrated circuit.
Background technology
The making of semiconductor integrated circuit is extremely complicated process, and purpose is various electronic building bricks and circuit that particular electrical circuit is required, dwindles on the wafer that is produced on small size.Wherein, each assembly must electrically connect by suitable internal connecting line, the competence exertion desired function.
Because the making of integrated circuit is to very lagre scale integrated circuit (VLSIC) (ULSI) development, its inner current densities is increasing, along with contained number of elements in the chip constantly increases, has in fact just reduced the free space of surperficial line.This way to solve the problem is to adopt the design of multiple layer metal lead, just utilizes multilayer dielectric layer to be connected with the multilayer of conductive layer mutual superposition, and it utilizes the connecting hole of filling with metal filled up plug in a large number, forms electric pathway between double layer of metal.
Development along with the semiconductor element Highgrade integration, the size of connecting hole reduces, the degree of depth deepens, depth-to-width ratio (AR, Aspect Ratio) constantly increase, for example, in the deep submicron process of critical live width CD below 0.16 μ m, the depth-to-width ratio AR of the connecting hole of DRAM device meta on-trace capacitors (COB, Capacitor Over Bit) is greater than 10: 1.Usually need in the connecting hole of this high-aspect-ratio to fill tungsten (W), but because tungsten and oxide adhesion are not strong with the CVD method, and if the tungsten deposit directly on silicon face, carry out reactant WF
6Can react with the silicon of lower floor, cause to the consumption of silicon and to the lateral corrasion of substrate, formed WSi
xResistivity also higher relatively, so must first deposit one deck adhesion layer before the CVD of tungsten deposit and one deck barrier layer.This adhesion layer/barrier layer makes tungsten fully to stick on the oxide of connecting hole, and prevents WF effectively
6React with silicon substrate and oxide.At present first-selected is with Ti as adhesion layer, plays the barrier layer and sticks tungsten with TiN.Ti and oxide have extraordinary adhesive, and can form TiSi with pasc reaction
x, reduce contact resistance greatly; And the TiN layer has the Ti of preventing layer and WF on the one hand
6Between the effect of reaction, have good adhesion with tungsten on the other hand.Adhesion layer Ti normally utilizes Ionized metallic plasma (IMP, IonizedMetal Plasma) technology to form in the prior art, and barrier layer TiN utilizes chemical vapor deposition (CVD, ChemicalVapor Deposition) technology to form usually.
Figure 1A to 1C is the filling process schematic diagram of connecting hole with high depth and width ratio in the prior art.Shown in Figure 1A, the thick interlayer dielectric 102 of deposit on Semiconductor substrate 101, and utilize photoetching, lithographic technique to remove interlayer dielectric 102 on the contact portion of Semiconductor substrate 101, expose substrate surface and form hole 103.Then, shown in Figure 1B, utilize IMP method and CVD method 103 bottom surface and side surface deposit adhesion layer (Ti) 104 and barrier layer (TiN) 105 in the hole respectively; Can be in deposition when the IMP method forms Ti the pasc reaction of original position (in suit) and bottom form TiSix contact layer 106, thereby form good electrical contact with electrode in the substrate.Then, shown in Fig. 1 C, in connecting hole, utilize CVD technology to fill tungsten 107, last, on the barrier layer in the outside of described tungsten layer and connecting hole, form the metal level of aluminium, utilize photoetching, lithographic technique to form the figure of metal line again.
Application number is the CVD formation method that discloses a kind of TiN of generation barrier layer in 200410031228.3 the Chinese patent.Because the defective of IMP technology itself, the bottom ladder of Ti (bottomstep coverage) covering power is relatively poor in the IMP technology, and the deposition of bottom Ti can not form enough TiSi
x, make in the contact layer 106 of bottom hole to occur, shown in Figure 1B, cause contact resistance to increase.For fear of the problems referred to above, the connecting hole for deep submicron process, big depth-to-width ratio does not adopt IMP technology usually in the forming process of its adhesion layer, and adopts CVD method deposit Ti adhesion layer and TiN barrier layer.Usually utilize TiCl at present
4With H
2And NH
3Ti and TiN layer are formed on the bottom that is reflected at connecting hole.When Fig. 2 reaches 11: 1 the connecting hole of COB electric capacity for forming depth-to-width ratio AR, utilize TiCl respectively
4With H
2And NH
3After being reflected at the bottom and the sidewall formation Ti/TiN layer of connecting hole and using the IMP method to form the Ti/CVDTiN layer, utilize the CVD method to carry out the statistics of the square resistance mean value of a plurality of wafers after tungsten is filled again.201 expressions is the statistics that adopts the CVD method among the figure; 202 expressions is the statistics of prolonging with the IMP method among the figure.Can see that 202 result will be apparently higher than 201 result.Therefore for connecting hole,, will cause device performance poor, can not normally use if press hour used IMP prepared of original depth-to-width ratio with big depth-to-width ratio.If but adopt TiCl
4With H
2And NH
3The bottom and the sidewall that are reflected at connecting hole form Ti and TiN layer, then need expensive equipment, have improved production cost.
Summary of the invention
Therefore, the object of the present invention is to provide a kind of method that forms connecting hole with high depth and width ratio, this method under the situation that does not increase production cost, solves the bigger problem of contact resistance when having technology formation connecting hole with high depth and width ratio now by existing technology is optimized.
For achieving the above object, the invention provides a kind of method that forms connecting hole with high depth and width ratio, this method comprises:
A forms the hole on dielectric film;
B forms adhesion layer with the bottom and the sidewall of Ionized metallic plasma IMP method in described hole;
C forms the barrier layer with metal organic chemical vapor deposition MOCVD method on described adhesion layer surface;
The d quick thermal annealing process;
E utilizes pulse nucleating layer PNL technology to fill metal in described hole and forms connecting hole.Wherein, adhesion layer described in the step b is the Ti layer, and its thickness arrives 200
Between, the Ti bias voltage scope that adopts when forming adhesion layer Ti layer at 200V between the 800V; Barrier layer described in the step c is a Ti N layer, and its thickness arrives 50
Between, the reacting gas that feeds when forming barrier layer TiN layer is four dimethyl acyl ammonia titanium TDMAT.
Wherein, the temperature of quick thermal annealing process described in the steps d between 400 to 800 ℃, the time between 10 to 50 seconds, and quick thermal annealing process gases used be nitrogen, its flow at 1sccm between the 20sccm.
In addition, further comprise among the described step e:
E1: initial step;
E2: nucleation step:
E3: filling step.
Wherein, used reacting gas is B among the described step e1
2H
6And WF
6, B
2H
6Flow at 50sccm between the 300sccm, WF
6Flow at 50sccm between the 200sccm.
And, feed gas carrier argon gas, described reacting gas B when feeding described reacting gas
2H
6, WF
6And the flow-rate ratio between gas carrier is between 1: 1: 1 to 1: 10: 100.
Wherein, the feeding of described reacting gas and gas carrier and extraction are periodic, and the feeding time in each cycle can be at 50ms between the 10s, and the time of the extraction in each cycle can be at 1s between the 30s.
Wherein, used reacting gas is SiH among the described step e2
4And WF
6, SiH
4Flow at 10sccm between the 300sccm, WF
6Flow at 10sccm between the 300sccm.
And, feed gas carrier argon gas, described reacting gas SiH when feeding described reacting gas
4, WF
6And the flow-rate ratio between gas carrier is between 1: 1: 1 to 1: 10: 100.
Wherein, the feeding of described reacting gas and gas carrier and extraction are periodic, and the feeding time in each cycle can be at 50ms between the 10s, and the time of the extraction in each cycle can be at 1s between the 30s.
Wherein, used reacting gas is WF among the described step e3
6And H
2, WF
6Flow at 50sccm between the 300sccm, H
2Flow at 1000sccm between the 4000sccm.
And, feed gas carrier argon gas, described reacting gas WF when feeding described reacting gas
6, H
2And the flow-rate ratio between gas carrier is between 1: 1: 1 to 1: 200: 20.
Wherein, the technological temperature among the described step e is between 200 to 500 ℃.
Compared with prior art, the present invention has the following advantages:
The present invention is by the optimization of process conditions, prolonging with ionized metal plasma (IMP, IonizedMetal Plasma) deposition techniques Ti layer, form with metal organic chemical vapor deposition MOCVD technology under the situation of TiN layer, form the TiSi of low-resistance by rapid thermal annealing (RTA, Rapid Thermal Anneal) technology
xOptimize the covering quality of formed Ti/TiN layer, and then adopt less pulse nucleating layer (PNL, the Pulsed Nucleation Layer) technology of contact resistance to fill tungsten to form stopple, realized for the manufacturing of depth-to-width ratio greater than the connecting hole of 10: 1 high-aspect-ratio, low contact resistance.On the one hand the performance of the connecting hole of its formation connecting hole that can form with the CVD method compares favourably, and it has overcome some inherent defects of existing CVD deposit Ti/TiN layer on the other hand, as problems such as easy pollution, reliability are relatively poor.Simultaneously,, need not to purchase new equipment, also reduced production cost because of the present invention prolongs with depth-to-width ratio hour used equipment.
Description of drawings
Figure 1A to 1C is for forming the device profile schematic diagram of connecting hole process in the explanation prior art;
Fig. 2 is the square resistance comparison diagram that adopts the connecting hole of prior art and original technology formation respectively;
Fig. 3 is the process chart of formation connecting hole with high depth and width ratio of the present invention;
Fig. 4 A to 4E forms the device profile schematic diagram of connecting hole process for explanation the present invention;
Fig. 5 is the square resistance comparison diagram that adopts the connecting hole of prior art and the technology of the present invention formation respectively.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing.
In the deep sub-micron technique below critical live width CD narrows down to 0.16 μ m, the depth-to-width ratio AR of COB electric capacity connecting hole is greater than 10: 1 in the DRAM device, if still prolong with hour used IMP technology of original depth-to-width ratio and CVD technology and form adhesion/barrier Ti/TiN and mesoporous metal tungsten in the connecting hole, can under so big depth-to-width ratio, be difficult to realize the step coverage rate of enough connecting hole bottoms because of the IMP method, and cause the increase of contact resistance, utilize CVD technology metals deposited tungsten simultaneously, be subjected to the material beneath quality influence bigger, its contact resistance also is difficult to reduce, and makes device performance obviously descend.Therefore generally use the CVD method instead, use TiCl
4Respectively with H
2, NH
3The mode that reaction generates Ti and TiN forms adhesion layer Ti and barrier layer TiN at the bottom and the sidewall of connecting hole.But adopt this process need purchase new equipment, and the equipment of realizing this technology is very expensive, in addition, it also exists reaction temperature higher, easily pollute, the easy stress of formed Ti/TiN layer and cause micro-fractures, and have more chlorine and remain in the barrier layer, influence adhering to of tungsten, problem such as reliability is relatively poor.The method of formation connecting hole with high depth and width ratio of the present invention by existing technology is optimized, has not only obtained lower contact resistance, its can with utilize TiCl
4The CVD method reach same effect, and greatly reduce production cost.
Fig. 3 is the process chart of formation connecting hole with high depth and width ratio of the present invention, and Fig. 4 A to 4E forms the device profile schematic diagram of connecting hole process for explanation explanation the present invention.
As shown in Figure 3, and in conjunction with Fig. 4, the implementation method following steps of one embodiment of the present of invention: at first, etching formation hole 103 (S301).The thick interlayer dielectric 102 of deposit on wafer 101, the part of utilizing photoetching, lithographic technique to carve contact on interlayer dielectric 102 forms hole 103, and it is carried out pre-clean processes, shown in Fig. 4 A.
Then, utilize Ionized metallic plasma IMP technology to form adhesion layer (S302), shown in Fig. 4 B.Fig. 4 B is the device architecture schematic diagram behind the formation adhesion layer Ti layer 104 in the present embodiment.The IMP method is widely used in the less technology of original depth-to-width ratio, it is that metal with sputter is in RF plasma intermediate ionization, on wafer, added simultaneously negative bias voltage, guide positive metal ion along vertical-path towards movement of wafers, make the film of institute's deposit still have higher consistency in the bottom and the corner in the gap of bigger depth-to-width ratio.In addition, added bias voltage can also be used for controlling the energy of incident metal ion, reduces the damage to wafer surface.But after critical live width CD further dwindled, its gradient coating performance also can not meet the demands, so substituted by the CVD technology gradually.In the present embodiment, by improvement to conventional I MP process conditions, thicker Ti layer in the growth fraction conventional I MP technology, scope can arrive 200
Between, such as being
The Ti bias voltage that employing is higher than conventional I MP technology, scope can be at 200V between the 800V, such as being 300V, improved the step coverage rate of the Ti layer 104 of institute's deposit, realized original IMP technology irrealizable to the better covering of depth-to-width ratio greater than 10: 1 connecting hole.
Then, utilize metal organic chemical vapor deposition MOCVD method to form TiN barrier layer 105 (S303), shown in Fig. 4 C.Fig. 4 C is the device architecture schematic diagram after this step of realization.This layer growth thickness can
Arrive
Between, as
Its used reacting gas is generally four dimethyl acyl ammonia titaniums (TDMAT), and its molecular formula is Ti[N (CH
3)
2]
4Desired reaction temperature is below 400 ℃.The MOCVD technology can be implemented in the comprehensive growth in the deep hole, and therefore the film that grows all has good spreadability on the bottom in hole, sidewall.But its shortcoming is to contain impurity such as higher C, O in the film of institute's deposit, makes the film quality comparatively loose, and membranous less stable can cause film resistor to increase in time.This point is improved by following rapid thermal annealing in the present embodiment.
Subsequently, carry out quick thermal annealing process (S304), shown in Fig. 4 D.Fig. 4 D is the device architecture schematic diagram that utilizes after the rapid thermal annealing method is improved Ti/TiN layer performance.In this step process, can be implemented in further reaction takes place between Ti adhesion layer 104 and the Si material, form the TiSi of low-resistance
xCompound 106 obviously improves the device electrical characteristics, in the present embodiment because with the IMP deposition techniques thicker Ti layer, in this step annealing technology, also can form enough thick TiSi
xCompound 106 reaches electrical property preferably; In addition, this step process also can be removed the impurity in the barrier layer 105 that front MOCVD deposit forms, and plays the elimination membrane stress, reduces film resistor, improves the effect of thin film stability.The condition of this step process can be set to: annealing temperature is between 400 to 800 ℃, and as 600 ℃, annealing time as 40 seconds, gases usedly can be nitrogen between 10 to 50 seconds, and its range of flow between the 20sccm, as is 10sccm at 1sccm.
So far, the formation of adhesion layer and obstruction layer finishes.Then, utilize the PNL method to carry out tungsten and fill formation stopple (S305).For further improving the device electrical characteristics, the present invention also fills tungsten to next step and also improves with the technology that forms stopple, no longer adopts traditional CVD method to form tungsten layer, but has utilized pulse nucleating layer PNL technology.Fig. 4 E is the structural profile schematic diagram that carries out after tungsten is filled formation stopple 107.Shown in Fig. 4 E, the pulse nucleating layer PNL technology of present embodiment utilization is that cycle alternation carries out the process of the continuous impulse of reactant by the adding removing cycle in reaction time.This technology is compared with traditional CVD method, and characteristics are that its reacting gas periodically feeds in regular turn.
That the PNL technical process can be divided into is initial, nucleation and filling for three steps, in initial sum nucleation step, be feeding and the extraction operation of finishing reacting gas with pulse mode, have gas carrier when wherein feeding reacting gas and feed simultaneously that used gas carrier is an argon gas in the present embodiment.
Used reacting gas is B in the initial step of the first step
2H
6And WF
6The former range of flow is between 50sccm to 300sccm, as 150sccm; The latter's range of flow is between 50sccm to 200sccm, as 100sccm.The range of flow of the gas carrier that charges into simultaneously can be between 100sccm to 5000sccm, as 1000sccm.The flow-rate ratio of three kinds of gases can be between 1: 1: 1 to 1: 10: 100, as is 1: 3: 5.
In the nucleation step in second step, be to utilize silane (SiH
4) and tungsten hexafluoride (WF
6) as reacting gas deposit tungsten layer.Wherein, concrete technological parameter can be provided with as follows: SiH
4Flow can be between 10sccm to 300sccm, as be 100sccm; WF
6Flow can be between 10sccm to 300sccm, as is 100sccm; Still used gas carrier in the step before can adopting, the flow-rate ratio of three kinds of gases can be between 1: 1: 1 to 1: 10: 100, as is 1: 3: 5.
In addition, in this two step, the feeding time of the reacting gas in each cycle and gas carrier can be at 50ms between the 10s, as 2s; The time of the extraction in each cycle can be at 1s between the 30s, as 5s.
The 3rd step was a filling process, and what this step adopted is the current constant mode operation, and the reacting gas of feeding is WF
6And H
2, wherein, the former range of flow is between 50sccm to 300sccm, as 100sccm; The latter's range of flow is between 1000sccm to 4000sccm, as 1000sccm.Consistent in used gas carrier and the first two steps, and the flow-rate ratio of three kinds of gases can be between 1: 1: 1 to 1: 200: 20, as be 1: 100: 10.
Utilize the reaction temperature of PNL technology filling tungsten lower, can be controlled between 200 to 500 ℃, as 200 ℃.And, because of its reaction only occurs on the surface, can form densification, level and smooth tungsten layer, in addition, this method has lower surface sensitivity, higher step coverage rate, filling the tungsten technology with traditional CVD method compares, filling effect is better, can form lower contact resistance, has improved the electrical characteristics of device effectively.
Fig. 5 is the square resistance comparison diagram that adopts the connecting hole of prior art and the technology of the present invention formation respectively.Wherein 501 is available technology adopting CVD method TiCl
4Deposit Ti/TiN layer, the mean value statistics of the square resistance of a plurality of wafers behind the usefulness CVD method filling tungsten again; The 502nd, employing the technology of the present invention forms the mean value statistics of the square resistance of a plurality of wafers behind the connecting hole.Can see that after present embodiment had carried out the combination of a plurality of process conditions and optimized, the square resistance among the preparation result was compared with Fig. 2, obvious decline has been arranged, dropped between 375 to 410ohm/ea, mean value is 391ohm/ea, has reached effect same as the prior art.Simultaneously, it is relatively poor to utilize the process of present embodiment also to overcome the reliability of existing CVD deposit Ti/TiN layer, easily wafer surface and vacuum system is polluted, and reaction temperature is crossed problems such as height.And, need not to purchase new equipment, and reduced production cost because of the present invention prolongs with depth-to-width ratio hour used equipment.
Among the above-described embodiment, in PNL technology, used gas carrier is an argon gas, in other embodiments of the invention, can also be the multiple gas that has nothing to do with reaction such as helium, nitrogen, neon or xenon.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (22)
1, a kind of formation depth-to-width ratio is characterized in that greater than the method for 10: 1 connecting hole, and described method comprises:
A forms the hole on dielectric film;
B forms adhesion layer with the bottom and the sidewall of Ionized metal plasma body method in described hole, and described adhesion layer is the Ti layer, and its thickness arrives 200
Between, the Ti bias voltage scope that adopts when forming adhesion layer Ti layer at 200V between the 800V;
C forms the barrier layer with the metal organic chemical vapor deposition method on described adhesion layer surface, and described barrier layer is the TiN layer;
The d quick thermal annealing process, the temperature of described quick thermal annealing process is between 400 to 800 ℃, the time of described quick thermal annealing process, described quick thermal annealing process is gases used to be nitrogen between 10 to 50 seconds, the flow of described nitrogen at 1sccm between the 20sccm;
E utilizes pulse nucleating layer technology to fill metal W in described hole and forms connecting hole.
2, the method for claim 1 is characterized in that: described barrier layer thickness arrives 50
Between.
3, method as claimed in claim 2 is characterized in that: the reacting gas that feeds during the TiN layer of described formation barrier layer is four dimethyl acyl ammonia titaniums.
4, the method for claim 1 is characterized in that: further comprise among the described step e:
E1: initial step;
E2: nucleation step:
E3: filling step.
5, method as claimed in claim 4 is characterized in that: used reacting gas is B among the described step e1
2H
6And WF
6
6, method as claimed in claim 5 is characterized in that: described reacting gas B
2H
6Flow at 50sccm between the 300sccm, described reacting gas WF
6Flow at 50sccm between the 200sccm.
7, method as claimed in claim 5 is characterized in that: feed gas carrier when feeding described reacting gas.
8, method as claimed in claim 7 is characterized in that: described gas carrier is an argon gas.
9, method as claimed in claim 7 is characterized in that: described reacting gas B
2H
6, WF
6And the flow-rate ratio between gas carrier is between 1: 1: 1 to 1: 10: 100.
10, method as claimed in claim 7 is characterized in that: the feeding of described reacting gas and gas carrier and extraction are periodic, the feeding time in each cycle at 50ms between the 10s, the time of the extraction in each cycle at 1s between the 30s.
11, method as claimed in claim 4 is characterized in that: used reacting gas is SiH among the described step e2
4And WF
6
12, method as claimed in claim 11 is characterized in that: described reacting gas SiH
4Flow at 10sccm between the 300sccm, described reacting gas WF
6Flow at 10sccm between the 300sccm.
13, method as claimed in claim 11 is characterized in that: feed gas carrier when feeding described reacting gas.
14, method as claimed in claim 13 is characterized in that: described gas carrier is an argon gas.
15, method as claimed in claim 13 is characterized in that: described reacting gas SiH
4, WF
6And the flow-rate ratio between gas carrier is between 1: 1: 1 to 1: 10: 100.
16, method as claimed in claim 13 is characterized in that: the feeding of described reacting gas and gas carrier and extraction are periodic, the feeding time in each cycle at 50ms between the 10s, the time of the extraction in each cycle at 1s between the 30s.
17, method as claimed in claim 4 is characterized in that: used reacting gas is WF among the described step e3
6And H
2
18, method as claimed in claim 17 is characterized in that: described reacting gas WF
6Flow at 50sccm between the 300sccm, described reacting gas H
2Flow at 1000sccm between the 4000sccm.
19, method as claimed in claim 17 is characterized in that: feed gas carrier when feeding described reacting gas.
20, method as claimed in claim 19 is characterized in that: described gas carrier is an argon gas.
21, method as claimed in claim 19 is characterized in that: described reacting gas WF
6, H
2And the flow-rate ratio between gas carrier is between 1: 1: 1 to 1: 200: 20.
22, the method for claim 1 is characterized in that: the technological temperature among the described step e is between 200 to 500 ℃.
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| KR101263856B1 (en) * | 2008-12-31 | 2013-05-13 | 어플라이드 머티어리얼스, 인코포레이티드 | Method of depositing tungsten film with reduced resistivity and improved surface morphology |
| CN104716055B (en) * | 2013-12-11 | 2017-09-29 | 中芯国际集成电路制造(上海)有限公司 | Wafer-level packaging method |
| CN105514028A (en) * | 2015-12-31 | 2016-04-20 | 上海华虹宏力半导体制造有限公司 | Process for enlarging a Ti/TiN stress window |
| CN109103139B (en) * | 2018-08-14 | 2020-11-20 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing semiconductor through hole |
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| WO2001027982A1 (en) * | 1999-10-12 | 2001-04-19 | Advanced Micro Devices, Inc. | Method and apparatus for lining contact, via and trench layers with high-density ionized metal plasma (imp) titanium and cvd titanium nitride layers |
| US20050031786A1 (en) * | 2001-05-22 | 2005-02-10 | Novellus Systems, Inc. | Method for reducing tungsten film roughness and improving step coverage |
| KR20040086858A (en) * | 2003-03-22 | 2004-10-13 | 주식회사 하이닉스반도체 | A method for forming a bit line of semiconductor device |
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