CN104716055B - Wafer-level packaging method - Google Patents
Wafer-level packaging method Download PDFInfo
- Publication number
- CN104716055B CN104716055B CN201310675699.7A CN201310675699A CN104716055B CN 104716055 B CN104716055 B CN 104716055B CN 201310675699 A CN201310675699 A CN 201310675699A CN 104716055 B CN104716055 B CN 104716055B
- Authority
- CN
- China
- Prior art keywords
- layer
- wafer
- semiconductor crystal
- crystal wafer
- level packaging
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 49
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 35
- 239000004065 semiconductor Substances 0.000 claims abstract description 102
- 238000002955 isolation Methods 0.000 claims abstract description 82
- 239000013078 crystal Substances 0.000 claims abstract description 73
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 28
- 229910052751 metal Inorganic materials 0.000 claims abstract description 25
- 239000002184 metal Substances 0.000 claims abstract description 25
- 238000002161 passivation Methods 0.000 claims abstract description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 37
- 238000006243 chemical reaction Methods 0.000 claims description 24
- 239000000377 silicon dioxide Substances 0.000 claims description 23
- 230000008569 process Effects 0.000 claims description 19
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 18
- 235000012239 silicon dioxide Nutrition 0.000 claims description 12
- 239000007789 gas Substances 0.000 claims description 11
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 8
- 239000003085 diluting agent Substances 0.000 claims description 6
- 239000011261 inert gas Substances 0.000 claims description 4
- 238000010790 dilution Methods 0.000 claims 1
- 239000012895 dilution Substances 0.000 claims 1
- 238000012360 testing method Methods 0.000 description 14
- 239000000853 adhesive Substances 0.000 description 10
- 230000001070 adhesive effect Effects 0.000 description 10
- 229910052681 coesite Inorganic materials 0.000 description 10
- 229910052906 cristobalite Inorganic materials 0.000 description 10
- 229910052682 stishovite Inorganic materials 0.000 description 10
- 229910052905 tridymite Inorganic materials 0.000 description 10
- 238000010586 diagram Methods 0.000 description 7
- 239000003795 chemical substances by application Substances 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 4
- 238000005336 cracking Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000005538 encapsulation Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 239000000843 powder Substances 0.000 description 3
- 238000000926 separation method Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- -1 Xi Yin Chemical compound 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 238000013467 fragmentation Methods 0.000 description 2
- 238000006062 fragmentation reaction Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 239000004836 Glue Stick Substances 0.000 description 1
- ZCQWOFVYLHDMMC-UHFFFAOYSA-N Oxazole Chemical compound C1=COC=N1 ZCQWOFVYLHDMMC-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 1
- PSMFTUMUGZHOOU-UHFFFAOYSA-N [In].[Sn].[Bi] Chemical compound [In].[Sn].[Bi] PSMFTUMUGZHOOU-UHFFFAOYSA-N 0.000 description 1
- WGCXSIWGFOQDEG-UHFFFAOYSA-N [Zn].[Sn].[In] Chemical compound [Zn].[Sn].[In] WGCXSIWGFOQDEG-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 238000004026 adhesive bonding Methods 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000003064 anti-oxidating effect Effects 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- RHZWSUVWRRXEJF-UHFFFAOYSA-N indium tin Chemical compound [In].[Sn] RHZWSUVWRRXEJF-UHFFFAOYSA-N 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- LQBJWKCYZGMFEV-UHFFFAOYSA-N lead tin Chemical compound [Sn].[Pb] LQBJWKCYZGMFEV-UHFFFAOYSA-N 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 238000004375 physisorption Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229920006389 polyphenyl polymer Polymers 0.000 description 1
- 239000000376 reactant Substances 0.000 description 1
- 230000036632 reaction speed Effects 0.000 description 1
- 238000006479 redox reaction Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000004062 sedimentation Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- GZCWPZJOEIAXRU-UHFFFAOYSA-N tin zinc Chemical compound [Zn].[Sn] GZCWPZJOEIAXRU-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000009736 wetting Methods 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
- 239000011701 zinc Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/43—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Element Separation (AREA)
Abstract
A kind of wafer-level packaging method, including：Semiconductor crystal wafer is provided, the semiconductor crystal wafer includes first surface and second surface, in the first surface formation groove of the semiconductor crystal wafer；In the semiconductor crystal wafer and the bottom of the groove and side wall formation adhesion auxiliary layer；Isolation layer is formed on the adhesion auxiliary layer；Along isolation layer described in the recess etch and adhesion auxiliary layer, the isolation layer and adhesion auxiliary layer of the bottom portion of groove are removed, exposes the semiconductor crystal wafer；Metal interconnecting wires layer is formed on the isolation layer, the side wall of the groove, and the exposed semiconductor crystal wafer of the bottom portion of groove；Afterwards, the structures such as pad, passivation layer, soldered ball are formed on metal interconnecting wires layer, completes wafer-level packaging.In above-mentioned technical proposal, one layer of adhesion auxiliary layer is formed on a semiconductor wafer, afterwards, is to form the isolation layer above the adhesion auxiliary layer, so as to effectively improve the bond strength of the isolation layer and semiconductor crystal wafer.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly, to a kind of wafer-level packaging method.
Background technology
Wafer-level packaging (Wafer Level Packaging, WLP) is one kind of chip package mode, is full wafer wafer
After the completion of production, packaging and testing is carried out directly on wafer, single chip is just cut into after completion, is not necessary to by routing
Or filler.Wafer-level packaging have the advantages that package dimension is small and encapsulation after excellent electrical properties, wafer-level packaging be also easy to it is brilliant
Circle manufacture and chip assemble compatibility, simplify the process that wafer is fabricated onto product turnout, the overall production cost of reduction.
With reference to shown in Fig. 1, during wafer-level packaging, it usually needs be bonded in wafer 10 with substrate 12 with adhesive 13
Together, then isolation layer 11 is made on the surface of wafer 10 with the conductive structure by crystal column surface with being subsequently formed to keep apart.For
Adhesive is avoided to be failed because of high temperature, it usually needs to use low temperature oxide（Low temperature oxide, LTO）Come
Form isolation layer 11.
However, in being tested to isolation layer 11 and the bonding strength of wafer 10, with reference to shown in Fig. 2, to the side of isolation layer 11
Edge applies pressure soon, just starts crack 10 and 11 occur between the isolation layer 11 and wafer 10.Wherein, A points are pressurization
Starting point, B points are cracking appearance point.With reference to shown in Fig. 3, after certain pressure is applied to the center section of isolation layer 11, at interval
After a period of time, larger crack 13 and 14 equally occurs.Wherein, A ' points are pressurization starting point, and B ' points are cracking appearance point.
The bonding strength of isolation layer 11 and wafer 10 is poor, there is the hidden danger that separation layer 11 is peeled off on wafer 10, the direct shadow of hidden danger
Ring subsequent technique carry out, and the semiconductor devices ultimately formed reliability.
For this reason, it may be necessary to a kind of new wafer-level packaging method, to improve the bonding strength of isolation layer and wafer, so as to prevent
The problem of isolation layer generation cracking or stripping are those skilled in the art's urgent need to resolve.
The content of the invention
The problem of present invention is solved is to provide a kind of wafer-level packaging method, to improve the waterproof ability with isolation layer, prevents
Only isolation layer occurs cracking or peeled off, so as to strengthen the buffer action of isolation layer.
To solve the above problems, the present invention provides a kind of wafer-level packaging method, including：
Semiconductor crystal wafer is provided, the semiconductor crystal wafer includes first surface and second surface, the first surface and the
Two surface locations are relative；
The second surface of the semiconductor crystal wafer is adhered into substrate；
In the first surface formation groove of the semiconductor crystal wafer；
In the first surface of the semiconductor crystal wafer, and the bottom of the groove and side wall formation adhesion auxiliary layer；
Isolation layer is formed on the adhesion auxiliary layer；
Along isolation layer described in the recess etch and adhesion auxiliary layer, isolation layer and the adhesion of the bottom portion of groove are removed
Auxiliary layer, exposes the semiconductor crystal wafer；
Gold is formed on the isolation layer, the side wall of the groove, and the exposed semiconductor crystal wafer of the bottom portion of groove
Belong to interconnection line layer；
Pad is formed on metal interconnecting wires layer, the metal interconnecting wires layer is electrically connected with the pad；
Passivation layer is formed in the metal interconnecting wires with the pad layer by layer；
Opening, at least partly described pad of opening exposure are formed in the passivation layer；
Metal level is formed on the passivation layer and on exposed pad in the opening, and is formed on the metal level
Soldered ball.
Alternatively, the adhesion auxiliary layer is silicon dioxide layer.
Alternatively, the thickness of the adhesion auxiliary layer is
Alternatively, the formation process of the adhesion auxiliary layer is PECVD.
Alternatively, the formation process of the adhesion auxiliary layer includes：The air pressure for adjusting reaction cavity is 2~4torr, temperature
For 170~200 DEG C, SiH is passed through into reaction cavity4And NO2, wherein, the flow of the SiH4 is 60~100sccm, NO2's
Flow is 6000~10000sccm.
Alternatively, the thickness of the isolation layer is
Alternatively, the formation process of the isolation layer is PECVD.
Wafer-level packaging method as claimed in claim 7, alternatively, the formation process of the isolation layer includes：Adjustment
The air pressure of reaction cavity is 3~4torr, and temperature is 170~200 DEG C, and TEOS and O are passed through into reaction cavity2Or TEOS and
O3, the flow of the TEOS is 1000~1500sccm, O2Or O3Flow be 2500~3200sccm.
Alternatively, while being passed through diluent gas into the reaction cavity, the diluent gas is inert gas, and flow is
1900~2300sccm.
Alternatively, the diluent gas is He.
Compared with prior art, technical scheme has advantages below：
In the first surface of semiconductor crystal wafer, and bottom in the groove of first surface and the one layer of adhesion of formation of side wall it is auxiliary
Help after layer, the isolation layer is formed on the adhesion auxiliary layer, afterwards along isolation layer described in the recess etch and viscous
Attached auxiliary layer, removes the isolation layer and adhesion auxiliary layer of the bottom portion of groove, exposes the semiconductor crystal wafer；In the isolation
Metal interconnecting wires layer is formed on layer, the side wall of the groove, and the exposed semiconductor crystal wafer of the bottom portion of groove；Afterwards, exist
The structures such as pad, passivation layer, soldered ball are formed on the metal interconnecting wires layer, wafer-level packaging is completed.Above-mentioned technical proposal is in institute
The knot of the isolation layer and semiconductor crystal wafer can be effectively improved by stating the adhesion auxiliary layer formed between isolation layer and semiconductor crystal wafer
Intensity is closed, so as to improve the stability for the semiconductor devices for completing to be formed after wafer level packaging.
In further alternative, the adhesion auxiliary layer is with SiH4And NO2For presoma, using pecvd process described
Silicon dioxide layer is formed on the side wall of the groove of semiconductor wafer surface and semiconductor crystal wafer figure and bottom, afterwards again with
TEOS is presoma and and O2Or O3Reaction, layer of silicon dioxide is continuously formed with pecvd process in the silicon dioxide layer
Isolation layer.In above-mentioned technical proposal, SiH4First it is deposited in chemisorbed mode on semiconductor crystal wafer, afterwards and NO2Reaction is formed
Silicon dioxide layer, above-mentioned technical proposal can effectively increase silicon dioxide layer and the bond strength of semiconductor crystal wafer, afterwards with
TEOS and O2（Or O3）The continued growth silicon dioxide layer in silicon dioxide layer, can be effectively increased the silicon dioxide layer ultimately formed
Thickness.In above-mentioned technical proposal, adhesion auxiliary layer and the silicon dioxide layer being subsequently formed are integral, described as separation layer
While isolation layer can effectively completely cut off semiconductor crystal wafer with follow-up conductive structure above the semiconductor crystal wafer, effectively enhancing
The bond strength of separation layer and semiconductor crystal wafer.
Brief description of the drawings
During Fig. 1 is existing wafer-level packaging, the schematic diagram of semiconductor package；
During Fig. 2 is the bonding strength test process of the semiconductor package in Fig. 1, isolation layer and semiconductor die rounded edge
Test structure schematic diagram；
During Fig. 3 is the bonding strength test process of the semiconductor package in Fig. 1, in the middle of isolation layer and semiconductor crystal wafer
The test structure schematic diagram in region；
Fig. 4 to Fig. 9 is the structural representation of wafer-level packaging method provided in an embodiment of the present invention；
Figure 10 is the isolation of the semiconductor package using wafer-level packaging method provided in an embodiment of the present invention formation
The test structure schematic diagram of layer and semiconductor die rounded edge；
Figure 11 is the isolation of the semiconductor package using wafer-level packaging method provided in an embodiment of the present invention formation
Layer and the test structure schematic diagram of semiconductor crystal wafer intermediate region.
Embodiment
In existing wafer-level packaging method, it is necessary to first semiconductor wafer surface formation one layer of low temperature oxide layer as every
Exhausted layer, semiconductor crystal wafer to be come with the follow-up conductive structure isolation in semiconductor wafer surface formation.But
Discovery in actual manufacturing process, the isolation layer formed using existing process in the semiconductor wafer surface and semiconductor crystal wafer
Bond strength is poor, often occurs that isolation layer departs from the phenomenon of semiconductor crystal wafer, and it seriously reduces half formed after encapsulation
The stability of conductor device.
Therefore, the invention provides a kind of wafer-level packaging method, it is first before semiconductor wafer surface formation isolation layer
In one layer of adhesion auxiliary layer of upper formation of semiconductor crystal wafer, isolation layer is formed on adhesion auxiliary layer afterwards, so as to improve isolation
The bond strength of layer and semiconductor crystal wafer, prevents isolation layer from being departed from by semiconductor wafer surface.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
With reference to a kind of schematic diagram of Fig. 4 and Fig. 6 wafer-level packaging methods provided for the present embodiment.
There is provided semiconductor crystal wafer 100 with reference to shown in Fig. 4.The semiconductor crystal wafer 100 includes first surface 101 and second
Surface 102.First surface 101 and second surface 102 position is oppositely arranged.
In the present embodiment, the first surface 101 is the active face of semiconductor crystal wafer 100, and second surface 102 is semiconductor
The back side of wafer 100.Substrate 120 is adhered on the second surface 102 of the semiconductor crystal wafer 100.
The semiconductor crystal wafer 100 is Silicon Wafer.Multiple chip units are formed with the semiconductor crystal wafer 100（Figure
In do not show）, e.g., the chip unit can be image sensor chip unit etc..There is Cutting Road between each chip unit,
Each chip unit can form one single chip after encapsulation and cutting.
In the present embodiment, the substrate 120 is chosen as glass substrate.The substrate 120 is by being coated on second table
The adhesive 110 in face 102 is fixedly connected with the semiconductor crystal wafer 100.
In the present embodiment, adhesive 100 uses organic adhesion agent.The organic adhesion agent has that adhesion speed is fast, not shadow
Ring bonded structure, it is readily removable remove, low cost and the features such as high adhesive strength.Specifically, the adhesive is chosen as epoxide-resin glue
Stick.
Fluted 103 are opened up on the first surface 101 of the semiconductor crystal wafer 100, the groove 103 is partly led with described
Device position correspondence in body wafer 100, can subsequently form interconnection line, to turn on the semiconductor die in the groove 103
Device and external devices in circle 100.
The formation process of groove 103 includes：Photoresist layer first is coated on the first surface 101,
The techniques such as exposed development are formed after photoetching agent pattern on photoresist layer, the institute by mask etching of photoetching agent pattern
The first surface 101 of semiconductor crystal wafer 100 is stated to form the groove 103, the photoresist layer is removed afterwards.These steps are equal
For art technology mature technology, it will not be repeated here.
It is worth noting that, in other embodiments of the present invention in addition to the present embodiment, first surface 101 can be semiconductor
The back side of wafer 100, and second surface 102 can be the active face of wafer 100, now, the level packaging methods of wafer 100 are a kind of
Flip-chip（flip chip）Method for packing.These simple changes are within the scope of the present invention.
With reference to shown in Fig. 5, on the first surface 101 of the semiconductor crystal wafer 100, and the groove 103 side wall
And adhesion auxiliary layer 130 is formed on bottom.
The adhesion auxiliary layer 130 is chosen as low temperature oxide layer.In the present embodiment, the adhesion auxiliary layer 130 is chosen as
Silica（SiO2）.The adhesion forming method of auxiliary layer 130 is chosen as PECVD（Plasma Enhanced Chemical
Vapor Deposition, plasma enhanced chemical vapor deposition method）.Specifically include：
The air pressure for adjusting PECVD reaction cavity is 2~4torr, and temperature control is 170~200 DEG C, into reaction cavity
It is passed through SiH4And NO2It is used as reacting gas.Wherein, the SiH4Flow be 60~100sccm, NO2Flow for 6000~
10000sccm。
In the present embodiment, the SiH4It is passed through after reaction cavity, first table of the rapid absorption in the semiconductor crystal wafer 100
On face 101, afterwards and NO2Generation redox reaction, so as to form the SiO of solid-state on the first surface 1012Layer.
In the present embodiment, still optionally further the air pressure of the reaction cavity is 3torr or so, the SiH4Flow be
800sccm or so, NO2Flow for 8000sccm or so.The flow control of above-mentioned reacting gas, can effectively control SiH4And NO2
Reaction rate, so as to form a layer thickness uniform SiO on the first surface 101 of the semiconductor crystal wafer 1002Layer.
It is square on the adhesion auxiliary layer 130 after the adhesion auxiliary layer 130 is formed with reference to shown in reference to Fig. 6
Into one layer of isolation layer 140.The material of the isolation layer 140 is chosen as low temperature oxide.
In the present embodiment, the low temperature oxide layer is chosen as silicon dioxide layer.
In the present embodiment, for bonding the adhesive 100 of the semiconductor crystal wafer 100 and substrate 120 using organic gluing
Agent, the adhesive heat resisting temperature is relatively low.In the present embodiment, the adhesion auxiliary layer 130 and the material of isolation layer 140 are low temperature
Oxide skin(coating), thus when forming isolation layer, can effectively prevent adhesive 300 to be heated too high and lose bonding effect.
In the present embodiment, the formation process of the isolation layer 140 is chosen as PECVD, specifically includes：
The air pressure for adjusting PECVD reaction cavity is 3~4torr（It is still optionally further 3.5torr or so）Temperature control
170~200 DEG C are made as, TEOS is passed through into reaction cavity（Tetraethyl orthosilicate）And O2, or TEOS and O3.To the reaction
Intracavitary is passed through TEOS and O2（Or O3）Afterwards, the TEOS is in O2（Or O3）Reaction of decomposing is acted on, so that in the semiconductor die
One layer of SiO is formed on the first surface 101 of circle 1002Layer.And the temperature in PECVD is less than 200 DEG C, can effectively prevent adhesive
300 are heated too high and lose bonding effect.
In the present embodiment, the flow of the TEOS is 1000~1500sccm（Further it is chosen as 1200sccm or so）Institute
State O2Or O3Flow be 2500~3200sccm（Further it is chosen as 2900sccm or so）.Above-mentioned reactant flow control can
Isolation layer 140 in uniform thickness is formed on the adhesion auxiliary layer 130.
Still optionally further, it is being passed through the TEOS and O2（Or O3）When, indifferent gas can be passed through into the reaction chamber simultaneously
Body, to be used as diluent gas.In the present embodiment, the inert gas is chosen as helium（He）, flow be chosen as 1900sccm~
2300sccm, is further chosen as 2100sccm or so.The inert gas of above-mentioned flow control, can effectively control TEOS reaction
Speed, to form SiO in uniform thickness2Layer simultaneously, improves the security of reaction system.
In the present embodiment, first with SiH4As presoma one is formed on the first surface 101 of the semiconductor crystal wafer 100
Layer SiO2After layer, then it is presoma in established SiO to use TEOS2One layer of SiO of continued growth on layer2Layer, two layers of SiO2Layer is made
It is integral as isolation layer.
In the present embodiment, the thickness of the adhesion auxiliary layer 130 is chosen asThe isolation layer 140
Thickness is chosen asThe adhesion auxiliary layer, can effectively improve the isolation layer 140 and semiconductor being subsequently formed
The bonding strength of wafer 100.In the present embodiment, if the adhesion thickness of auxiliary layer 130 is too small（It is less than）, then can reduce
Its adhesion, if blocked upThe intensity that can equally influence it to connect isolation layer 140 and semiconductor crystal wafer 100.The isolation layer
If excessively thin（It is less than）Good insulating effect can not be played, if blocked up（It is more than）Increase process costs simultaneously,
Increase the structure for the semiconductor devices being subsequently formed.
With reference to shown in Fig. 7, in the first surface 101 of the semiconductor crystal wafer 100, and the side wall of groove 103 and bottom
Formed after the isolation layer 140, the adhesion auxiliary layer 130 and isolation layer of the bottom of groove 103 are etched along the groove 103
140, until exposing the semiconductor crystal wafer 100 of the bottom of groove 103.
With reference to shown in Fig. 8, on the isolation layer 140, and groove 103 side wall, and the bottom of the groove 130 is naked
The surface of the semiconductor crystal wafer 100 of dew forms metal interconnecting wires layer 150, the metal interconnecting wires layer 150 and the semiconductor die
Device electrical connection in circle 100.
In the present embodiment, the material of the metal interconnecting wires layer 150 is chosen as Al.Its formation process can be PVD（Physics gas
Phase sedimentation）.
With reference to shown in Fig. 9, form pad 160 on metal interconnecting wires layer 150, metal interconnecting wires layer 150 with
The pad 160 is electrically connected, and forms passivation layer 170 on metal interconnecting wires layer 150 and the pad 160 afterwards；Etching
The passivation layer 170, forms opening in the passivation layer 170（Do not indicated in figure）, the opening exposes at least partly described
Pad 160, afterwards, metal level 180 is formed on the pad 160 of the passivation layer 170 and exposure in the opening, and described
Soldered ball 190 is formed on metal level 180.
In the present embodiment, the material of the pad 610 can include the one or more in aluminium, copper, silver, gold, nickel, tungsten
Any combination.The material of passivation layer 170 both can be epoxy resin (Epoxy), polyimides（PI）, benzocyclobutene, polyphenyl
The inorganic material such as the organic materials such as oxazole or silicon nitride, silicon oxynitride or silica.Metal level 180 can include
There are the sandwich constructions such as diffusion layer, barrier layer, wetting layer and anti oxidation layer.The material of soldered ball 190 can be tin, Xi Yin, tin-lead, tin
One or more in the metals such as the silver-colored antimony of silver-bearing copper, tin silver-colored zinc, tin zinc, tin bismuth indium, tin indium, Sillim, tin copper, tin zinc indium or tin
Any combination, and activating agent can be included in soldered ball 190, soldered ball 190 can pass through electroplating technology and reflow soldering process shape
Into.
Figure 10 and Figure 11 is to be formed on the semiconductor crystal wafer 100 after isolation layer 140, to the semiconductor crystal wafer 100
In the bonding strength test of isolation layer 140, the attachment structure schematic diagram of the semiconductor crystal wafer 100 and isolation layer 140.
The fine powder 16 in fine powder 15 and Figure 11 in Figure 10 is to apply pressure to semiconductor package
Afterwards, the powder formed after the semiconductor crystal wafer 100 is pulverized.
Wherein, Figure 10 is isolation layer（Entirety including the adhesion auxiliary layer 130 and the formation of isolation layer 140）And semiconductor
The structural representation of the test result of wafer frontside edge.
With reference to shown in Figure 10, C points be applied voltage test starting point, by applied voltage test for a period of time after, even if semiconductor
There is fragmentation situation in wafer 100（Pressure is excessive）, do not occur the shape that significantly ftractures between the isolation layer and semiconductor crystal wafer 100 yet
Condition.The connection state of the isolation layer and semiconductor crystal wafer 100 is good.
Figure 11 is the structural representation of the test result of isolation layer and the intermediate region of semiconductor crystal wafer 100.
With reference to shown in Figure 11, D points be applied voltage test starting point, by applied voltage test for a period of time after, even if semiconductor
There is fragmentation situation in wafer 100（Pressure is excessive）, do not occur the shape that significantly ftractures between the isolation layer and semiconductor crystal wafer 100 yet
Condition.The connection state of the isolation layer and semiconductor crystal wafer 100 is good.
Based on shown in Figure 10 and Figure 11, each position of the isolation layer and semiconductor crystal wafer 100 is respectively provided with good connection
Structure.Analyzing its reason is probably：
If forming SiO on a semiconductor wafer by presoma of TEOS2In the technical scheme of layer, after the TEOS is decomposed,
It is deposited on institute's semiconductor crystal wafer and forms SiO2Layer, it is equivalent to physisorption, and absorption affinity is weaker.In the present embodiment, with
SiH4As presoma, be chemisorbed on the surface of semiconductor crystal wafer, afterwards again with NO2Reaction forms SiO2Layer, it can effectively increase
The SiO formed by force2The bonding strength of layer and semiconductor crystal wafer.However, in practical operation, using SiH4Exist as presoma
The side wall of groove 103 in the semiconductor crystal wafer 100 is only capable of forming thin layer SiO2Layer, it is difficult to form thicker SiO2Layer.
If single with SiH4Desired SiO can not be met in the side wall formation thickness of groove 103 as presoma2Layer.Prepared in semiconductor
During the isolation layer of the follow-up etching bottom of groove 103, using SiH4The relatively thin SiO formed2Layer is easily consumed totally.Cause
And with SiH4For the SiO of presoma formation layer2After layer, then by presoma of TEOS in established SiO2Layer on after
It is continuous to form one layer of SiO2Layer, two layers of SiO2The bonding strength of layer is high, and both shapes are integral as isolation layer, to ensure what is formed
The thickness of isolation layer.In the present embodiment, two layers of SiO2The isolation layer that layer is integrated effectively increases while isolation layer effect is ensured
The bonding strength of isolation layer and semiconductor crystal wafer 100 is added.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, are not departing from this
In the spirit and scope of invention, it can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
The scope of restriction is defined.
Claims (10)
1. a kind of wafer-level packaging method, it is characterised in that including：
Semiconductor crystal wafer is provided, the semiconductor crystal wafer includes first surface and second surface, the first surface and the second table
Face position is relative；
The second surface of the semiconductor crystal wafer is adhered into substrate；
In the first surface formation groove of the semiconductor crystal wafer；
In the first surface of the semiconductor crystal wafer, and the bottom of the groove and side wall formation adhesion auxiliary layer；
Isolation layer is formed on the adhesion auxiliary layer；
Along isolation layer described in the recess etch and adhesion auxiliary layer, the isolation layer and adhesion for removing the bottom portion of groove are aided in
Layer, exposes the semiconductor crystal wafer；
Metal is formed on the isolation layer, the side wall of the groove, and the exposed semiconductor crystal wafer of the bottom portion of groove mutual
Connecting line layer；
Pad is formed on metal interconnecting wires layer, the metal interconnecting wires layer is electrically connected with the pad；
Passivation layer is formed on metal interconnecting wires layer and the pad；
Opening, at least partly described pad of opening exposure are formed in the passivation layer；
Metal level, and the formation weldering on the metal level are formed on the passivation layer and on exposed pad in the opening
Ball.
2. wafer-level packaging method as claimed in claim 1, it is characterised in that the adhesion auxiliary layer is silicon dioxide layer.
3. wafer-level packaging method as claimed in claim 1, it is characterised in that the thickness of the adhesion auxiliary layer is
4. wafer-level packaging method as claimed in claim 1, it is characterised in that the formation process of the adhesion auxiliary layer is
PECVD。
5. wafer-level packaging method as claimed in claim 4, it is characterised in that the formation process bag of the adhesion auxiliary layer
Include：The air pressure for adjusting reaction cavity is 2~4torr, and temperature is 170~200 DEG C, and SiH is passed through into reaction cavity4And NO2, its
In, the SiH4Flow be 60~100sccm, NO2Flow be 6000~10000sccm.
6. wafer-level packaging method as claimed in claim 1, it is characterised in that the thickness of the isolation layer is
7. wafer-level packaging method as claimed in claim 1, it is characterised in that the formation process of the isolation layer is PECVD.
8. wafer-level packaging method as claimed in claim 7, it is characterised in that the formation process of the isolation layer includes：Adjust
The air pressure of whole reaction cavity is 3~4torr, and temperature is 170~200 DEG C, and TEOS and O are passed through into reaction cavity2Or TEOS
And O3, the flow of the TEOS is 1000~1500sccm, O2Or O3Flow be 2500~3200sccm.
9. wafer-level packaging method as claimed in claim 8, it is characterised in that while being passed through dilution into the reaction cavity
Gas, the diluent gas is inert gas, and flow is 1900~2300sccm.
10. wafer-level packaging method as claimed in claim 9, it is characterised in that the diluent gas is He.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310675699.7A CN104716055B (en) | 2013-12-11 | 2013-12-11 | Wafer-level packaging method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310675699.7A CN104716055B (en) | 2013-12-11 | 2013-12-11 | Wafer-level packaging method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104716055A CN104716055A (en) | 2015-06-17 |
| CN104716055B true CN104716055B (en) | 2017-09-29 |
Family
ID=53415258
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310675699.7A Active CN104716055B (en) | 2013-12-11 | 2013-12-11 | Wafer-level packaging method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104716055B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB201522552D0 (en) | 2015-12-21 | 2016-02-03 | Spts Technologies Ltd | Method of improving adhesion |
| CN112285828A (en) * | 2020-09-30 | 2021-01-29 | 中国科学院微电子研究所 | End face coupler and packaging method and application thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6107190A (en) * | 1997-01-30 | 2000-08-22 | Nec Corporation | Method of fabricating semiconductor device |
| CN1319887A (en) * | 2000-01-31 | 2001-10-31 | 摩托罗拉公司 | Structure of semiconductor device adherence layer and technology for forming same |
| CN101075575A (en) * | 2006-05-15 | 2007-11-21 | 中芯国际集成电路制造(上海)有限公司 | Method for forming connecting hole with high depth and width ratio |
| CN101231949A (en) * | 2007-01-24 | 2008-07-30 | 国际商业机器公司 | Method and semiconductor structure improving adhesion strength between two different layers |
| CN101699622A (en) * | 2009-11-18 | 2010-04-28 | 晶方半导体科技（苏州）有限公司 | Packaging structure and packaging method of semiconductor device |
-
2013
- 2013-12-11 CN CN201310675699.7A patent/CN104716055B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6107190A (en) * | 1997-01-30 | 2000-08-22 | Nec Corporation | Method of fabricating semiconductor device |
| CN1319887A (en) * | 2000-01-31 | 2001-10-31 | 摩托罗拉公司 | Structure of semiconductor device adherence layer and technology for forming same |
| CN101075575A (en) * | 2006-05-15 | 2007-11-21 | 中芯国际集成电路制造(上海)有限公司 | Method for forming connecting hole with high depth and width ratio |
| CN101231949A (en) * | 2007-01-24 | 2008-07-30 | 国际商业机器公司 | Method and semiconductor structure improving adhesion strength between two different layers |
| CN101699622A (en) * | 2009-11-18 | 2010-04-28 | 晶方半导体科技（苏州）有限公司 | Packaging structure and packaging method of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104716055A (en) | 2015-06-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2022533048A (en) | Package composition and manufacturing method | |
| CN102270603B (en) | Manufacturing method of silicon through hole interconnect structure | |
| JP6195704B2 (en) | 3DIC method and apparatus | |
| CN100499095C (en) | Semiconductor device and method of manufacturing same | |
| WO2012057200A1 (en) | Process for manufacture of through-type wiring substrate, and through-type wiring substrate | |
| JP5730654B2 (en) | Wiring board and manufacturing method thereof | |
| CN102222647B (en) | Semiconductor die and method of manufacturing semiconductor feature | |
| JP5613620B2 (en) | Wiring board and manufacturing method thereof | |
| TWI587470B (en) | Substrate, method of manufacturing substrate, semiconductor device, and electronic apparatus | |
| CN105655320B (en) | Low-cost chip back silicon through hole interconnection structure and preparation method thereof | |
| US7919406B2 (en) | Structure and method for forming pillar bump structure having sidewall protection | |
| TW200836321A (en) | Method for manufacturing semiconductor device and semiconductor device | |
| CN105023906A (en) | Substrate with electrical connection structure and manufacturing method thereof | |
| TW201128754A (en) | A conductive pillar structure for semiconductor substrate and method of manufacture | |
| TW202008539A (en) | Assembly structure, method of bonding using the same, and circuit board therefor | |
| WO2022103527A1 (en) | Package structures with built-in emi shielding | |
| CN103258791B (en) | Method and the corresponding device of metal interconnection is realized by preparing ultra fine-pitch micro convex point | |
| KR101215644B1 (en) | Semiconductor chip, package and method for manufacturing semiconductor chip | |
| CN104716055B (en) | Wafer-level packaging method | |
| CN105489550B (en) | Inexpensive crystal wafer chip dimension silicon through hole interconnection structure and preparation method thereof | |
| CN104362105A (en) | Packaging process of copper post and bump structure | |
| CN106960829A (en) | A kind of structure for alleviating chip package stress and preparation method thereof | |
| JP5873145B2 (en) | Method for manufacturing through wiring board | |
| CN105742193A (en) | Wafer and Wafer Bonding Process and Structures | |
| CN102290397A (en) | Silicon wafer structure and multiple grain stack structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20180608 Address after: No. 18 Zhangjiang Road, Pudong New Area, Shanghai Co-patentee after: Core integrated circuit (Ningbo) Co., Ltd. Patentee after: Semiconductor Manufacturing International (Shanghai) Corporation Address before: No. 18 Zhangjiang Road, Pudong New Area, Shanghai Patentee before: Semiconductor Manufacturing International (Shanghai) Corporation |
|
| TR01 | Transfer of patent right |