CN102270603B - Manufacturing method of silicon through hole interconnect structure - Google Patents
Manufacturing method of silicon through hole interconnect structure Download PDFInfo
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- CN102270603B CN102270603B CN2011102302661A CN201110230266A CN102270603B CN 102270603 B CN102270603 B CN 102270603B CN 2011102302661 A CN2011102302661 A CN 2011102302661A CN 201110230266 A CN201110230266 A CN 201110230266A CN 102270603 B CN102270603 B CN 102270603B
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Abstract
The invention discloses a manufacturing method of a silicon through hole interconnect structure, belonging to the field of microelectronic packaging. The manufacturing method comprises the following steps of: 1) splicing a glass wafer on the front of a silicon wafer; 2) thinning the back of the silicon wafer to reach a target thickness, and preparing a silicon through hole of the silicon wafer; 3) sequentially depositing an insulating layer and a seed layer on the back of the silicon wafer; 4) making an electroplating mask on the back of the silicon wafer, and filling the silicon through hole by an electroplating conductive material to form a bump; and then making a bonding pad on the bump, and exposing the insulating layer at the periphery of the bump; and 5) splicing the back of the silicon wafer onto a glass wafer, and stripping the glass wafer; removing the insulating layer deposited at the bottom of the silicon through hole by etching on the front of the silicon wafer, making a rewiring layer to be electrically connected with the seed layer deposited in the silicon connecting through hole and the microelectronic circuit, and making the bonding pad for the rewiring layer. By adopting the manufacturing method disclosed by the invention, deposition effect of the seed layer and electroplating filling effect can be conveniently monitored, technical difficulty of a process is reduced, and yield is improved.
Description
Technical field
The invention belongs to the microelectronics Packaging field, specifically, relate to the manufacture method of a kind of interconnecting silicon through holes (TSV).
Technical background
Three-dimensional integration technology based on silicon through hole (Through Silicon Via, TSV) interconnection can provide the electrical signal interconnection of vertical direction, reduces the parasitic parameter of line, improves the operating rate of system, reduces power consumption.In addition, it can also provide highdensity packing forms, reduces area, the volume and weight of microelectronics system, at portable set or to area, volume and weight, has the harsh field required to have wide practical use.
The manufacture craft of interconnecting silicon through holes, comprise the steps such as silicon via etch, the deposit of through-silicon via sidewall insulating barrier, silicon filling through hole and stud bump making.In current disclosed technical scheme, through-silicon via sidewall insulating layer deposition method has plasma enhanced chemical vapor deposition (PECVD), and inductively coupled plasma strengthens chemical vapour deposition (CVD) (ICP-CVD) etc.The silicon method for filling through hole has bottom-up electro-coppering to fill (Bottom-up), electro-coppering guarantor type is filled (conformal), the filling of chemical vapour deposition (CVD) tungsten etc.Electroplate the filling silicon through holes technical process and can produce copper projection (overloading), in disclosed technical scheme, the general method of the Cu dual Damascene technology in similar integrated circuit fabrication process that adopts is removed the copper projection.With the Cu dual Damascene technology of integrated circuit fabrication process, compare, the copper projection that silicon the electroplates in hole copper fill to produce at several microns to tens micron dimensions, this brings larger technological challenge to the copper flatening process, require the copper flatening process that higher removal speed is provided on the one hand, require on the other hand the damage of copper flatening process reduce to the passivation layer under it or substrate silicon layer, and the demand of this two aspect is contradiction each other.In addition, how to technique on-line monitorings such as seed layer deposition technique, electro-coppering fill process to improving rate of finished products, reduce costs significant.
Summary of the invention
For technological challenge, the interconnecting silicon through holes manufacture craft monitoring difficulty that in existing interconnecting silicon through holes manufacture craft, the copper flatening process faces, the object of the present invention is to provide a kind of silicon through hole (Through Silicon Via, TSV) interconnected manufacture method, as shown in Fig. 1 (a), its step comprises:
Step 1, provide the semiconductor wafer, the semiconductor crystal wafer one side has completed microelectronic circuit and has made.Interim bonding Silicon Wafer front is to glass wafer (the Silicon Wafer front refers to the one side that contains the microelectronic circuit chip);
Step 2, attenuate, polished silicon wafer rear are to certain thickness.Make silicon via etch mask, make the silicon through hole;
Step 3, in Silicon Wafer backside deposition insulating barrier, Seed Layer; Can pass through the glass wafer of step 1, the seed layer deposition effect is monitored;
Step 4, making electro-coppering mask; The electro-coppering filling silicon through holes, remove photoresist, Seed Layer.Can pass through the glass wafer of step 1, the electro-coppering filling effect is monitored;
The glass-silicon wafer, to another secondary wafer, is peeled off in step 5, the interim bonding Silicon Wafer back side.At the positive re-wiring layer of making of the Silicon Wafer exposed, be electrically connected to interconnecting silicon through holes and microelectronic circuit chip, make pad.
Step 6, peel off Silicon Wafer, cut apart microelectronic chip.
Preferably, step 4, electrotinning or electrosilvering tin or electronickelling tin after electro-coppering, make copper tin or copper silver tin dimpling point.
Preferably, step 6 comprise by 2 or above microelectronic circuit Chip Vertical stacking, a microelectronic circuit chip copper dimpling point and another microelectronic circuit chip bonding pad bonding.
Preferably, between chip-stacked more than 2 or 2, exist macromolecule organic to fill.
Preferably, adopt the interim bonding Silicon Wafer of a kind of high-molecular organic material.
Preferably, method (CMP) attenuate, the polished silicon wafer that adopt mechanical reduction and chemico-mechanical polishing to combine.
The invention discloses a kind of silicon through hole (Through Silicon Via, TSV) interconnected manufacture method, as shown in Fig. 1 (b), its step comprises:
Step 1-1, provide the semiconductor wafer, one side has completed microelectronic circuit and has made.In the positive blind hole of making of semiconductor crystal wafer.The semiconductor crystal wafer front refers to the one side that contains the microelectronic circuit chip.
Step 1-2, depositing metal layers, to the semiconductor crystal wafer front, comprise the blind hole sidewall sections.Graphical metal level, make being electrically connected between microelectronic chip pad and blind hole sidewall.
Step 1, interim bonding semiconductor crystal wafer front are to glass wafer (the semiconductor crystal wafer front refers to the one side that contains microelectronic chip).
Step 2, the attenuate Silicon Wafer back side are to certain thickness.Making the positive blind hole of silicon through hole and semiconductor crystal wafer realizes connecting.
Step 3, at Silicon Wafer backside deposition copper seed layer; Can pass through the glass wafer of step 1, the seed layer deposition effect is monitored.
Step 4, making electro-coppering mask; The electro-coppering filling silicon through holes, remove photoresist, Seed Layer; Can pass through the glass wafer of step 1, the electro-coppering filling effect is monitored.
Step 5, separating semiconductor wafer and glass wafer, cut apart microelectronic chip.
Preferably, step 1-2 is included in the positive deposit passivation layer of semiconductor crystal wafer, graphical passivation layer technique.
Preferably, the positive blind hole of step 1-2 semiconductor crystal wafer can be at the interconnection passivation layer of semiconductor crystal wafer microelectronic circuit chip; Or the interconnection passivation layer of break-through microelectronic circuit chip is to the silicon substrate certain depth; Or interconnection passivation layer and the silicon substrate of break-through microelectronic circuit chip.
Preferably, the technique that step 3 comprises deposited barrier layer.
Preferably, step 3 comprises through-silicon via sidewall making insulating barrier technique.
Preferably, step 4, electrotinning after electro-coppering, or electrosilvering tin, or electronickelling tin, make copper tin or copper silver tin or cuprum-nickel-stannum dimpling point.
Preferably, step 5 comprise by 2 or above microelectronic circuit Chip Vertical stacking, a microelectronic circuit chip copper dimpling point and another microelectronic circuit chip bonding pad bonding.
Preferably, interim bonding Silicon Wafer adopts a kind of high-molecular organic material.
Preferably, the attenuate Silicon Wafer adopts the method (CMP) that mechanical reduction and chemico-mechanical polishing combine.
Compared with prior art, technique effect of the present invention is:
The technical scheme of this disclosure of the invention is exempted the copper flatening process, conveniently carries out the seed layer deposition effect simultaneously, electroplates the filling effect monitoring, effectively reduces the technical difficulty of technique, is conducive to improve rate of finished products, reduces process costs.
The accompanying drawing explanation
Fig. 1 (a), Fig. 1 (b) are the manufacture method flow chart of interconnecting silicon through holes of the present invention;
The manufacture method flow chart that Fig. 2 (a)～(h) is embodiment mono-;
The manufacture method flow chart that Fig. 3 (a)～(h) is embodiment bis-.
Embodiment
Embodiment mono-
The invention discloses a kind of manufacture method of silicon through hole interconnect structure, as shown in Figure 2, specific as follows:
Step 1, provide a Silicon Wafer 100, positive 110 have completed microelectronic circuit makes, and there is pad 111 in the microelectronic circuit chip.Adopt the interim bonding Silicon Wafer of high-molecular organic material 112 front to glass wafer 200 (the Silicon Wafer front refers to the one side that contains microelectronic chip).High-molecular organic material is spin-coated on glass wafer or Silicon Wafer front, 50 degrees centigrade to 150 degrees centigrade precuring, and at 100 degrees centigrade to 250 degrees centigrade, bonding under certain pressure.
Step 2, at Silicon Wafer thinning back side Silicon Wafer to approximately 50 microns to 250 microns of target thicknesses.The method that attenuate can adopt mechanical reduction to combine with chemico-mechanical polishing, also can adopt chemical corrosion (TMAH or KOH) or lithographic method to realize.Photoetching, the spin coating photoresist, adopt the alignment mark of the microelectronic circuit that sees through glass wafer observation to be aimed at, expose, develop, make silicon via etch mask, deep reaction ion etching (DRIE) Silicon Wafer is to interconnection layer (dielectric layer), the surface passivation layer of Silicon Wafer microelectronic circuit chip, and interconnection layer, the surface passivation layer of reactive ion etching Silicon Wafer microelectronic circuit chip, finally remove photoresist, form silicon through hole 101, as Fig. 2-(a).
Step 3, at Silicon Wafer back side plasma enhanced chemical vapor deposition silicon dioxide (SiO
2), the insulating barrier 102 of formation wafer rear, through-silicon via sidewall and bottom, as shown in Fig. 2 (b).Then sputtered titanium tungsten metal level (TiW), copper (Cu) form barrier layer, plating seed layer 103, as shown in Fig. 2-(c).Insulating barrier also can adopt other semiconductor technology customary insulation materials, and deposition process can adopt physical vapour deposition (PVD) or other semiconductive thin film deposition techniques.Barrier layer, Seed Layer also can adopt other materials, and deposition process can adopt the semiconductive thin film deposition technique as ALD etc.
Step 4, at Silicon Wafer back side spin coating photoresist, or hot pressing dry film, photolithographic exposure, development, make electro-coppering mask 120, as shown in Fig. 2-(d).Electro-coppering guarantor type filling silicon through holes, form the copper metal column 104 with dimpling point.On 104, electrotinning forms dimpling means of spot welds layer 105.Remove photoresist 120, dimpling point Seed Layer, barrier layer 103 on every side, as shown in Fig. 2-(e).The electro-coppering mask can also spray liquid photoresist, or the photo-conductive film realization is pasted in hot pressing.After the electro-coppering filling silicon through holes, can also the electroplating other metals welding material, as silver-colored ashbury metal etc., prepare weld layer 105.
Glass wafer 200, to another secondary wafer 300, is peeled off in step 5, the interim bonding Silicon Wafer back side.Reactive ion etching silicon via bottoms insulating barrier 102, expose 103 layers of interconnecting silicon through holes (TSV); Can also adopt other wet etching methods to remove copper silicon hole bottom insulation layer 102, as Fig. 2-(f).Make re-wiring layer, interconnecting silicon through holes and microelectronic chip are realized electrical interconnection, make the pad of this re-wiring layer.The re-wiring layer metal level can adopt the metals such as aluminium, copper, and insulating barrier can adopt the insulating material such as silicon dioxide, silicon nitride, BCB, PI.
Step 6, peel off Silicon Wafer 300, cut apart Silicon Wafer, separate the microelectronic circuit chip, as shown in Fig. 2-(g).The cutting apart of Silicon Wafer can adopt machinery to cut apart or laser is cut apart, also can adopt other cutting techniques commonly used of semicon industry.
Step 7, stacking microelectronic chip successively, dimpling point 105 is positive by the pad thermocompression bonding of re-wiring layer with microelectronic chip.Lower filling organic substance is between stacking microelectronic chip, as Fig. 2-(h).
Embodiment bis-
The invention discloses a kind of manufacture method of silicon through hole interconnect structure, as shown in Figure 3, specific as follows:
Step 1, provide a Silicon Wafer 100, positive 110 have completed the microelectronic circuit chip manufacturing, and there is pad 111 in the microelectronic circuit chip.Make blind hole in wafer frontside.Evaporated metal layer copper or aluminium, to the semiconductor crystal wafer front, comprise the blind hole sidewall sections.Utilize evaporation technique step guarantor type to cover poor technical characterictic, the blind hole sidewall is deposition section metal, and bottom, bottom sidewall cover without metal.Graphical copper metal layer, make being electrically connected to 114 between microelectronic chip pad 111 and blind hole sidewall, as shown in Fig. 3-(a).The method realization that graphic method can adopt wet etching or peel off.The positive blind hole of semiconductor crystal wafer can be at the interconnection passivation layer of semiconductor crystal wafer microelectronic circuit chip; Or the interconnection passivation layer of break-through microelectronic circuit chip is to the silicon substrate certain depth; Or interconnection passivation layer and the silicon substrate of break-through microelectronic circuit chip.The blind hole manufacture method can adopt silicon substrate under the interconnection layer of surface passivation layer, interconnection layer and deep reaction ion etching Silicon Wafer microelectronic circuit chip of reactive ion etching silicon wafer surface microelectronic circuit chip in conjunction with carrying out; Also can adopt the additive method realizations such as laser drilling.
Step 2, at Silicon Wafer front depositing insulating layer silica 1 20, etching silicon dioxide is made window, exposes around blind hole and the metal level of sidewall, forms pad.Then adopt the interim bonding Silicon Wafer of high-molecular organic material 112 front to glass wafer (the Silicon Wafer front refers to the one side that contains microelectronic chip).High-molecular organic material is spin-coated on glass wafer or Silicon Wafer front, and 50 degrees centigrade to 150 degrees centigrade precuring, at 100 degrees centigrade to 250 degrees centigrade, bonding under certain pressure, as shown in Fig. 3-(b).
Step 3, at Silicon Wafer thinning back side Silicon Wafer to approximately 50 microns to 250 microns of target thicknesses.The method that attenuate can adopt mechanical reduction to combine with chemico-mechanical polishing, also can adopt chemical corrosion (TMAH or KOH) or lithographic method to realize.At Silicon Wafer back side spin coating photoresist, adopt the alignment mark that sees through glass wafer observation to be aimed at, expose, develop, make silicon via etch mask, the interconnection layer of deep reaction ion etching (DRIE) Silicon Wafer, reactive ion etching Silicon Wafer front microelectronic circuit chip, until connect with the positive blind hole of Silicon Wafer, form silicon through hole 101, remove photoresist, as Fig. 3-(c).
Step 4, at Silicon Wafer back side plasma enhanced chemical vapor deposition silicon dioxide (SiO
2).Then make the photoresist mask, reactive ion etching silicon via bottoms (i.e. that end in close Silicon Wafer front), bottom sidewall oxide (the sidewall sections of 114 layers is arranged), remove photoresist, form wafer rear, through-silicon via sidewall insulating barrier 102, as shown in Fig. 3-(d).Then sputtered titanium tungsten metal level (TiW), copper (Cu) form barrier layer, plating seed layer 103.Insulating barrier also can adopt other semiconductor technology customary insulation materials, and deposition process can adopt physical vapour deposition (PVD).Barrier layer, Seed Layer also can adopt other materials, and deposition process can adopt the semiconductive thin film deposition technique as ALD etc.
Step 5, in the photoetching of the Silicon Wafer back side, make electro-coppering mask 120, as shown in Fig. 3-(e).Electro-coppering guarantor type filling silicon through holes, form the copper metal column 104 with dimpling point.Electrotinning forms dimpling means of spot welds layer 105, as shown in Fig. 3-(f).Remove photoresist 120, dimpling point Seed Layer, barrier layer 103 on every side, as shown in Fig. 3-(g).The electro-coppering mask can spin coating or the spraying liquid photoresist, can also paste photo-conductive film and realize.After the electro-coppering filling silicon through holes, can also the electroplating other metals welding material, as silver-colored ashbury metal etc.
Step 6, peel off Silicon Wafer, cut apart Silicon Wafer, separate the microelectronic circuit chip, as shown in Fig. 3-(g).The cutting apart of Silicon Wafer can adopt machinery to cut apart or laser is cut apart, also can adopt other cutting techniques commonly used of semicon industry.
Step 7, stacking microelectronic chip successively, the pad bonding of dimpling point 105 and microelectronic circuit chip front side.Lower filling organic substance 400 is between stacking microelectronic chip, as shown in Fig. 3-(h).
Claims (9)
1. the manufacture method of a silicon through hole interconnect structure, the steps include:
1) at the positive bonding glass wafer of Silicon Wafer; Described Silicon Wafer comprise be prepared with the positive of microelectronic circuit and with the back side of this vis-a-vis;
2) by described Silicon Wafer thinning back side to target thickness, and prepare the silicon through hole of described Silicon Wafer;
3) at described Silicon Wafer back side depositing insulating layer, Seed Layer successively, wherein by described glass wafer, the deposition process of described Seed Layer is monitored;
4) make plating mask at the described Silicon Wafer back side, plated conductive material filling silicon through holes, form salient point at described Silicon Wafer back side silicon through hole correspondence position; Then make pad on salient point, and expose the insulating barrier around salient point; Wherein by described glass wafer, described plated conductive material filling silicon through holes process is monitored;
5) the described Silicon Wafer back side is bonded on a wafer, peel off described glass wafer; In described Silicon Wafer front, etch away the insulating barrier that the silicon via bottoms deposits, make a re-wiring layer and be electrically connected to Seed Layer and the described microelectronic circuit deposited in the silicon through hole, and make the pad of described re-wiring layer.
2. the method for claim 1, the method that it is characterized in that preparing the silicon through hole of described Silicon Wafer is: in the back side photoetching of described Silicon Wafer, the spin coating photoresist, alignment mark by described glass wafer observation microelectronic circuit is aimed at, is exposed, is developed, make silicon via etch mask, prepare the silicon through hole of described Silicon Wafer.
3. the method for claim 1, is characterized in that deposition one barrier layer between described insulating barrier and Seed Layer.
4. the method for claim 1, is characterized in that described Silicon Wafer is divided into to some microelectronic chips, by the pad thermocompression bonding of the pad on the microelectronic chip bumps and re-wiring layer, the microelectronic chip after successively stacking cutting apart.
5. the manufacture method of a silicon through hole interconnect structure, the steps include:
1) in the positive blind hole of making of Silicon Wafer, described Silicon Wafer comprise be prepared with the positive of microelectronic circuit and with the back side of this vis-a-vis; Then and described blind hole sidewall positive at described Silicon Wafer prepares a metal level, is electrically connected to described blind hole sidewall and microelectronic circuit;
2) at described Silicon Wafer front depositing insulating layer, the described insulating barrier of etching, the metal level of exposure blind hole around openings and sidewall, form pad; Then at the positive bonding glass wafer of described Silicon Wafer;
3) by described Silicon Wafer thinning back side to target thickness, carry out etching until connect with blind hole at described Silicon Wafer back side blind hole correspondence position, prepare the silicon through hole of described Silicon Wafer;
4), at described Silicon Wafer backside deposition insulating barrier, remove and be deposited on the insulating barrier on silicon via bottoms and bottom sidewall metal level; Then at described Silicon Wafer back side plating seed layer; Wherein, by described glass wafer, the deposition process of described Seed Layer is monitored;
5) make plating mask at the described Silicon Wafer back side, plated conductive material filling silicon through holes, form salient point at described Silicon Wafer back side silicon through hole correspondence position; Then make pad on salient point, and expose the insulating barrier around salient point; Wherein, by described glass wafer, the process of described plated conductive material filling silicon through holes is monitored;
6) peel off described glass wafer.
6. method as claimed in claim 5, is characterized in that the bottom of described blind hole is positioned at the interconnection passivation layer of described Silicon Wafer microelectronic circuit chip; Or the interconnection passivation layer of break-through microelectronic circuit chip is to the silicon substrate set depth.
7. method as described as claim 5 or 6, is characterized in that the method for evaporating that adopts step guarantor type to cover prepares described metal level.
8. method as claimed in claim 5, is characterized in that deposition one barrier layer between described insulating barrier and Seed Layer.
9. method as claimed in claim 5, is characterized in that described Silicon Wafer is divided into to some microelectronic chips, by pad and the step 2 on the microelectronic chip bumps) formed pad thermocompression bonding, the microelectronic chip after successively stacking cutting apart.
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| CN101870450A (en) * | 2009-04-22 | 2010-10-27 | 昆山西钛微电子科技有限公司 | Manufacturing process of chip through silicon via (TSV) packaging technology of micro electro mechanical system (MEMS) |
| CN102148192A (en) * | 2010-12-30 | 2011-08-10 | 上海交通大学 | Method for growing blocking layer and seed layer on surface of silicon through hole |
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