CN103295915B - The manufacture method of TSV keyset and TSV keyset - Google Patents
The manufacture method of TSV keyset and TSV keyset Download PDFInfo
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- CN103295915B CN103295915B CN201210055246.XA CN201210055246A CN103295915B CN 103295915 B CN103295915 B CN 103295915B CN 201210055246 A CN201210055246 A CN 201210055246A CN 103295915 B CN103295915 B CN 103295915B
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- salient point
- manufacture method
- sacrifice layer
- substrate
- tsv
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
The invention provides a kind of manufacture method and TSV keyset of TSV keyset, the method comprises the following steps: obtain substrate; Sacrifice layer is made on the surface of described substrate; Photoetching and lithographic technique is utilized to make the through hole running through described substrate and described sacrifice layer over the substrate; Make conductive pole and salient point at described lead to the hole site, described salient point is positioned at the top of described conductive pole, and the top of described salient point exceeds the upper surface of described sacrifice layer; The material being positioned at described sacrifice layer upper surface is removed; The described sacrifice layer being positioned at described substrate top surface is removed, thus obtains salient point at described lead to the hole site.This manufacture method not only simplify technological process, thus reduces production cost, improves production efficiency; And the reliability of TSV keyset can be improved.
Description
Technical field
The invention belongs to microelectronics technology, relate to a kind of manufacture method and TSV keyset of TSV keyset.
Background technology
Along with the continuous progress of microelectric technique, only rely on integrated more device on one chip and cannot meet actual demand to the performance improving chip.Therefore, stack chip package technology becomes the main flow of technical development gradually.Stack chip package technology is under the prerequisite not changing package body sizes, the encapsulation technology of the stacked multiple chip of the vertical direction in same packaging body.Wherein, through-silicon-via (ThroughSivia, TSV) keyset is the connecting plate realizing upper and lower chip interconnects, and TSV keyset mainly comprises TSV through hole, built-up circuit and salient point three parts, it not only can reduce the length of interconnection line, and can reduce the power consumption of circuit.
Fig. 1 is the schematic diagram utilizing TSV keyset to connect substrate and chip.Refer to Fig. 1, substrate 1 with treat that integrated chip 3 is connected by TSV keyset 2.TSV keyset 2 is connected with the conducting wire on substrate 1 and chip 3 by salient point 21 that is disposed thereon, lower surface, and the salient point 21 being positioned at the upper and lower surface of TSV keyset 2 connects by the conductive pole 22 running through its thickness.
At present, TSV through hole and Solder bumping are completed by following method: namely, first on TSV keyset 2, make through hole, then use filled with conductive material through hole, thus in TSV keyset 2, form the conductive pole running through its thickness, finally make salient point 21 on the surface of TSV keyset 2.Fig. 2 a-Fig. 2 h is the schematic diagram of current stud bump making process.Refer to Fig. 2 a-Fig. 2 h, the concrete manufacturing process of salient point is as follows:
Photoetching technique is utilized to make through hole 51 on undressed silicon chip 5, as shown in Figure 2 b; Then by PCD sputtering technology at the sidewall of through hole 51 and the surface deposition barrier layer 52 of silicon chip 5 and inculating crystal layer 53, as shown in Figure 2 c; Utilize electroplating technology plated metal copper 54 in through hole 51, as shown in Figure 2 d; Cmp (CMP) is utilized to be removed by the metallic copper 54 exceeding inculating crystal layer 53, as shown in Figure 2 e; At the surface-coated photoresist 55 of silicon chip 5, and exposure, developing process is utilized to form the figure of making salient point on the surface of silicon chip 5, as shown in figure 2f; In bump location electro-coppering, then polish, as shown in Figure 2 g; Again utilize photoetching technique to be removed by photoresist 55, thus form salient point 21 on the surface of silicon chip 5, as shown in fig. 2h.
As from the foregoing, make the process need Twi-lithography technique of salient point at present, make the cost of TSV keyset higher.And photoresist is organic substance, and it has harmful effect to electroplating technology, easily reduce the conductivity of salient point, thus reduce the reliability of TSV keyset electrical connection.
Summary of the invention
For at least one of solving the problem, the invention provides a kind of manufacture method and TSV keyset of TSV keyset, not only cost of manufacture is low for it, and can improve the reliability of TSV keyset.
The technical scheme adopted solved the problems of the technologies described above is to provide a kind of manufacture method of TSV keyset, comprises the following steps:
Obtain substrate;
Sacrifice layer is made on the surface of described substrate;
Photoetching and lithographic technique is utilized to make the through hole running through described substrate and described sacrifice layer over the substrate;
Make conductive pole and salient point at described lead to the hole site, described salient point is positioned at the top of described conductive pole, and the top of described salient point exceeds the upper surface of described sacrifice layer;
The material being positioned at described sacrifice layer upper surface is removed;
The described sacrifice layer being positioned at described substrate top surface is removed, thus obtains salient point at described lead to the hole site.
Wherein, described substrate is silicon chip.
Wherein, described sacrifice layer is Titanium or SiN or SiO
2.
Wherein, the manufacturing process of described conductive pole and described salient point is:
The hole wall of described through hole makes barrier layer;
Inculating crystal layer is made on the surface on described barrier layer;
Fill described through hole with the metal material of conduction, thus form conductive pole;
Described salient point is made on the top of described conductive pole.
Wherein, described barrier layer and described inculating crystal layer are made by physical gas-phase deposition.
Wherein, make described conductive pole by electroplating technology, described conductive pole adopts metallic copper to make.
Wherein, make described salient point by electroplating technology, described salient point adopts metallic copper or leaded electric conducting material to make.
Wherein, the mode of cmp is utilized to remove the material being positioned at described sacrificial layer surface.
Wherein, the mode of chemical corrosion is utilized to be removed by described sacrifice layer.
Wherein, after the described sacrifice layer of removal, make the glomerate salient point of described salient point shape by heating reflux type.
The present invention also provides a kind of TSV keyset, and it is made by described manufacture method provided by the invention.
The present invention has following beneficial effect:
The manufacture method of TSV keyset provided by the invention is before making through hole and salient point, first one deck sacrifice layer is made on the surface of substrate, only can carry out a photoetching process when making through hole by sacrifice layer can carry out follow-up filling vias and make salient point step, this not only simplifies technological process, thus reduce production cost, improve production efficiency; And owing to no longer carrying out photoetching process at filling vias with when making salient point, the photoresist avoided on the impact of the electric conductivity of salient point and conductive pole, thus can improve the reliability of TSV keyset.
Similarly, TSV keyset provided by the invention is due to before making through hole and salient point, first one deck sacrifice layer is made on the surface of substrate, no longer photoetching process can be carried out at filling vias with when making salient point by sacrifice layer, thus avoidable photoresist is on the impact of the electric conductivity of salient point and conductive pole, the reliability of the TSV keyset therefore obtained is high.
Accompanying drawing explanation
Fig. 1 is the schematic diagram utilizing TSV keyset to connect substrate and chip;
Fig. 2 a-Fig. 2 h is the schematic diagram of the manufacturing process of current TSV keyset;
Fig. 3 a-Fig. 3 h is the schematic diagram of the manufacturing process of embodiment of the present invention TSV keyset;
Fig. 4 is the fabrication processing figure of embodiment of the present invention TSV keyset.
Embodiment
For making those skilled in the art understand technical scheme of the present invention better, below in conjunction with accompanying drawing, the manufacture method of TSV keyset provided by the invention and TSV keyset are described in detail.
The schematic diagram of the TSV keyset manufacturing process that Fig. 3 a-Fig. 3 h provides for the embodiment of the present invention.Fig. 4 is the fabrication processing figure of embodiment of the present invention TSV keyset.See also Fig. 3 a-Fig. 3 h and Fig. 4, the manufacture method of the TSV keyset that the present embodiment provides comprises the following steps:
Step s10, obtains substrate.
The substrate 5 of the present embodiment is silicon chip, as shown in Figure 3 a.Be understood that, substrate 5 also can adopt other suitable material.
Step s20, makes sacrifice layer on the surface of substrate.
The present embodiment adopts PVD (physical vapour deposition (PVD)) method to make sacrifice layer 50, and sacrifice layer 50 is SiN, as Fig. 3 b.
Be appreciated that sacrifice layer 50 also can be such as SiO
2or the easy removed material such as titanium (Ti) makes, and sacrifice layer 50 also can adopt other methods such as such as CVD (chemical vapour deposition (CVD)) to make.
Step s30, utilizes photoetching and lithographic technique to make the through hole running through described substrate and described sacrifice layer over the substrate.
Salient point figure is formed on the surface of sacrifice layer 50 by mask, exposure, developing process; Then make through hole 51 by plasma etch process, and through hole 51 runs through substrate 5 and sacrifice layer 50; Again mask is removed, as shown in Figure 3 c.
Obviously, the present embodiment also can form salient point figure by other means on the surface of sacrifice layer 50, and, also can make through hole 51 by other existing methods such as chemical etchings.In other words, the existing method that can make through hole 51 on sacrifice layer 50 and substrate 5 may be used to make the through hole needed for the present embodiment.
Step s40, make conductive pole and salient point at described lead to the hole site, salient point is positioned at the top of described conductive pole, and the top of described salient point exceeds the upper surface of described sacrifice layer.
Step s40 specifically comprises following steps:
Step s41, the hole wall of through hole makes barrier layer.
In step s41, adopt physical gas-phase deposition to make barrier layer 52, and barrier layer 52 adopt tantalum nitride or tantalum material to make.
Step s42, makes inculating crystal layer 53 on the surface on barrier layer 52.
In step s42, adopt physical gas-phase deposition to make inculating crystal layer 53, and inculating crystal layer 53 adopt metallic copper to make.As shown in Figure 3 d, for making the schematic diagram after barrier layer and inculating crystal layer.
Step s43, fills described through hole with the metal material of conduction, thus forms conductive pole.
In step s43, adopt copper plating process to fill metallic copper in through hole 51, thus obtain the conductive pole 54 of electrical connection substrate 5 upper and lower surface.Certainly, the present embodiment also can adopt other method of the prior art to carry out filling vias 51, thus obtains conductive pole 54, as shown in Figure 3 e.
Step s44, makes salient point on the top of described conductive pole.
In step s44, adopt electroplating technology to make salient point 21, and salient point 21 is adopt leaded material or metallic copper to make, as illustrated in figure 3f.It should be noted that, when conductive pole 54 and salient point 21 adopt identical material, step s43 and step s44 can be merged, namely conductive pole 54 and salient point 21 are directly made by an electroplating technology.
Also it should be noted that, the making of salient point 21 take sacrifice layer as mask, namely, after conductive pole 54 completes, no longer need the figure being made salient point by photoetching process, this not only simplifies the manufacture craft of TSV keyset, and avoid the impact of photoresist on salient point conductivity.
Step s50, removes the material being positioned at sacrifice layer upper surface.
In step s50, by cmp mode will be positioned at sacrifice layer 50 surface material remove, as by barrier layer 52, inculating crystal layer 53 and exceed sacrifice layer 50 surface convex point material remove.Obviously, the present embodiment also can adopt alternate manner to be removed by the material being positioned at sacrifice layer 50 surface.
Step s60, removes the sacrifice layer being positioned at substrate top surface, thus obtains salient point at lead to the hole site.
In step s60, by chemical corrosion method conventional in prior art, SiN is removed, thus obtain salient point 21 in through hole 51 position.So far, the manufacturing process of TSV keyset is terminated.
It should be noted that, the present embodiment can also be processed the profile of salient point 21 as required after step s60, as the profile of salient point 21 changed into spherical by heating reflux type, i.e. and the glomerate salient point of shape.
The manufacture method of the TSV keyset that the present embodiment provides is before making through hole and salient point, first one deck sacrifice layer is made on the surface of substrate, only can carry out a photoetching process when making through hole by sacrifice layer can carry out follow-up filling vias and make salient point step, this not only simplifies technological process, reduce production cost, improve production efficiency; And owing to no longer carrying out photoetching process at filling vias with when making salient point, the photoresist avoided on the impact of the electric conductivity of salient point and conductive pole, thus can improve the reliability of TSV keyset.
The present embodiment also provides a kind of TSV keyset, comprises substrate, runs through the conductive pole of substrate thickness and is arranged on the salient point on conductive pole top, and the manufacture method of the TSV keyset that this conductive pole and salient point are provided by the present embodiment obtains.
Described TSV keyset, comprising:
Substrate; Cover the sacrifice layer of substrate surface;
Run through the through hole of described substrate and described sacrifice layer;
At barrier layer and the inculating crystal layer on the surface of the inwall of described through hole and sacrifice layer successively attached lid;
The conductive pole that metallic copper forms electrical connection substrate upper and lower surface is filled in described through hole;
Make the top of salient point higher than the convex point material of the upper surface of described sacrifice layer;
After removing the material and sacrifice layer being positioned at sacrificial layer surface, the salient point obtained at lead to the hole site place.
The TSV keyset that the present embodiment provides is due to before making through hole and salient point, first one deck sacrifice layer is made on the surface of substrate, and utilize sacrifice layer as the figure making salient point, thus avoid making salient point before make with photoresist, and then avoidable photoresist is on the impact of the electric conductivity of salient point and conductive pole, obtains high performance TSV keyset.
Be understandable that, the illustrative embodiments that above execution mode is only used to principle of the present invention is described and adopts, but the present invention is not limited thereto.For those skilled in the art, without departing from the spirit and substance in the present invention, can make various modification and improvement, these modification and improvement are also considered as protection scope of the present invention.
Claims (11)
1. a manufacture method for TSV keyset, is characterized in that, comprises the following steps:
Obtain substrate;
Sacrifice layer is made on the surface of described substrate;
Photoetching and lithographic technique is utilized to make the through hole running through described substrate and described sacrifice layer over the substrate;
Make conductive pole and salient point at described lead to the hole site, described salient point is positioned at the top of described conductive pole, and the top of described salient point exceeds the upper surface of described sacrifice layer;
The material being positioned at described sacrifice layer upper surface is removed;
The described sacrifice layer being positioned at described substrate top surface is removed, thus obtains salient point at described lead to the hole site.
2. the manufacture method of TSV keyset according to claim 1, is characterized in that, described substrate is silicon chip.
3. the manufacture method of TSV keyset according to claim 1, is characterized in that, described sacrifice layer is Titanium or SiN or SiO
2.
4. the manufacture method of TSV keyset according to claim 1, is characterized in that, the manufacturing process of described conductive pole and described salient point is:
The hole wall of described through hole makes barrier layer;
Inculating crystal layer is made on the surface on described barrier layer;
Fill described through hole with the metal material of conduction, thus form conductive pole;
Described salient point is made on the top of described conductive pole.
5. the manufacture method of TSV keyset according to claim 4, is characterized in that, described barrier layer and described inculating crystal layer are made by physical gas-phase deposition.
6. the manufacture method of TSV keyset according to claim 4, is characterized in that, makes described conductive pole by electroplating technology, and described conductive pole adopts metallic copper to make.
7. the manufacture method of TSV keyset according to claim 4, is characterized in that, makes described salient point by electroplating technology, and described salient point adopts metallic copper or leaded electric conducting material to make.
8. the manufacture method of TSV keyset according to claim 1, is characterized in that, utilizes the mode of cmp to remove the material being positioned at described sacrificial layer surface.
9. the manufacture method of TSV keyset according to claim 1, is characterized in that, utilizes the mode of chemical corrosion to be removed by described sacrifice layer.
10. the manufacture method of TSV keyset according to claim 1, is characterized in that, after the described sacrifice layer of removal, makes the glomerate salient point of described salient point shape by heating reflux type.
11. 1 kinds of TSV keysets, is characterized in that, are made by the manufacture method described in claim 1-10 any one.
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| CN201210055246.XA CN103295915B (en) | 2012-03-05 | 2012-03-05 | The manufacture method of TSV keyset and TSV keyset |
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| CN103295915B true CN103295915B (en) | 2016-02-10 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102103979A (en) * | 2009-12-16 | 2011-06-22 | 中国科学院微电子研究所 | Method for manufacturing three-dimensional silicon-based passive circuit consisting of through silicon vias |
| CN102124551A (en) * | 2008-08-18 | 2011-07-13 | 诺发系统有限公司 | Process for through silicon via filling |
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| CN104011848A (en) * | 2010-07-30 | 2014-08-27 | 昆山智拓达电子科技有限公司 | Tsv interconnect structure and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102124551A (en) * | 2008-08-18 | 2011-07-13 | 诺发系统有限公司 | Process for through silicon via filling |
| CN102103979A (en) * | 2009-12-16 | 2011-06-22 | 中国科学院微电子研究所 | Method for manufacturing three-dimensional silicon-based passive circuit consisting of through silicon vias |
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Address after: 100176 No. 8 Wenchang Avenue, Beijing economic and Technological Development Zone Patentee after: Beijing North China microelectronics equipment Co Ltd Address before: 100176 Beijing economic and Technological Development Zone, Wenchang Road, No. 8, No. Patentee before: Beifang Microelectronic Base Equipment Proces Research Center Co., Ltd., Beijing |