CN105070698A - Wafer-level tin soldering dimpling point and manufacturing method thereof - Google Patents
Wafer-level tin soldering dimpling point and manufacturing method thereof Download PDFInfo
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- CN105070698A CN105070698A CN201510435559.1A CN201510435559A CN105070698A CN 105070698 A CN105070698 A CN 105070698A CN 201510435559 A CN201510435559 A CN 201510435559A CN 105070698 A CN105070698 A CN 105070698A
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- scolding tin
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Abstract
The invention relates to a wafer-level tin soldering dimpling point and a manufacturing method thereof. The wafer-level tin soldering dimpling point comprises a soldering pad formed on an IC wafer and a passivation layer. The passivation layer is provided with an opening. The surface of the soldering pad is exposed at the opening. The soldering pad is successively provided with a sputtered titanium layer and copper layer. The surface of the sputtered copper layer is provided with an electroplated adhesion layer and barrier layer. The barrier layer is provided with a soldering dimpling point. The soldering dimpling point covers the surface of the barrier layer and side parts of the barrier layer and the adhesion layer. The sizes of the adhesion layer and the barrier layer are smaller than the sizes of the copper layer and the titanium layer. Certain intervals exist between the edges of the adhesion layer and the barrier layer and the edges of the copper layer and the titanium layer. The soldering dimpling point covers the surface of the copper layer at the interval and the side parts of the sputtered titanium layer and copper layer. According to the invention, the contact area of the soldering dimpling point and the sputtered copper layer is increased, the adhesiveness between the soldering dimpling point and the sputtered copper layer is improved, and a layered failure is prevented; in addition, the wafer-level tin soldering dimpling point and the manufacturing method thereof solve the problem of an existing wet method etching technology that an electroplated copper layer is undercut in a sputtered metal layer removing process.
Description
Technical field
The present invention relates to a kind of wafer scale scolding tin micro convex point and preparation method thereof, belong to technical field of semiconductor encapsulation.
Background technology
Along with each electronic product is constantly to high integration, high-performance, lightweight and microminiaturized future development, the packaging density of Electronic Packaging is also more and more higher, and the I/O number of chip also gets more and more.In order to meet these requirements, create such as BGA(BallGridArrayPackage, BGA Package), CSP(ChipScalePackage, wafer-level package), FlipChip(flip-chip) etc. Advanced Packaging form.But no matter be which kind of packing forms, wafer-level packaging with its high integration, product cost can be reduced, shorten the advantage such as manufacturing time, become main flow encapsulation technology just gradually.Given this, a key technology in wafer-level packaging---micro convex point technology is also towards small size, pitch, highdensity future development.
Existing micro convex point manufacture craft process comprises: deposit ubm layer, coating photoresist, exposure and development, plating, etching ubm layer, apply scaling powder, backflow, removal scaling powder etc.In existing technique, immersed in etching solution by full wafer wafer during etching ubm layer, with plated solder micro convex point for etch mask carries out isotropism wet etching, a major defect of this technique is exactly the undercutting problem of copper electroplating layer.This is because the density of sputter copper, titanium is higher than the density of electro-coppering, thus the copper electroplating layer be positioned under salient point in metal copper layer is vulnerable to overetch, the otch be inwardly recessed is formed below the nickel dam of barrier layer, thus reduce the reliability of micro convex point i.e. so-called " undercutting (Undercut) ".
Summary of the invention
The object of this part is some aspects of general introduction embodiments of the invention and briefly introduces some preferred embodiments.May do in the specification digest and denomination of invention of this part and the application a little simplify or omit with avoid making this part, specification digest and denomination of invention object fuzzy, and this simplification or omit and can not be used for limiting the scope of the invention.
In view of the problem that there is undercutting in micro convex point manufacturing process in above-mentioned and/or existing wafer-level packaging technique, propose the present invention.
The object of the invention is to overcome the deficiencies in the prior art, a kind of wafer scale scolding tin micro convex point is provided, adds the contact area of scolding tin micro convex point and sputtered Cu layer, improve adhesiveness between the two, avoid the generation that layering was lost efficacy.
The present invention also provides a kind of manufacture method of wafer scale scolding tin micro convex point, avoids the copper electroplating layer undercutting problem caused when existing wet-etching technology removes sputtered metal layer.
According to technical scheme provided by the invention, described wafer scale scolding tin micro convex point, comprise and be formed at pad on IC wafer and passivation layer, be provided with opening over the passivation layer, the surface of pad is exposed in opening part; Described pad sets gradually titanium layer and the layers of copper of sputter, adhesion layer and the barrier layer of plating is set on the layers of copper surface of sputter, scolding tin micro convex point is set over the barrier layer; The described scolding tin micro convex point parcel surface on barrier layer and the sidepiece of barrier layer and adhesion layer, the size on adhesion layer and barrier layer is little compared with the size of layers of copper and titanium layer, the edge on adhesion layer and barrier layer and there is a determining deviation between layers of copper and the edge of titanium layer, scolding tin micro convex point wraps up the surface of this spacing place layers of copper and the layers of copper of sputter and the sidepiece of titanium layer.
The manufacture method of described wafer scale scolding tin micro convex point, comprises the steps:
(1) the IC wafer having formed pad and passivation layer is provided, sputter titanium layer and layers of copper on IC wafer;
(2) in the layers of copper of sputter, adhesion layer and barrier layer is electroplated;
(3) plated solder salient point layer on adhesion layer and barrier layer, the surface on scolding tin salient point layer parcel adhesion layer and barrier layer and sidepiece;
(4) remove unnecessary titanium layer and layers of copper using scolding tin micro convex point as mask, backflow forms micro convex point.
Further, described step (2) electroplates adhesion layer and barrier layer in the layers of copper of sputter, specifically comprises:
(1) at the layers of copper surface-coated ground floor photoresist of sputter, exposure imaging, forms opening above pad, exposes the layers of copper of open bottom;
(2) adhesion layer and barrier layer is electroplated successively in open bottom;
(3) removal ground floor photoresist is peeled off.
Further, described step (3) is plated solder salient point layer on adhesion layer and barrier layer, specifically comprises:
(1) at the layers of copper surface-coated second layer photoresist of sputter, exposure imaging, forms opening above pad, the edge of this opening and have gap between adhesion layer and the edge on barrier layer;
(2) plated solder salient point layer on adhesion layer and barrier layer, scolding tin salient point layer fills the opening on second layer photoresist, and covers the edge of opening;
(3) removal second layer photoresist is peeled off.
Further, the top of described scolding tin salient point layer has the edge wider than bottom, and the lower end of scolding tin salient point layer covers titanium layer and the layers of copper of sputter completely.
Further, the thickness of the titanium layer of described sputter is 1500 ~ 2000, and the thickness of layers of copper is 8000 ~ 10000.
Further, the material of described adhesion layer is copper, and thickness is 5 ~ 10 μm.
Further, described barrier layer material is nickel, and thickness is 1 ~ 2 μm.
Further, described passivation layer material is silica or silicon nitride.
The present invention has the following advantages: plating adhesion layer layers of copper-barrier layer nickel dam is covered completely by solder, when carrying out isotropism wet etching and removing unnecessary sputtered Cu layer and titanium layer, plating adhesion layer layers of copper by overetch, can not be avoided undercutting occurs, thus ensure that the reliability of micro convex point.In addition, solder wraps plating adhesion layer layers of copper-barrier layer nickel dam completely, increases the contact area of scolding tin micro convex point and sputtered Cu layer, improves adhesiveness between the two, avoid the generation that layering was lost efficacy.
Accompanying drawing explanation
In order to be illustrated more clearly in the technical scheme of the embodiment of the present invention, below the accompanying drawing used required in describing embodiment is briefly described, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 ~ Fig. 9 is the schematic diagram of the product that each step of the manufacture method of wafer scale scolding tin micro convex point of the present invention obtains.Wherein:
Fig. 1 is the schematic diagram of described IC wafer.
Fig. 2 is the schematic diagram at layers of copper surface-coated ground floor photoresist.
Fig. 3 is the schematic diagram electroplating adhesion layer layers of copper and barrier layer nickel dam in the open bottom of ground floor photoresist.
Fig. 4 peels off the schematic diagram after removing ground floor photoresist.
Fig. 5 is the schematic diagram of layers of copper surface-coated second layer photoresist.
Fig. 6 is the schematic diagram after plated solder micro convex point.
Fig. 7 peels off the schematic diagram removing second layer photoresist.
Fig. 8 is the schematic diagram after removing unnecessary titanium layer and layers of copper.
The schematic diagram of the wafer scale scolding tin micro convex point that Fig. 9 obtains.
Sequence number in figure: IC wafer 1, pad 2, passivation layer 3, titanium layer 4, layers of copper 5, ground floor photoresist 6, adhesion layer 7, barrier layer 8, second layer photoresist 9, scolding tin salient point layer 10, scolding tin micro convex point 11.
Embodiment
In order to enable above-mentioned purpose of the present invention, feature and advantage become apparent more, are further described the specific embodiment of the present invention below in conjunction with concrete accompanying drawing.
Set forth a lot of detail in the following description so that fully understand the present invention, but the present invention can also adopt other to be different from alternate manner described here carrys out embodiment, those skilled in the art can when without prejudice to doing similar popularization when intension of the present invention, therefore the present invention is by the restriction of following public specific embodiment.
Secondly, the present invention is described in detail in conjunction with schematic diagram, when describing the embodiment of the present invention in detail; for ease of explanation; represent that the profile of device architecture can be disobeyed general ratio and be made partial enlargement, and described schematic diagram is example, it should not limit the scope of protection of the invention at this.In addition, the three-dimensional space that should comprise length, width and the degree of depth in making is being implemented.
Separately, the term " surface " proposed in the present invention, " sidepiece ", etc. indicating position or position relationship for based on orientation shown in the drawings or position relationship, instead of require that the present invention with specific azimuth configuration and operation, therefore must be not understood to limitation of the present invention.
Wafer scale scolding tin micro convex point of the present invention, as shown in Figure 9, comprise and be formed at pad 2 on IC wafer 1 and passivation layer 3, passivation layer 3 is provided with opening, and the surface of pad 2 is exposed in opening part; Described pad 2 sets gradually titanium layer 4 and the layers of copper 5 of sputter, adhesion layer 7 and the barrier layer 8 of plating is set on layers of copper 5 surface of sputter, barrier layer 8 arranges scolding tin micro convex point 11; Described scolding tin micro convex point 11 wraps up the surface on barrier layer 8 and the sidepiece of barrier layer 8 and adhesion layer 7, the size on adhesion layer 7 and barrier layer 8 is little compared with the size of layers of copper 5 and titanium layer 4, there is a determining deviation between the edge on adhesion layer 7 and barrier layer 8 and the edge of layers of copper 5 and titanium layer 4, scolding tin micro convex point 11 wraps up the sidepiece of the surface of this spacing place layers of copper 5 and the layers of copper 5 of sputter and titanium layer 4.The present invention, by said structure, increases the contact area of scolding tin micro convex point and sputtered Cu layer, improves adhesiveness between the two, avoids the generation that layering was lost efficacy.
The manufacture method of wafer scale scolding tin micro convex point of the present invention, as shown in Fig. 1 ~ Fig. 9, this manufacture method comprises the steps: to provide the IC wafer having formed pad and passivation layer, sputter-deposited titanium layer and layers of copper on IC wafer; At the scolding tin micro convex point region of IC wafer plating adhesion layer and barrier layer, then on adhesion layer and barrier layer plated solder salient point layer, remove unnecessary titanium layer and layers of copper using scolding tin salient point layer as mask, backflow forms scolding tin micro convex point.
Concrete, the manufacture method of described wafer scale scolding tin micro convex point, comprises the following steps:
Step one: as shown in Figure 1, provide on IC wafer 1, IC wafer 1 and adopt prior art to form pad 2 and passivation layer 3, passivation layer 3 material can be silica or silicon nitride; Sputter-deposited titanium layer 4 and layers of copper 5 successively on pad 2 and passivation layer 3, the thickness of titanium layer 4 is 1500 ~ 2000, and the thickness of layers of copper 5 is 8000 ~ 10000;
Step 2: as shown in Figure 2, at layers of copper 5 surface-coated ground floor photoresist 6, and exposure imaging, form opening in scolding tin micro convex point region, expose the layers of copper 5 of open bottom;
Step 3: as shown in Figure 3, the open bottom obtained in step 2 electroplates adhesion layer 7 and barrier layer 8 successively; Described adhesion layer 7 material is copper, and thickness is 5 ~ 10 μm; Described barrier layer 8 material is nickel, and thickness is 1 ~ 2 μm; Described adhesion layer 7 is mainly used in strengthening the adhesion with layers of copper 5, improves the conductivity of salient point simultaneously; Described barrier layer 8 is mainly used in the phase counterdiffusion slowed down between scolding tin with copper, improves welding spot reliability;
Step 4: as shown in Figure 4, peels off and removes ground floor photoresist 6;
Step 5: as shown in Figure 5, at layers of copper 5 surface-coated second layer photoresist 9, and exposure imaging, forms opening in scolding tin micro convex point region, this opening and have gap between adhesion layer 7 and barrier layer 8;
Step 6: as shown in Figure 6, plated solder salient point layer 10 on adhesion layer 7 and barrier layer 8, scolding tin salient point layer 10 is filled the opening on second layer photoresist 9 and is covered the edge of opening;
Step 7: as shown in Figure 7, peel off and remove second layer photoresist 9, now the top of scolding tin salient point layer 10 has the edge wider than bottom, the lower end of scolding tin salient point layer 10 covers titanium layer 4 and layers of copper 5 completely, and the edge that scolding tin salient point layer 10 upper end is extended can play the effect of mask in the wet etching process of postorder;
Step 8: as shown in Figure 8, with scolding tin salient point layer 10 for etch mask carries out wet etching, removes the titanium layer 4 and layers of copper 5 that are not covered by scolding tin salient point layer 10 bottom; Top due to scolding tin salient point layer 10 has the edge wider than bottom, this edge can ensure that when carrying out isotropism wet etching the layers of copper 5 of scolding tin salient point layer 10 lower edge can not by overetch carrying out this edge of isotropism wet method, avoid undercutting occurs, thus ensure that the reliability of micro convex point;
Step 9: as shown in Figure 9, carry out high temperature reflux and form scolding tin micro convex point 11, scolding tin micro convex point 11 wraps surface and the sidepiece on adhesion layer 7 and barrier layer 8 completely, increases the contact area of scolding tin micro convex point 11 and layers of copper 5, improve adhesiveness between the two, avoid the generation that layering was lost efficacy.
It should be noted that, above embodiment is only in order to illustrate technical scheme of the present invention and unrestricted, although with reference to preferred embodiment to invention has been detailed description, those of ordinary skill in the art is to be understood that, can modify to technical scheme of the present invention or equivalent replacement, and not departing from the spirit and scope of technical solution of the present invention, it all should be encompassed in the middle of right of the present invention.
Claims (9)
1. a wafer scale scolding tin micro convex point, comprise and be formed at pad (2) on IC wafer (1) and passivation layer (3), passivation layer (3) is provided with opening, and the surface of pad (2) is exposed in opening part; Described pad (2) sets gradually titanium layer (4) and the layers of copper (5) of sputter, adhesion layer (7) and barrier layer (8) of plating is set on layers of copper (5) surface of sputter, barrier layer (8) arrange scolding tin micro convex point (11); It is characterized in that: the described surface of scolding tin micro convex point (11) parcel barrier layer (8) and the sidepiece of barrier layer (8) and adhesion layer (7), the size of adhesion layer (7) and barrier layer (8) is little compared with the size of layers of copper (5) and titanium layer (4), there is a determining deviation between the edge of adhesion layer (7) and barrier layer (8) and the edge of layers of copper (5) and titanium layer (4), scolding tin micro convex point (11) wraps up the sidepiece of the surface at this spacing place layers of copper (5) and the layers of copper (5) of sputter and titanium layer (4).
2. a manufacture method for wafer scale scolding tin micro convex point, is characterized in that, comprises the steps:
(1) the IC wafer having formed pad and passivation layer is provided, sputter titanium layer and layers of copper on IC wafer;
(2) in the layers of copper of sputter, adhesion layer and barrier layer is electroplated;
(3) plated solder salient point layer on adhesion layer and barrier layer, the surface on scolding tin salient point layer parcel adhesion layer and barrier layer and sidepiece;
(4) remove unnecessary titanium layer and layers of copper using scolding tin micro convex point as mask, backflow forms micro convex point.
3. the manufacture method of wafer scale scolding tin micro convex point as claimed in claim 2, is characterized in that: described step (2) electroplates adhesion layer and barrier layer in the layers of copper of sputter, specifically comprises:
(1) at the layers of copper surface-coated ground floor photoresist of sputter, exposure imaging, forms opening above pad, exposes the layers of copper of open bottom;
(2) adhesion layer and barrier layer is electroplated successively in open bottom;
(3) removal ground floor photoresist is peeled off.
4. the manufacture method of wafer scale scolding tin micro convex point as claimed in claim 2, is characterized in that: described step (3) is plated solder salient point layer on adhesion layer and barrier layer, specifically comprises:
(1) at the layers of copper surface-coated second layer photoresist of sputter, exposure imaging, forms opening above pad, the edge of this opening and have gap between adhesion layer and the edge on barrier layer;
(2) plated solder salient point layer on adhesion layer and barrier layer, scolding tin salient point layer fills the opening on second layer photoresist, and covers the edge of opening;
(3) removal second layer photoresist is peeled off.
5. the manufacture method of wafer scale scolding tin micro convex point as claimed in claim 4, it is characterized in that: the top of described scolding tin salient point layer has the edge wider than bottom, the lower end of scolding tin salient point layer covers titanium layer and the layers of copper of sputter completely.
6. the manufacture method of wafer scale scolding tin micro convex point as claimed in claim 2, it is characterized in that: the thickness of the titanium layer of described sputter is 1500 ~ 2000, the thickness of layers of copper is 8000 ~ 10000.
7. the manufacture method of wafer scale scolding tin micro convex point as claimed in claim 2, is characterized in that: the material of described adhesion layer is copper, and thickness is 5 ~ 10 μm.
8. the manufacture method of wafer scale scolding tin micro convex point as claimed in claim 2, it is characterized in that: described barrier layer material is nickel, thickness is 1 ~ 2 μm.
9. the manufacture method of wafer scale scolding tin micro convex point as claimed in claim 2, is characterized in that: described passivation layer material is silica or silicon nitride.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108695289A (en) * | 2017-04-05 | 2018-10-23 | 中芯国际集成电路制造(北京)有限公司 | A kind of semiconductor devices and preparation method thereof, electronic device |
| CN111081553A (en) * | 2019-12-06 | 2020-04-28 | 联合微电子中心有限责任公司 | Semi-buried micro-bump structure and preparation method thereof |
| US20220328614A1 (en) * | 2021-04-09 | 2022-10-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Device structure and methods of forming the same |
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| US20030189261A1 (en) * | 2002-04-03 | 2003-10-09 | Ho-Ming Tong | Under-bump-metallurgy layer |
| CN2550899Y (en) * | 2002-06-17 | 2003-05-14 | 盛威电子股份有限公司 | Lug bottom buffer metal structure |
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| CN108695289A (en) * | 2017-04-05 | 2018-10-23 | 中芯国际集成电路制造(北京)有限公司 | A kind of semiconductor devices and preparation method thereof, electronic device |
| CN108695289B (en) * | 2017-04-05 | 2020-04-10 | 中芯国际集成电路制造(北京)有限公司 | Semiconductor device, manufacturing method thereof and electronic device |
| CN111081553A (en) * | 2019-12-06 | 2020-04-28 | 联合微电子中心有限责任公司 | Semi-buried micro-bump structure and preparation method thereof |
| US20220328614A1 (en) * | 2021-04-09 | 2022-10-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Device structure and methods of forming the same |
| US11715756B2 (en) * | 2021-04-09 | 2023-08-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Device structure and methods of forming the same |
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| Publication number | Publication date |
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| CN105070698B (en) | 2018-01-16 |
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