CN111081553A - Semi-buried micro-bump structure and preparation method thereof - Google Patents
Semi-buried micro-bump structure and preparation method thereof Download PDFInfo
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- CN111081553A CN111081553A CN201911238723.4A CN201911238723A CN111081553A CN 111081553 A CN111081553 A CN 111081553A CN 201911238723 A CN201911238723 A CN 201911238723A CN 111081553 A CN111081553 A CN 111081553A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Abstract
The invention provides a semi-buried micro-bump structure and a preparation method thereof, comprising a substrate; an embedded groove is formed in one surface, far away from the substrate, of the insulating layer; a UBM layer disposed on the embedded groove surface; the bump metal is partially embedded in the embedded groove and arranged on the surface of the UBM layer, the conducting layer is arranged in the insulating layer, and two opposite ends of the conducting layer are respectively connected with the UBM layer and the substrate. Because the UBM layer and the salient point metal in the micro salient point are embedded into the insulating layer, the stability of the micro salient point is enhanced, and the mechanical reliability of the micro salient point can be effectively improved.
Description
Technical Field
The invention relates to the field of semiconductor packaging, in particular to a semi-buried micro-bump structure and a preparation method thereof.
Background
With the development of micro-systems in the directions of multifunction, miniaturization, low power consumption, etc., it is an important development trend of micro-systems to use bumps (Bump) to replace the conventional bonding wires to realize the input/output connection between chips of each functional unit. In the field of traditional microsystem packaging, the back of a chip is generally sintered on a substrate, and the interconnection among chips of each functional unit is realized through a bonding wire, the chips of each functional unit can only be arranged along a plane, and the area of a packaging cavity is larger than the sum of the areas of the chips of each functional unit. With the development of packaging technology, Wafer Level Packaging (WLP) is applied in a large scale with the maturity of technologies such as wafer bonding, bump bonding, thinning and the like, and the technologies such as bump bonding, wafer bonding and the like are adopted to realize the longitudinal stacking of chips of each functional unit, so that the area of a packaging cavity is only required to be larger than that of the largest chip, each functional unit in a microsystem evolves from two-dimensional layout to three-dimensional stacking, and bonding lead connection is changed to bump connection. At present, the size of the bump has been developed from the first hundreds of microns to the micron level, and the problem of mechanical reliability of the bump is increasingly revealed.
A conventional bump structure is shown in fig. 10, in which UBM metal is generally sputtered over a metal pad, a bump plating window is formed over the UBM by thick paste, and copper (Cu), tin-silver (AgSn), or tin (Sn) is plated in the window. According to the salient point with the structure, as the UBM, the Cu, the AgSn and other metals are directly manufactured on the welding spot, a cavity is easily generated on a dissimilar metal interface formed between the UBM and the bonding pad metal, so that the salient point is easy to fall off, and the problem of mechanical reliability is caused.
Therefore, the technical problem of low mechanical reliability of the micro-bump in the prior art is that the problem needs to be solved in the field when the bump size is in the micrometer scale.
Disclosure of Invention
The invention aims to provide a semi-buried micro-bump structure which can obviously improve the mechanical property of the micro-bump structure.
In order to solve the technical problem, the invention provides the following scheme: a semi-buried micro-bump structure comprises a substrate;
an embedded groove is formed in one surface, far away from the substrate, of the insulating layer;
a UBM layer disposed on the embedded groove surface;
the salient point metal is partially embedded in the embedded groove and arranged on the surface of the UBM layer,
and the conductive layer is arranged in the insulating layer, and two opposite ends of the conductive layer are respectively connected with the UBM layer and the substrate.
Further, the method comprises the following steps: the insulating layer is including keeping away from gradually the substrate and first insulating layer, second insulating layer and the third insulating layer that sets gradually, the embedded groove set up in the third insulating layer, the embedded groove opening orientation is kept away from one side of substrate.
Further, the method comprises the following steps: the first, second, and third insulating layers are silicon dioxide and/or silicon nitride.
Further, the method comprises the following steps: the conductive layer includes a first conductive layer and a second conductive layer, the first conductive layer is disposed in the first insulating layer, the second conductive layer is disposed in the second insulating layer, and the first conductive layer and the second conductive layer are in contact with each other.
Further, the method comprises the following steps: the bump metal includes first bump metal and second bump metal, first bump metal set up in the UBM is kept away from the one side of insulating layer is inlayed and is located in the embedded groove, first bump metal height is greater than the degree of depth of embedded groove, second bump metal set up in on the first bump metal. The first bump metal may be, but is not limited to, Cu or Au, the second bump metal may be, but is not limited to, AgSn or Sn, and the UBM layer is TiN.
The application further provides a preparation method of the semi-buried micro-bump structure, which comprises the following steps:
s1: arranging a lower insulating layer on the surface of a substrate, arranging a conducting layer in the lower insulating layer, wherein one end of the conducting layer is flush with the lower insulating layer, and the other end of the conducting layer is in contact with the substrate;
s2: arranging a third insulating layer on one side, far away from the substrate, of the lower insulating layer and one side, far away from the substrate, of the conducting layer;
and S3, arranging an embedded groove penetrating through the third insulating layer at the position of the third insulating layer corresponding to the conducting layer, attaching a UBM layer on the inner surface of the embedded groove, and arranging bump metal in the embedded groove.
Further, the method comprises the following steps: the lower insulating layer includes a first insulating layer and a second insulating layer, the conductive layer includes a first conductive layer and a second conductive layer, and the step S1 includes the steps of:
s101: depositing a first insulating layer on the surface of a substrate, etching a first window penetrating through the first insulating layer on the first insulating layer, arranging a first conducting layer in the first window, and carrying out planarization treatment on the first conducting layer;
s102: depositing a second insulating layer on the first insulating layer and one side of the first conducting layer, which is far away from the surface of the substrate, etching a second window which penetrates through the second insulating layer at the position of the second insulating layer, which corresponds to the first conducting layer, arranging a second conducting layer in the second window, and carrying out planarization treatment on the second conducting layer.
Further, the method comprises the following steps: the first insulating layer is deposited by an LPCVD or PECVD process, and the second and third insulating layers are deposited by a PECVD process.
Further, the method comprises the following steps: the step S3 includes the steps of:
s301: arranging photoresist on the surface of the third insulating layer, exposing and developing at the position corresponding to the conducting layer, etching to form a third window,
s302: sputtering UBM metal in the third window to form a UBM layer, and then sequentially electroplating first salient point metal and second salient point metal;
s303: and removing the residual photoresist to obtain the semi-buried micro-bump structure.
The invention has the beneficial effects that: the UBM layer and the salient point metal in the micro salient points are embedded into the insulating layer, so that the stability of the micro salient points is enhanced, and the mechanical reliability of the micro salient points can be effectively improved.
In addition, the insulating layer, the embedded groove and the salient point metal can be prepared by a conventional process method in the existing advanced packaging process, and have good process compatibility with the advanced packaging process.
Drawings
FIG. 1 is a schematic view of a layered structure of an embodiment of a semi-buried microbump structure according to the present invention;
FIGS. 2 to 9 are schematic views showing the process flow of steps S2 and S3 in the embodiment of the production method of the present invention;
FIG. 10 is a schematic view of a prior art layered structure
The reference numbers are as follows: the semiconductor device comprises a substrate 101, a first insulating layer 102, a first conductive layer 103, a second insulating layer 104, a second conductive layer 105, a third insulating layer 106, a fourth-order photoresist 107, an embedded groove 108, a UBM layer 109, a photoresist 110, a third window 111, a first bump metal 112 and a second bump metal 113.
Detailed Description
The present invention is further described below in conjunction with the following figures and specific examples so that those skilled in the art may better understand the present invention and practice it.
The following discloses many different embodiments or examples for implementing the subject technology described. While specific examples of one or more arrangements of features are described below to simplify the disclosure, the examples should not be construed as limiting the invention, and the first feature described later in the specification in conjunction with the second feature may include embodiments that are directly related, may also include embodiments that form additional features, and further may include embodiments in which one or more additional intervening features are used to indirectly connect or combine the first and second features to each other, so that the first and second features may not be directly related.
For ease of understanding, the noun abbreviations appearing in this application are explained:
UBM layer: a under bump metallization layer;
LPCVD: low pressure chemical vapor deposition;
PECVD: plasma enhanced chemical vapor deposition;
and (3) CMP: chemical mechanical planarization;
it is to be understood that the abbreviations mentioned above are terms of art and that the meaning of the terms mentioned above may be unambiguously identified by a person skilled in the art.
As shown in fig. 1, an embodiment of a semi-buried microbump structure includes a substrate 101, an insulating layer, a UMB layer, and a bump metal sequentially arranged in a layered structure, wherein a surface of the insulating layer away from the substrate 101 is provided with an embedded groove 108, a UBM layer 109 is arranged on an inner side surface of the embedded groove 108, and a height of the bump metal is greater than a depth of the embedded groove 108, so that a portion of the bump metal close to the insulating layer is embedded in the embedded groove 108.
Specifically, the substrate 101 may be, but is not limited to, a monocrystalline silicon substrate 101, the UBM layer 109 may be, but is not limited to, TiN, and the insulating layer may be silicon dioxide, silicon nitride, or a composite dielectric composed of silicon dioxide and silicon nitride.
In addition, the device further comprises a conductive layer embedded in the insulating layer, and two ends of the conductive layer are respectively connected with the UMB layer and the substrate 101.
In some embodiments, the bump metal includes a first bump metal 112 and a second bump metal 113, the height of the first bump metal 112 is greater than the depth of the embedded groove 108, one end of the first bump metal 112 is fixed on the UBM layer 109 and embedded in the embedded groove 108, and the second bump metal 113 is disposed on the first bump metal 112.
The insulating layer includes a first insulating layer 102, a second insulating layer 104, and a third insulating layer 106, which are sequentially disposed away from the substrate 101, and the embedded groove 108 is disposed on the third insulating layer 106. The conductive layers include a first conductive layer 103 and a second conductive layer 105, the first conductive layer 103 is embedded in the first insulating layer 102, the second conductive layer 105 is embedded in the second insulating layer 104, and the first conductive layer 103 and the second conductive layer 105 are in contact with each other.
The first bump metal 112 may be, but is not limited to, Cu or Au, and the second bump metal 113 may be, but is not limited to, AgSn or Sn.
Compared with the conventional micro-bump structure, the stability of the micro-bump under small size can be enhanced by embedding the UBM layer 109 and the bump metal in the micro-bump into the insulating layer as a medium. Thereby achieving the effect of remarkably improving the mechanical reliability of the micro-convex points.
In order to facilitate understanding of the present application, the present application further provides an embodiment of a method for manufacturing the above-mentioned semi-buried microbump structure, as shown in fig. 2 to 9, including the following steps:
s101: a first insulating layer 102 is deposited on the surface of a substrate 101, a first window penetrating through the first insulating layer 102 is etched on the first insulating layer 102, a first conductive layer 103 is disposed in the first window, and planarization processing is performed on the first conductive layer 103.
Specifically, a polished silicon single crystal wafer of 8 inches, <100> crystal orientation and a thickness of 725 ± 25 μm is prepared, cleaned and dried to obtain a substrate 101, and then a first insulating layer 102 is deposited on one surface of the substrate 101 by LPCVD at 720 ℃ to obtain a first insulating layer 102 having a thickness of 1 μm ± 0.1 μm.
The method comprises the steps of arranging photoresist 110 on the surface of a first insulating layer 102, selecting a position where a first conducting layer 103 is to be arranged, carrying out exposure and development, then carrying out etching to obtain a first window, sputtering conducting metal in the first window to obtain the first conducting layer 103, carrying out CMP planarization treatment on the first conducting layer 103 to enable the first conducting layer 103 to be level with the first insulating layer 102, measuring the thickness of the remaining first insulating layer 102, enabling the thickness of the remaining first insulating layer 102 to be smaller than 2nm, and removing the photoresist 110.
S102: depositing a second insulating layer 104 on the first insulating layer 102 and the first conductive layer 103 away from the surface of the substrate 101, etching a second window penetrating through the second insulating layer 104 at a position of the second insulating layer 104 corresponding to the first conductive layer 103, arranging a second conductive layer 105 in the second window, and performing planarization treatment on the second conductive layer 105:
depositing a second insulating layer 104 on the surfaces, far away from the substrate 101, of the first insulating layer 102 and the first conductive layer 103 by a PECVD (plasma enhanced chemical vapor deposition) process, wherein the deposition temperature is 280 ℃, the deposition thickness is 1 [ mu ] m +/-0.1 [ mu ] m, then forming a step-shaped second window on the second insulating layer 104 at a position corresponding to the first conductive layer 103 by two times of photoetching, wherein the diameter of one side, close to the first insulating layer 102, of the second window is smaller, sputtering Ti/TiN metal on a small-diameter part in the second window, and then sputtering a seed layer Cu and electroplating Cu on a large-diameter part in the second window, thereby obtaining a second conductive layer 105, as shown in FIG. 2.
The first insulating layer 102 and the second insulating layer 104 together constitute a lower insulating layer.
S2: as shown in fig. 3, a third insulating layer 106 is deposited on the second insulating layer 104 and the side of the second conductive layer 105 facing away from the first insulating layer 102: the third insulating layer 106 is deposited using a PECVD process, wherein the deposition temperature is 280 ℃.
S3 etching an embedded groove 108 penetrating the third insulating layer 106 at a position of the third insulating layer 106 corresponding to the second conductive layer 105, disposing a UBM layer 109 on an inner surface of the embedded groove 108, i.e., a portion defined as a bottom surface of the embedded groove 108 in the second conductive layer 105, and a portion defined as a sidewall of the embedded groove 108 on the third insulating layer 106, each having the UBM layer 109 sputtered thereon, and then disposing a first bump metal 112 and a second bump metal 113 in the embedded groove 108 in this order:
the method specifically comprises the following two steps:
s301, as shown in fig. 4, a photoresist 110 is disposed on the surface of the third insulating layer 106, and after exposure and development are performed at a position corresponding to the second conductive layer 105, a third window 111 communicating with the second conductive layer 105 is formed by etching, as shown in fig. 5.
S302: first, as shown in fig. 6, a UBM metal is sputtered in the third window 111 to form a UBM layer, and then, as shown in fig. 7 and 8, the first bump metal 112 and the second bump metal 113 are sequentially plated in the third window 111, specifically, the second bump metal 113 can be plated by a reflow plating method.
S303: after removing the residual photoresist 110, the structure shown in fig. 9 is obtained, and after reflow, the microbump structure in which the second bump metal 113 wraps the first bump metal 112 is obtained as shown in fig. 1.
According to the preparation method adopted by the application, the UBM layer 109 and the first bump metal 112 in the micro bumps are embedded in the third insulating layer 106, so that the stability of the micro bumps is enhanced, and the mechanical reliability of the micro bumps can be effectively improved.
In addition, the third insulating layer 106, the embedded groove 108 and the first bump metal 112 in the present invention can be prepared by conventional process methods in the existing advanced packaging process, and have good process compatibility with the advanced packaging process.
Finally, the above embodiments are only for illustrating the technical solutions of the present invention and not for limiting, although the present invention has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that modifications or equivalent substitutions may be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all of them should be covered in the claims of the present invention.
Claims (9)
1. A semi-buried micro-bump structure is characterized by comprising a substrate;
an embedded groove is formed in one surface, far away from the substrate, of the insulating layer;
a UBM layer attached to the embedded groove surface;
the salient point metal is partially embedded in the embedded groove and arranged on the surface of the UBM layer,
a conductive layer disposed in the insulating layer, the conductive layer connecting the UBM layer and the substrate, respectively.
2. The semi-buried microbump structure of claim 1, wherein the insulating layer includes a first insulating layer, a second insulating layer and a third insulating layer disposed in sequence away from the substrate, the embedded slot is disposed in the third insulating layer, and the embedded slot has an opening facing a side away from the substrate.
3. The semi-buried microbump structure of claim 2, wherein the first insulating layer, the second insulating layer, and the third insulating layer are silicon dioxide and/or silicon nitride.
4. The semi-buried microbump structure of claim 2, wherein the conductive layer includes a first conductive layer and a second conductive layer, the first conductive layer being disposed in the first insulating layer, the second conductive layer being disposed in the second insulating layer, and the first conductive layer and the second conductive layer being in contact with each other.
5. The semi-buried microbump structure of claim 1, wherein the bump metal includes a first bump metal and a second bump metal, the first bump metal is disposed on a side of the UBM away from the insulating layer and embedded in the embedded groove, the height of the first bump metal is greater than the depth of the embedded groove, and the second bump metal is disposed on the first bump metal.
6. A preparation method of a semi-buried micro-bump structure comprises the following steps:
s1: arranging a lower insulating layer on the surface of a substrate, arranging a conducting layer in the lower insulating layer, wherein one end of the conducting layer is flush with the lower insulating layer, and the other end of the conducting layer is in contact with the substrate;
s2: arranging a third insulating layer on one side, far away from the substrate, of the lower insulating layer and one side, far away from the substrate, of the conducting layer;
and S3, arranging an embedded groove penetrating through the third insulating layer at the position of the third insulating layer corresponding to the conducting layer, attaching a UBM layer on the inner surface of the embedded groove, and arranging bump metal in the embedded groove.
7. The method as claimed in claim 6, wherein the lower insulating layer comprises a first insulating layer and a second insulating layer, the conductive layer comprises a first conductive layer and a second conductive layer, and the step S1 comprises the steps of:
s101: depositing a first insulating layer on the surface of a substrate, etching a first window penetrating through the first insulating layer on the first insulating layer, arranging a first conducting layer in the first window, and carrying out planarization treatment on the first conducting layer;
s102: depositing a second insulating layer on the first insulating layer and one side of the first conducting layer, which is far away from the surface of the substrate, etching a second window which penetrates through the second insulating layer at the position of the second insulating layer, which corresponds to the first conducting layer, arranging a second conducting layer in the second window, and carrying out planarization treatment on the second conducting layer.
8. The method according to claim 7, wherein the first insulating layer is deposited by LPCVD or PECVD process, and the second insulating layer and the third insulating layer are deposited by PECVD process.
9. The method for preparing a semi-buried microbump structure as claimed in claim 6, wherein the step S3 includes the steps of:
s301: arranging photoresist on the surface of the third insulating layer, exposing and developing at the position corresponding to the conducting layer, etching to form a third window,
s302: sputtering UBM metal in the third window to form a UBM layer, and then sequentially electroplating first salient point metal and second salient point metal;
s303: and removing the residual photoresist to obtain the semi-buried micro-bump structure.
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