CN105070698B - Wafer scale scolding tin micro convex point and preparation method thereof - Google Patents
Wafer scale scolding tin micro convex point and preparation method thereof Download PDFInfo
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- CN105070698B CN105070698B CN201510435559.1A CN201510435559A CN105070698B CN 105070698 B CN105070698 B CN 105070698B CN 201510435559 A CN201510435559 A CN 201510435559A CN 105070698 B CN105070698 B CN 105070698B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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Abstract
The present invention relates to a kind of wafer scale scolding tin micro convex point and preparation method thereof, including the pad and passivation layer being formed on IC wafers, it is exposed in opening provided with opening, the surface of pad over the passivation layer；The titanium layer and layers of copper of sputter are set gradually on the pad, adhesion layer and the barrier layer of plating are set on the layers of copper surface of sputter, scolding tin micro convex point is set over the barrier layer；The surface on the scolding tin micro convex point parcel barrier layer and the sidepiece of barrier layer and adhesion layer, the size on adhesion layer and barrier layer is small compared with the size of layers of copper and titanium layer, a determining deviation between the edge and layers of copper on adhesion layer and barrier layer and the edge of titanium layer be present, scolding tin micro convex point wraps up the surface of layers of copper and the sidepiece of the layers of copper of sputter and titanium layer at the spacing.Invention increases scolding tin micro convex point and the contact area of sputtered Cu layer, improves adhesiveness between the two, avoids the generation of layering failure；Avoid existing wet-etching technology and remove caused copper electroplating layer undercutting problem during sputtered metal layer.
Description
Technical field
The present invention relates to a kind of wafer scale scolding tin micro convex point and preparation method thereof, belong to technical field of semiconductor encapsulation.
Background technology
As each electronic product constantly develops to high integration, high-performance, lightweight and miniaturization direction, Electronic Packaging
Packaging density also more and more higher, the I/O numbers of chip are also more and more.In order to meet these requirements, such as BGA is generated
（Ball Grid Array Package, BGA Package）、CSP（Chip Scale Package, wafer-level package）、
Flip Chip（Flip-chip）Deng Advanced Packaging form.But either which kind of packing forms, wafer-level packaging are highly whole with it
Close, product cost can be reduced, shorten the advantages such as manufacturing time, be increasingly becoming main flow encapsulation technology.In consideration of it, wafer-level packaging
In a key technology --- micro convex point technology is also developing towards small size, pitch, highdensity direction.
Existing micro convex point manufacture craft process includes：Deposit ubm layer, coating photoresist, it is exposed and developed,
Plating, etching ubm layer, coating scaling powder, backflow, removal scaling powder etc..In existing technique, etch under salient point
Full wafer wafer is immersed in etching solution during metal level, isotropism wet method quarter is carried out by etch mask of plated solder micro convex point
Erosion, a major defect of the technique is exactly the undercutting problem of copper electroplating layer.This is due to that sputter copper, the density of titanium are higher than electricity
Copper-plated density, thus the copper electroplating layer in metal copper layer under salient point is vulnerable to overetch, below the nickel dam of barrier layer
Form the otch being inwardly recessed, i.e., so-called " undercutting（Undercut）", so as to reduce the reliability of micro convex point.
The content of the invention
The purpose of this part is to summarize some aspects of embodiments of the invention and briefly introduce some preferably to implement
Example.It may do a little simplified or be omitted to avoid making our department in this part and the description of the present application summary and denomination of invention
Point, the purpose of specification digest and denomination of invention obscure, and this simplification or omit and cannot be used for limiting the scope of the present invention.
In view of the problem of undercutting in above-mentioned and/or existing wafer-level packaging technique in micro convex point manufacturing process be present, propose
The present invention.
The purpose of the present invention is to overcome the deficiencies in the prior art, there is provided a kind of wafer scale scolding tin micro convex point, increase
The contact area of scolding tin micro convex point and sputtered Cu layer, improves adhesiveness between the two, avoids the generation of layering failure.
The present invention also provides a kind of preparation method of wafer scale scolding tin micro convex point, avoids existing wet-etching technology and removes
Caused copper electroplating layer undercutting problem during sputtered metal layer.
According to technical scheme provided by the invention, the wafer scale scolding tin micro convex point, including the weldering being formed on IC wafers
Disk and passivation layer are exposed in opening provided with opening, the surface of pad over the passivation layer；Sputter is set gradually on the pad
Titanium layer and layers of copper, sputter layers of copper surface set plating adhesion layer and barrier layer, over the barrier layer set scolding tin dimpling
Point；The chi on the surface on the scolding tin micro convex point parcel barrier layer and the sidepiece of barrier layer and adhesion layer, adhesion layer and barrier layer
The very little size compared with layers of copper and titanium layer is small, between existing necessarily between the edge and layers of copper on adhesion layer and barrier layer and the edge of titanium layer
Away from scolding tin micro convex point wraps up the surface of layers of copper and the sidepiece of the layers of copper of sputter and titanium layer at the spacing.
The preparation method of the wafer scale scolding tin micro convex point, comprises the following steps：
（1）The IC wafers for having formed pad and passivation layer, sputter titanium layer and layers of copper on IC wafers are provided；
（2）Adhesion layer and barrier layer are electroplated in the layers of copper of sputter；
（3）The table on the plated solder salient point layer on adhesion layer and barrier layer, scolding tin salient point layer parcel adhesion layer and barrier layer
Face and sidepiece；
（4）Unnecessary titanium layer and layers of copper are removed using scolding tin micro convex point as mask, backflow forms micro convex point.
Further, the step（2）Adhesion layer and barrier layer are electroplated in the layers of copper of sputter, is specifically included：
（1）First layer photoresist is coated on the layers of copper surface of sputter, exposure imaging, opening is formed above pad, is exposed
The layers of copper of open bottom；
（2）Adhesion layer and barrier layer are electroplated successively in open bottom；
（3）Peel off and remove first layer photoresist.
Further, the step（3）Plated solder salient point layer, is specifically included on adhesion layer and barrier layer：
（1）Second layer photoresist is coated on the layers of copper surface of sputter, exposure imaging, opening is formed above pad, this is opened
There is gap between the edge and adhesion layer and the edge on barrier layer of mouth；
（2）The plated solder salient point layer on adhesion layer and barrier layer, scolding tin salient point layer fill opening on second layer photoresist
Mouthful, and cover the edge of opening；
（3）Peel off and remove second layer photoresist.
Further, the top of the scolding tin salient point layer is complete with the edge for being wider than bottom, the lower end of scolding tin salient point layer
Cover the titanium layer and layers of copper of sputter.
Further, the thickness of the titanium layer of the sputter is 1500 ~ 2000, and the thickness of layers of copper is 8000 ~ 10000.
Further, the material of the adhesion layer is copper, and thickness is 5 ~ 10 μm.
Further, the barrier layer material is nickel, and thickness is 1 ~ 2 μm.
Further, the passivation layer material is silica or silicon nitride.
The present invention has advantages below：Plating adhesion layer layers of copper-barrier layer nickel dam is completely covered by solder, carry out it is each to
When same sex wet etching removes unnecessary sputtered Cu layer and titanium layer, plating adhesion layer layers of copper will not avoid occurring by overetch
Undercutting, so as to ensure that the reliability of micro convex point.Live to electroplate adhesion layer layers of copper-barrier layer nickel dam in addition, solder is fully wrapped around, increase
The big contact area of scolding tin micro convex point and sputtered Cu layer, improves adhesiveness between the two, avoids the hair of layering failure
It is raw.
Brief description of the drawings
In order to illustrate the technical solution of the embodiments of the present invention more clearly, required use in being described below to embodiment
Accompanying drawing be briefly described, it should be apparent that, drawings in the following description are only some embodiments of the present invention, for this
For the those of ordinary skill of field, on the premise of not paying creative work, it can also be obtained according to these accompanying drawings other
Accompanying drawing.
Fig. 1~Fig. 9 is showing for the product that each step of the preparation method of wafer scale scolding tin micro convex point of the present invention obtains
It is intended to.Wherein：
Fig. 1 is the schematic diagram of the IC wafers.
Fig. 2 is to coat the schematic diagram of first layer photoresist on layers of copper surface.
Fig. 3 is in the open bottom plating adhesion layer layers of copper of first layer photoresist and the schematic diagram of barrier layer nickel dam.
Fig. 4 is to peel off the schematic diagram after removing first layer photoresist.
Fig. 5 is the schematic diagram that layers of copper surface coats second layer photoresist.
Fig. 6 is the schematic diagram after plated solder micro convex point.
Fig. 7 is to peel off the schematic diagram for removing second layer photoresist.
Fig. 8 is to remove the schematic diagram after unnecessary titanium layer and layers of copper.
The schematic diagram for the wafer scale scolding tin micro convex point that Fig. 9 is obtained.
Sequence number in figure：IC wafers 1, pad 2, passivation layer 3, titanium layer 4, layers of copper 5, first layer photoresist 6, adhesion layer 7, stop
Layer 8, second layer photoresist 9, scolding tin salient point layer 10, scolding tin micro convex point 11.
Embodiment
In order that the above objects, features and advantages of the present invention can be more obvious understandable, with reference to specific accompanying drawing pair
The embodiment of the present invention is further described.
Many details are elaborated in the following description to facilitate a thorough understanding of the present invention, still the present invention can be with
It is different from other manner described here using other come embodiment, those skilled in the art can be without prejudice to intension of the present invention
In the case of do similar popularization, therefore the present invention is not limited by following public specific embodiment.
Secondly, combination schematic diagram of the present invention is described in detail, when the embodiment of the present invention is described in detail, for purposes of illustration only, table
Show that the profile of device architecture can disobey general proportion and make partial enlargement, and the schematic diagram is example, and it should not herein
Limit the scope of protection of the invention.In addition, the three-dimensional space of length, width and depth should be included in implementing to make.
In addition, the term " surface " proposed in the present invention, " sidepiece ", etc. indicating position or position relationship be based on shown in accompanying drawing
Orientation or position relationship, rather than require the present invention must with specific azimuth configuration and operation, therefore be not understood to this
The limitation of invention.
Wafer scale scolding tin micro convex point of the present invention, as shown in figure 9, the pad 2 including being formed on IC wafers 1 and passivation
Layer 3, is provided with opening, the surface of pad 2 is exposed in opening on passivation layer 3；The titanium of sputter is set gradually on the pad 2
Layer 4 and layers of copper 5, adhesion layer 7 and the barrier layer 8 of plating are set on the surface of layers of copper 5 of sputter, set scolding tin micro- on barrier layer 8
Salient point 11；The scolding tin micro convex point 11 wraps up surface and the sidepiece of barrier layer 8 and adhesion layer 7 on barrier layer 8, the He of adhesion layer 7
The size on barrier layer 8 is small compared with the size of layers of copper 5 and titanium layer 4, edge and the layers of copper 5 and the side of titanium layer 4 on adhesion layer 7 and barrier layer 8
A determining deviation between edge be present, scolding tin micro convex point 11 wraps up the surface of layers of copper 5 and the layers of copper 5 of sputter and titanium layer 4 at the spacing
Sidepiece.The present invention is increased scolding tin micro convex point and the contact area of sputtered Cu layer, improved between the two by said structure
Adhesiveness, avoid layering failure generation.
The preparation method of wafer scale scolding tin micro convex point of the present invention, as shown in Fig. 1~Fig. 9, the preparation method is included such as
Lower step：The IC wafers for having formed pad and passivation layer, sputter depositing layers of titanium and layers of copper on IC wafers are provided；In IC wafers
Scolding tin micro convex point region plating adhesion layer and barrier layer, then the plated solder salient point layer on adhesion layer and barrier layer, with scolding tin
Salient point layer removes unnecessary titanium layer and layers of copper as mask, and backflow forms scolding tin micro convex point.
Specifically, the preparation method of the wafer scale scolding tin micro convex point, comprises the following steps：
Step 1：As shown in Figure 1, there is provided IC wafers 1, pad 2 and passivation have been formed using prior art on IC wafers 1
Layer 3, the material of passivation layer 3 can be silica or silicon nitride；Sputter depositing layers of titanium 4 and layers of copper successively on pad 2 and passivation layer 3
5, the thickness of titanium layer 4 is 1500 ~ 2000, and the thickness of layers of copper 5 is 8000 ~ 10000；
Step 2：As shown in Fig. 2 first layer photoresist 6 is coated on the surface of layers of copper 5, and exposure imaging, in scolding tin micro convex point
Region forms opening, exposes the layers of copper 5 of open bottom；
Step 3：As shown in figure 3, adhesion layer 7 and barrier layer 8 are electroplated successively in the open bottom that step 2 obtains；It is described
The material of adhesion layer 7 is copper, and thickness is 5 ~ 10 μm；The material of barrier layer 8 is nickel, and thickness is 1 ~ 2 μm；The adhesion layer 7 is main
For strengthening the adhesion with layers of copper 5, while improve the electric conductivity of salient point；The barrier layer 8 is mainly used in slowing down scolding tin and copper
Between phase counterdiffusion, improve welding spot reliability；
Step 4：First layer photoresist 6 is removed as shown in figure 4, peeling off；
Step 5：As shown in figure 5, second layer photoresist 9 is coated on the surface of layers of copper 5, and exposure imaging, in scolding tin micro convex point
Region forms opening, has gap between the opening and adhesion layer 7 and barrier layer 8；
Step 6：As shown in fig. 6, the plated solder salient point layer 10 on adhesion layer 7 and barrier layer 8, scolding tin salient point layer 10 are filled out
The opening filled on second layer photoresist 9 simultaneously covers the edge of opening；
Step 7：Second layer photoresist 9 is removed as shown in fig. 7, peeling off, now the top of scolding tin salient point layer 10 has and is wider than
The edge of bottom, the lower end of scolding tin salient point layer 10 cover all titanium layer 4 and layers of copper 5, and the upper end of scolding tin salient point layer 10 is extended
Edge can play a part of mask during the wet etching of postorder；
Step 8：As shown in figure 8, being that etch mask carries out wet etching with scolding tin salient point layer 10, remove not convex by scolding tin
The titanium layer 4 and layers of copper 5 of point layer 10 bottom covering；Because the top of scolding tin salient point layer 10 has the edge for being wider than bottom, the edge
Carrying out that when the isotropism wet method edge is carrying out isotropism wet etching the lower edge of scolding tin salient point layer 10 can be ensured
Layers of copper 5 will not avoid undercuting by overetch, so as to ensure that the reliability of micro convex point；
Step 9：As shown in figure 9, carrying out high temperature reflux forms scolding tin micro convex point 11, scolding tin micro convex point 11 is fully wrapped around firmly
The surface and sidepiece on adhesion layer 7 and barrier layer 8, increase the contact area of scolding tin micro convex point 11 and layers of copper 5, improve both it
Between adhesiveness, avoid layering failure generation.
It should be noted that the above embodiments are merely illustrative of the technical solutions of the present invention and it is unrestricted, although with reference to preferable
The present invention is described in detail embodiment, it will be understood by those within the art that, can be to the technology of the present invention
Scheme is modified or equivalent substitution, and without departing from the spirit and scope of technical solution of the present invention, it all should cover in this hair
Among bright right.
Claims (7)
1. a kind of preparation method of wafer scale scolding tin micro convex point, it is characterized in that, comprise the following steps：
（1）The IC wafers for having formed pad and passivation layer, sputter titanium layer and layers of copper on IC wafers are provided；
（2）Adhesion layer and barrier layer are electroplated in the layers of copper of sputter；
（3）The plated solder salient point layer on adhesion layer and barrier layer, scolding tin salient point layer parcel adhesion layer and barrier layer surface and
Sidepiece；The top of the scolding tin salient point layer has the edge for being wider than bottom, and the lower end of scolding tin salient point layer covers all sputter
Titanium layer and layers of copper；
（4）Unnecessary titanium layer and layers of copper are removed using scolding tin salient point layer as mask, backflow forms micro convex point.
2. the preparation method of wafer scale scolding tin micro convex point as claimed in claim 1, it is characterized in that：The step（2）In sputter
Layers of copper on electroplate adhesion layer and barrier layer, specifically include：
（1）First layer photoresist is coated on the layers of copper surface of sputter, exposure imaging, opening is formed above pad, exposes opening
The layers of copper of bottom；
（2）Adhesion layer and barrier layer are electroplated successively in open bottom；
（3）Peel off and remove first layer photoresist.
3. the preparation method of wafer scale scolding tin micro convex point as claimed in claim 1, it is characterized in that：The step（3）Adhering to
Plated solder salient point layer on layer and barrier layer, is specifically included：
（1）Second layer photoresist is coated on the layers of copper surface of sputter, exposure imaging, opening is formed above pad, the opening
There is gap between edge and adhesion layer and the edge on barrier layer；
（2）The plated solder salient point layer on adhesion layer and barrier layer, scolding tin salient point layer fill the opening on second layer photoresist, and
Cover the edge of opening；
（3）Peel off and remove second layer photoresist.
4. the preparation method of wafer scale scolding tin micro convex point as claimed in claim 1, it is characterized in that：The thickness of the titanium layer of the sputter
Spend for 1500 ~ 2000, the thickness of layers of copper is 8000 ~ 10000.
5. the preparation method of wafer scale scolding tin micro convex point as claimed in claim 1, it is characterized in that：The material of the adhesion layer is
Copper, thickness are 5 ~ 10 μm.
6. the preparation method of wafer scale scolding tin micro convex point as claimed in claim 1, it is characterized in that：The barrier layer material is
Nickel, thickness are 1 ~ 2 μm.
7. the preparation method of wafer scale scolding tin micro convex point as claimed in claim 1, it is characterized in that：The passivation layer material is oxygen
SiClx or silicon nitride.
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| CN201510435559.1A CN105070698B (en) | 2015-07-22 | 2015-07-22 | Wafer scale scolding tin micro convex point and preparation method thereof |
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| CN105070698B true CN105070698B (en) | 2018-01-16 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20230335578A1 (en) * | 2021-04-09 | 2023-10-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Device structure and methods of forming the same |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108695289B (en) * | 2017-04-05 | 2020-04-10 | 中芯国际集成电路制造(北京)有限公司 | Semiconductor device, manufacturing method thereof and electronic device |
| CN111081553A (en) * | 2019-12-06 | 2020-04-28 | 联合微电子中心有限责任公司 | Semi-buried micro-bump structure and preparation method thereof |
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| CN1700435A (en) * | 2004-05-20 | 2005-11-23 | 恩益禧电子股份有限公司 | Semiconductor device |
| CN1841689A (en) * | 2005-03-28 | 2006-10-04 | 富士通株式会社 | Semiconductor device and semiconductor-device manufacturing method |
| CN102237316A (en) * | 2010-04-22 | 2011-11-09 | 台湾积体电路制造股份有限公司 | Integrated circuit element and forming method of bumping block structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| TWI307152B (en) * | 2002-04-03 | 2009-03-01 | Advanced Semiconductor Eng | Under bump metallurgy |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2550899Y (en) * | 2002-06-17 | 2003-05-14 | 盛威电子股份有限公司 | Lug bottom buffer metal structure |
| CN1700435A (en) * | 2004-05-20 | 2005-11-23 | 恩益禧电子股份有限公司 | Semiconductor device |
| CN1841689A (en) * | 2005-03-28 | 2006-10-04 | 富士通株式会社 | Semiconductor device and semiconductor-device manufacturing method |
| CN102237316A (en) * | 2010-04-22 | 2011-11-09 | 台湾积体电路制造股份有限公司 | Integrated circuit element and forming method of bumping block structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US20230335578A1 (en) * | 2021-04-09 | 2023-10-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Device structure and methods of forming the same |
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| CN105070698A (en) | 2015-11-18 |
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