CN103325700B - A kind ofly realize interconnected method of through hole and products thereof by bottom-up filling - Google Patents
A kind ofly realize interconnected method of through hole and products thereof by bottom-up filling Download PDFInfo
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- CN103325700B CN103325700B CN201310168540.6A CN201310168540A CN103325700B CN 103325700 B CN103325700 B CN 103325700B CN 201310168540 A CN201310168540 A CN 201310168540A CN 103325700 B CN103325700 B CN 103325700B
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Abstract
The invention discloses and a kind ofly realize the interconnected method of through hole by bottom-up filling, comprising: (a) processes obtained blind hole on a surface of substrate; B () grows insulating barrier, barrier layer and Seed Layer successively on the substrate surface of processing blind hole; C () is coated with photoresist on the surface to Seed Layer and fills and leads up blind hole, then perform exposure and development treatment, to make photoresist only at the Seed Layer left on surfaces of blind via bottom; D () removes the Seed Layer not covering photoresist, and the Seed Layer of blind via bottom is unaffected; E () removes residual photoresist; F () completes bottom-up growth to filled conductive material in blind hole; G the surface of the undressed blind hole of () thinning substrate forms through hole, complete through hole interconnection process thus.The invention also discloses corresponding through hole interconnect architecture product.By the present invention, can so that manipulation, low cost, high efficiency mode perform the electroplates in hole process, and obtain filling effect better through hole interconnect architecture product.
Description
Technical field
The invention belongs to technical field of semiconductor encapsulation, more specifically, relate to and a kind ofly realize interconnected method of through hole and products thereof by bottom-up filling.
Background technology
In the past few decades, integrated circuit processing technique follows Moore's Law and remains development at a high speed, the performance of chip obtains and greatly promotes, power consumption and cost also decline significantly, but the development of Electronic Encapsulating Technology is but relatively slow, become one of bottleneck of restriction semiconductor technology evolves gradually, the integrated form of traditional two dimension cannot meet the industry such as consumer electronics, Aero-Space to the speed of integrated circuit and the more and more higher requirement of volume, and therefore three-dimensional integration technology is subject to increasing attention and research.In numerous three-dimensional integration technologies, interconnecting silicon through holes technology (TSV) is a kind of novel solution, and it by making the through hole of Z-direction on silicon chip, and in through hole, filled conductive material realizes the interconnection between different chip.The interconnection technique of this vertical direction can reduce the length of interconnection line between chip, thus the delay problem that can solve between chip, reduce chip area, improve integration density, surmount the limitation of Planar integration, allow microelectronic industry continue to develop according to Moore's Law.
One of key of TSV technology is that the filling of through hole realizes signal of telecommunication interconnection.Usually adopt the mode of plating to perform filling through hole in prior art, wherein a kind of the electroplates in hole mode is sputtering seed layer on through-hole wall, then electroplates; This electro-plating method is owing to being that whole through hole is electroplated in the vertical simultaneously, need special electroplating device, and electroplating velocity is slow, require high to electroplate liquid, thicker at the coating of silicon chip surface, and through hole upper and lower port can be there is first close, cause copper post inside to have hole, the defect such as hollow, reduce electrical property and the sealing of chip simultaneously, affect device lifetime.
Another kind of the electroplates in hole mode is bottom-up electroplating technology, and electroplating process is that copper deposits from one end of TSV through hole, upwards grows along through hole, the whole through hole of final filling.Bottom-up electro-plating method generally needs to provide a through hole, adopts auxiliary disk as electroplating cathode, or utilizes the characteristic of plating cross growth at disk one face closure silicon through hole, realizes bottom-up plating thus.Compared with electroplating with conformal, bottom-up plating does not need special installation, and speed is fast, and low to the requirement of electroplate liquid, and the coating of silicon chip surface also can control.But the method Seed Layer makes the extra processing step of general needs, as made auxiliary disk, auxiliary disk ephemeral key closes; Or need to carry out Seed Layer filling, plating in advance at the electroplated disk back side; Therefore there is technological process long, the defects such as inefficiency.
Summary of the invention
For above defect or the Improvement requirement of prior art, the invention provides and a kind ofly realize interconnected method of through hole and products thereof by bottom-up filling, its object is to by studying and corresponding adjusting process step the growth mechanism of filling through hole material and process, can so that manipulation, low cost, high efficiency mode perform the electroplates in hole process, and obtain filling effect better through hole interconnect architecture product.
According to one aspect of the present invention, provide and a kind ofly realize the interconnected method of through hole by bottom-up filling, it is characterized in that, the method comprises the following steps:
A () processes obtained blind hole on a surface of substrate, and make the degree of depth of blind hole be not less than its diameter;
B () grows insulating barrier, barrier layer and Seed Layer successively on the whole substrate surface of the obtained blind hole of processing;
C () is coated with photoresist and fills and leads up blind hole on the surface of described Seed Layer, then perform exposure and development treatment to photoresist, be only in the Seed Layer left on surfaces of blind via bottom to make photoresist;
D () performs Transformatin to Seed Layer not covered by photoresist on substrate, in the process, the Seed Layer of blind via bottom is unaffected due to the protection by residual photoresist;
E () removes the residual photoresist of blind via bottom, expose the Seed Layer bottom it;
F (), to filled conductive material in blind hole, in the process, using the Seed Layer of blind via bottom as boot media, utilizes the growth variation of electric conducting material in blind hole between Seed Layer and barrier layer to complete bottom-up growth;
G () another surface to the undressed blind hole of substrate performs reduction processing, until blind hole is formed through hole, complete the through hole interconnect architecture product of through hole interconnection process also needed for acquisition thus.
As further preferably, in step (a)., process obtained blind hole by deep reaction ion etching, laser ablation or wet etching; The quantity of described blind hole is one or more, and wherein blind hole aperture is between 1 micron ~ 1000 microns, and the degree of depth is between 10 microns ~ 1000 microns, and the degree of depth of blind hole is 1 ~ 50 times of its diameter.
As further preferably, in step (b), the material of described insulating barrier is selected from mixture or the complex of silicon dioxide, silicon nitride, alundum (Al2O3), polyimides, Parylene, polybenzocyclobutene or photoresist and above-mentioned material, and preferably adopt thermal oxidation, the mode of physical vapor deposition or chemical vapor deposition formed; Described barrier layer is titanium barrier layer, titanium-tungsten barrier bi-layer, titanium-titanium nitride barrier bi-layer or tantalum-tantalum nitride barrier bi-layer, and preferably adopts the mode of atomic layer deposition, physical vapor deposition or chemical vapor deposition to be formed; Described Seed Layer is the material such as copper or gold formation, and preferably adopt chemical plating, electrochemistry grafting, atomic layer deposition, physical vapor deposition or chemical vapor deposition mode formed.
As further preferably, in step (c), be coated with photoresist when there being the surface of Seed Layer to substrate deposition and after filling and leading up blind hole, its entirety put in vacuum environment to perform and vacuumize process, the bubble of discharging blind hole internal residual thus makes photoresist in blind hole, obtain fully filling.
As further preferably, described photoresist is positive photoresist or negative photoresist, and the vacuum degree of vacuum environment is set to-0.3MPa ~ 0.05MPa.
As further preferably, in step (c), by laser, electron beam or ion beam mode, exposure is performed to photoresist, after exposure heating firmly treatment is performed to photoresist, be then soaked in developer solution or by spray developing liquid and perform development treatment.
As further preferably, in step (c), the photoresist thickness remained on the surface in the Seed Layer of blind via bottom is set to be less than 1/2 of blind hole depth value.
As further preferably, in step (d), remove Seed Layer not covered by photoresist on substrate by the method such as wet etching, dry etching.
As further preferably, in process step (e), the mode of acetone immersion is preferably adopted to remove the residual photoresist of blind via bottom.
As further preferably, in step (f), described packing material is selected from copper, gold, silver or its mixture, and fill method preferentially selects plating.
As further preferably, after step (g), also comprise the step removed dry film, pad, the rerouting of line layer and/or make salient point.
As further preferably, described substrate is selected from the compound semiconductor such as the element semiconductor such as silicon, germanium or GaAs, InP, gallium nitride.
According to another aspect of the present invention, additionally provide corresponding through hole interconnect architecture product.
In general, according to above technical scheme of the present invention compared with prior art, following technical characterstic is mainly possessed:
1, by studying the growth mechanism of filling through hole material and process, there is very large growth variation in packing material in Seed Layer and barrier layer; And after process of the present invention, Seed Layer only exists at blind via bottom, impel the growth rate of blind via bottom packing material by the growth rate much larger than blind hole sidewall, packing material by with the Seed Layer of blind via bottom for boot media, deposit from blind via bottom, and realize bottom-up high speed, high-quality filling;
2, due to realization is a kind of bottom-up filling mode, requires low compared to general conformal plating during plating to solution composition; Meanwhile, can electroplating current be strengthened, improve electroplating efficiency, and need not worry because blind hole opening first closes and cause inside to occur the situations such as defect;
3, the surface of substrate is not owing to having Seed Layer, and plating rear surface can not produce coating, thus when post-processed, did not need CMP(chemico-mechanical polishing) etc. process, process costs can be reduced;
4, be convenient to manipulation according to manufacture method of the present invention, filling quality is high, and the processing step of through hole interconnect architecture can be simplified, reduce process costs, be thus particularly useful for large batch of suitability for industrialized production purposes.
Accompanying drawing explanation
Fig. 1 is achieved in accordance with the invention by bottom-up filling and realizes the interconnected process flow diagram of through hole;
Fig. 2 a is for being presented at structural representation substrate processing blind hole;
Fig. 2 b be processed with blind hole for being presented at substrate surface on the structural representation of deposition insulating layer, barrier layer and Seed Layer successively;
Fig. 2 c has for being presented at substrate deposition the surface of Seed Layer to be coated with photoresist and structural representation after filling and leading up blind hole;
Fig. 2 d performs the structural representation after exposure and development treatment for showing to photoresist;
Fig. 2 e is for showing with blind via bottom photoresist for protection mechanism, removing the structural representation of the Seed Layer come out in blind hole;
Fig. 2 f is for showing the structural representation removing photoresist residual in blind hole;
Fig. 2 g is the structural representation of filling for showing the blind hole that contains Seed Layer to bottom.
In all of the figs, identical Reference numeral is used for representing identical element or structure, wherein:
1-substrate 2-insulating barrier 3-barrier layer 4-Seed Layer 5-photoresist 6-electric conducting material
Embodiment
In order to make object of the present invention, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.In addition, if below in described each execution mode of the present invention involved technical characteristic do not form conflict each other and just can mutually combine.
Fig. 1 realizes the interconnected process flow diagram of through hole according to of the present invention by bottom-up filling.As shown in fig. 1, mainly comprise the following steps: according to the method realizing through hole interconnected of the present invention
First, shown in Fig. 2 a, the obtained blind hole of the upper processing of a surface (being shown as upper surface in figure) on the substrate 1, and make the degree of depth of blind hole be not less than its diameter.Substrate can select semi-conducting material, as compound semiconductors such as the element semiconductor such as silicon, germanium or GaAs, InP, gallium nitride.Two surfaces of substrate can there be the semiconductor device, multilayer electricity interlinkage layer or the micro-sensor structure that complete, pad or passivation layer can also be comprised.The obtained multiple blind hole of processing on the surface of substrate 1, from 1 micron to 1000 microns not etc., its cross section is generally circular or square for the diameter of blind hole; The degree of depth of blind hole is not less than its diameter, is preferably set to 1 times of its diameter to 50 times in the present invention.Above-mentioned blind hole can be processed obtained by deep reaction ion etching (DRIE), laser ablation or wet etching.
Then, shown in Fig. 2 b, deposition insulating layer 2, barrier layer 3 and Seed Layer 4 successively on the whole substrate surface of the obtained blind hole of processing, be formed with the insulating barrier of layer structure, barrier layer and Seed Layer thus successively at other positions of substrate surface of blind via bottom, blind hole sidewall and undressed blind hole.The material of insulating barrier 2 is selected from mixture or the complex of silicon dioxide, silicon nitride, alundum (Al2O3), polyimides, Parylene, polybenzocyclobutene or photoresist and above-mentioned material, and preferably adopt thermal oxidation, the mode of physical vapor deposition (PVD) or chemical vapor deposition (CVD) formed.Barrier layer 3 is titanium barrier layer, titanium-tungsten (Ti-W) barrier bi-layer, titanium-titanium nitride (Ti-TiN) barrier bi-layer or tantalum-tantalum nitride (Ta-TaN) barrier bi-layer, and preferably adopts the modes such as atomic layer deposition (ALD), physical vapor deposition (PVD) or chemical vapor deposition (CVD) to be formed; Seed Layer 4 is that copper (Cu) or the gold material such as (Au) are formed, and preferably adopt chemical plating, electrochemistry grafting, atomic layer deposition (ALD), physical vapor deposition (PVD) or chemical vapor deposition (CVD) mode formed.
Then, as is seen in fig 2 c and 2d, Seed Layer 4 whole surface on be for example coated with photoresist 5 by spin coating mode and fill and lead up blind hole, then to photoresist perform exposure and development treatment, with make photoresist only be in blind via bottom Some Species sublayer left on surfaces and cover Seed Layer.In the process, according to a preferred embodiment of the present invention, after blind hole filled and led up by coating photoresist, its entirety can be put execution in vacuum environment and vacuumize process, the bubble can discharging blind hole internal residual thus makes photoresist in blind hole, obtain the effect of fully filling.Described photoresist 5 is photo-sensitive characteristics, can be negative photoresist or positive photoresist; The vacuum degree of vacuum environment is set to-0.3MPa ~ 0.05MPa.Expose with specific equipment as mask aligner, or perform with laser, electron beam or ion beam.After exposure, preferably can select to heat by hot plate, baking oven or infrared mode to be applied to on-chip photoresist 5, carry out post bake step to improve photoetching quality.Development refers to and is soaked in developer solution by the substrate 1 scribbling photoresist 5, or passes through the method for spray developing liquid, removes a part of photoresist, thus the figure needed for being formed.According to another preferred implementation of the present invention, in above-mentioned steps, after photoresist 5 exposure imaging, only at blind via bottom residual fraction photoresist, make blind hole major part region come out thus, its one-tenth-value thickness 1/10 of photoresist residual is in this way set to be less than 1/2 of blind hole depth value.
Then, with reference to shown in Fig. 2 e, using the photoresist 5 of blind via bottom as mask, by the technique of wet etching or dry etching, the Seed Layer 4 come out is removed.Due to the protective effect of photoresist 5, by the Seed Layer 4 of photoresist 5 overlay area by the impact not by etching technics.Seed Layer 4 can be copper, gold etc.The thickness of Seed Layer is preferably between 10 nanometers to 10 micron.
Then, shown in Fig. 2 f, can for example adopt chemical mode to remove photoresist 5 residual in blind hole, and expose the Seed Layer bottom it, preferably adopt the mode that acetone soaks in the process.
Then, with reference to shown in Fig. 2 g, fill up electric conducting material 6 in blind hole, filling is generally the method adopting plating or chemical plating, and the material of filling is generally copper, also can be the mixture of the materials such as gold, silver or other metals, alloy.Although the barrier layer 3 on blind hole sidewall is also that band is conductive, but cover owing to there is no Seed Layer, packing material 6 growth rate on it will much smaller than the growth rate at bottom seed layer 4 place, packing material 6 by with the Seed Layer 4 of via bottoms for boot media, deposit from blind via bottom, realize bottom-up high speed, high-quality plating is filled.Finally, reduction processing is performed to another surface of the undressed blind hole of substrate, until blind hole is formed through hole, obtains required through hole interconnect architecture product thus.
In sum, only retain the Seed Layer of deposit in the present invention at through hole, utilize the growth variation of blind hole packing material in Seed Layer and barrier layer, with the Seed Layer of via bottoms for boot media, realize bottom-up growth; In addition, the surface of substrate is not owing to having Seed Layer, and plating rear surface can not produce coating, thus when post-processed, do not need the techniques such as CMP.Correspondingly, the manufacture craft of the bottom-up plating filling of through hole can be simplified according to manufacture craft of the present invention, reduce the process costs that through hole interconnect architecture makes, possess simultaneously and be convenient to manipulation, filling quality advantages of higher, be thus particularly useful for large batch of suitability for industrialized production purposes.
Those skilled in the art will readily understand; the foregoing is only preferred embodiment of the present invention; not in order to limit the present invention, all any amendments done within the spirit and principles in the present invention, equivalent replacement and improvement etc., all should be included within protection scope of the present invention.
Claims (5)
1. realize the interconnected method of through hole by bottom-up filling, it is characterized in that, the method comprises the following steps:
A () processes obtained multiple blind hole by deep reaction ion etching, laser ablation or wet etching on a surface of substrate, and make the degree of depth of each blind hole be not less than its diameter; The material of wherein said substrate is selected from silicon, germanium, GaAs or gallium nitride, and its two surfaces has the semiconductor device, multilayer electricity interlinkage layer or the micro-sensor structure that complete; The cross section of blind hole described in each is circular or square, and its aperture is 1 micron to 1000 microns, and the degree of depth is 10 microns to 1000 microns, and blind hole depth is set to 1 times of blind hole aperture to 50 times;
B () grows insulating barrier, barrier layer and Seed Layer successively on the whole substrate surface of the obtained described blind hole of processing, be formed with the insulating barrier of layer structure, barrier layer and Seed Layer thus at other positions of substrate surface of blind via bottom, blind hole sidewall and undressed blind hole successively;
C () is coated with photoresist and fills and leads up described blind hole on the whole surface of described Seed Layer, then exposure and development treatment are performed to photoresist, with make photoresist only be in described blind via bottom Some Species sublayer left on surfaces and cover described Seed Layer, and the one-tenth-value thickness 1/10 of residual photoresist be set to be less than 1/2 of described blind hole depth value; In addition, in this step, be coated with photoresist when there being the surface of described Seed Layer to substrate deposition and after filling and leading up blind hole, its entirety put in vacuum environment to perform and vacuumize process, discharge the bubble of blind hole internal residual thus, photoresist is obtained in blind hole and fully fills;
D () performs Transformatin to Seed Layer not covered by photoresist on substrate, in the process, the Seed Layer of blind via bottom is unaffected due to the protection by residual photoresist; Wherein the material of this Seed Layer is selected from copper or gold, and its thickness is that 10 nanometers are to 10 microns;
E () removes the residual photoresist of described blind via bottom, expose the Seed Layer bottom it;
F (), to filled conductive material in described blind hole, in the process, using the Seed Layer of blind via bottom as boot media, utilizes the growth variation of electric conducting material in blind hole between Seed Layer and barrier layer to complete bottom-up growth;
G () another surface to the undressed blind hole of substrate performs reduction processing, until blind hole is formed through hole, complete the through hole interconnect architecture product of through hole interconnection process also needed for acquisition thus.
2. the method for claim 1, it is characterized in that, in step (b), the material of described insulating barrier is selected from mixture or the complex of silicon dioxide, silicon nitride, alundum (Al2O3), polyimides, Parylene, polybenzocyclobutene or photoresist and above-mentioned material, and adopt thermal oxidation, the mode of physical vapor deposition or chemical vapor deposition formed; Described barrier layer is titanium barrier layer, titanium-tungsten barrier bi-layer, titanium-titanium nitride barrier bi-layer or tantalum-tantalum nitride barrier bi-layer, and adopts the mode of atomic layer deposition, physical vapor deposition or chemical vapor deposition to be formed; Described Seed Layer adopt chemical plating, electrochemistry grafting, atomic layer deposition, physical vapor deposition or chemical vapor deposition mode formed.
3. method as claimed in claim 2, it is characterized in that, described photoresist is positive photoresist or negative photoresist, and the vacuum degree of described vacuum environment is set to-0.3Mpa ~ 0.05Mpa.
4. method as claimed in claim 1 or 2, it is characterized in that, in step (f), described packing material is selected from copper, gold, silver or its mixture, and fill method selects plating.
5. method as claimed in claim 4, is characterized in that, after step (g), also comprises the step removed dry film, pad, the rerouting of line layer and/or make salient point.
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| CN104952934B (en) * | 2015-06-25 | 2018-05-01 | 京东方科技集团股份有限公司 | Thin film transistor (TFT) and manufacture method, array base palte, display panel |
| CN106191862A (en) * | 2016-07-25 | 2016-12-07 | 中国电子科技集团公司第四十研究所 | A kind of method making solid metal hole on substrate |
| CN106783634B (en) * | 2016-12-26 | 2019-09-20 | 通富微电子股份有限公司 | One kind being fanned out to packaging and its packaging method |
| CN112340694B (en) * | 2020-11-03 | 2023-05-12 | 中国电子科技集团公司第二十九研究所 | Preparation method of glass micro-channel radiator for gallium nitride power amplifier chip |
| CN113026067A (en) * | 2021-03-04 | 2021-06-25 | 珠海市创智芯科技有限公司 | Electroplating solution and electroplating process for wafer level packaging |
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| CN1275802A (en) * | 1999-05-26 | 2000-12-06 | 日本电气株式会社 | Semiconductor device and making method thereof |
| US6610596B1 (en) * | 1999-09-15 | 2003-08-26 | Samsung Electronics Co., Ltd. | Method of forming metal interconnection using plating and semiconductor device manufactured by the method |
| CN102130042A (en) * | 2010-12-14 | 2011-07-20 | 北京大学 | Method for manufacturing through hole interconnection structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1275802A (en) * | 1999-05-26 | 2000-12-06 | 日本电气株式会社 | Semiconductor device and making method thereof |
| US6610596B1 (en) * | 1999-09-15 | 2003-08-26 | Samsung Electronics Co., Ltd. | Method of forming metal interconnection using plating and semiconductor device manufactured by the method |
| CN102130042A (en) * | 2010-12-14 | 2011-07-20 | 北京大学 | Method for manufacturing through hole interconnection structure |
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