CN107858728B - TSV electro-plating method - Google Patents
TSV electro-plating method Download PDFInfo
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- CN107858728B CN107858728B CN201711387502.4A CN201711387502A CN107858728B CN 107858728 B CN107858728 B CN 107858728B CN 201711387502 A CN201711387502 A CN 201711387502A CN 107858728 B CN107858728 B CN 107858728B
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- 238000009713 electroplating Methods 0.000 title claims abstract description 62
- 238000000034 method Methods 0.000 title claims abstract description 62
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 141
- 239000010703 silicon Substances 0.000 claims abstract description 141
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 140
- 229910052751 metal Inorganic materials 0.000 claims abstract description 70
- 239000002184 metal Substances 0.000 claims abstract description 70
- 238000007747 plating Methods 0.000 claims abstract description 35
- 239000007788 liquid Substances 0.000 claims abstract description 22
- 230000008569 process Effects 0.000 claims abstract description 20
- 239000000654 additive Substances 0.000 claims abstract description 12
- 230000000996 additive effect Effects 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 239000003795 chemical substances by application Substances 0.000 claims description 12
- 238000000151 deposition Methods 0.000 claims description 10
- 230000008021 deposition Effects 0.000 claims description 10
- 238000009499 grossing Methods 0.000 claims description 10
- 239000003112 inhibitor Substances 0.000 claims description 9
- 239000010949 copper Substances 0.000 claims description 8
- 230000005611 electricity Effects 0.000 claims description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 238000002385 metal-ion deposition Methods 0.000 claims description 6
- 230000004888 barrier function Effects 0.000 claims description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 4
- 239000010931 gold Substances 0.000 claims description 4
- 229910052737 gold Inorganic materials 0.000 claims description 4
- 238000004891 communication Methods 0.000 abstract description 5
- 238000001465 metallisation Methods 0.000 abstract description 3
- 238000005516 engineering process Methods 0.000 description 7
- 239000000463 material Substances 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- 238000001179 sorption measurement Methods 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910021645 metal ion Inorganic materials 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 241000112839 Ampheres Species 0.000 description 1
- JPVYNHNXODAKFH-UHFFFAOYSA-N Cu2+ Chemical compound [Cu+2] JPVYNHNXODAKFH-UHFFFAOYSA-N 0.000 description 1
- 101150054854 POU1F1 gene Proteins 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910001431 copper ion Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 238000001764 infiltration Methods 0.000 description 1
- 230000008595 infiltration Effects 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 230000006911 nucleation Effects 0.000 description 1
- 238000010899 nucleation Methods 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D7/00—Electroplating characterised by the article coated
- C25D7/12—Semiconductors
- C25D7/123—Semiconductors first coated with a seed layer or a conductive layer
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D3/00—Electroplating: Baths therefor
- C25D3/02—Electroplating: Baths therefor from solutions
- C25D3/38—Electroplating: Baths therefor from solutions of copper
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
- C25D5/10—Electroplating with more than one layer of the same or of different metals
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- Chemical & Material Sciences (AREA)
- Engineering & Computer Science (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Electrochemistry (AREA)
- Materials Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Electroplating Methods And Accessories (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The present invention provides a kind of TSV electro-plating methods, additive is added in electroplate liquid, through silicon via in silicon base and the groove communicated therewith are electroplated, electroplating process is divided into three phases by adjusting electroplating current, the electroplating current of three phases is respectively the first current value, second current value third current value, wherein, first current value is less than second current value, second current value is less than the third current value, pass through the change of electroplating current, metal deposition rates in through silicon via and groove in communication change, and finally through silicon via and groove are filled up, the pit of corresponding through silicon via is not formed at the top of plating metal, after removing higher than the electroplated layer excessively of silicon substrate surface, the available TSV structure with flat surfaces.
Description
Technical field
The present invention relates to electroplating technologies, in particular to TSV electro-plating method.
Background technique
With being constantly progressive for microelectric technique, the characteristic size of integrated circuit constantly reduces, and interconnection density is continuously improved,
Requirement of the user to high-performance low power consumption simultaneously is continuously improved.In this case, by the line width for further reducing interconnection line
Propose limitation of the high performance mode by physical characteristics of materials and apparatus and process, and the RC (resistance capacitance) of two-dimensional interconnection line prolongs
It is increasingly becoming the bottleneck that limitation semiconductor core piece performance improves late.TSV (Through Silicon Via, through silicon via) technique is logical
Cross and form metal upright post in wafer, and be equipped with metal salient point, may be implemented between wafer (chip) or between chip and substrate it is straight
The three-dimensional interconnection connect can make up the limitation of conventional semiconductor chip two dimension wiring in this way.That is, TSV technology can mention
The integrated level of high density integrated circuit can greatly shorten line between integrated circuit, and then obtain RC retardation ratio and power consumption all significantly
Reducing, this interconnection mode can make the performance of integrated circuit be greatly improved from many aspects, meanwhile, TSV technology is also
Different process material and different functional modules can be integrated together, be brought great convenience to the optimization of chip overall performance.This
A little significant advantages, which all make TSV technology in recent years, becomes popular research field.
The key of TSV technology first is that the through silicon via of the channel region of double of conductor element and the groove being connected to through silicon via into
Row metal plating is to realize that electric signal interconnects.Existing TSV electro-plating method is in filling silicon through holes and the groove being connected to through silicon via
Afterwards, it will form pit in the region that plating layer surface corresponds to through silicon via, still to this pit after electroplated layer progress CMP process
In the presence of this phenomenon is especially apparent when being greater than 1 μm for the aperture of through silicon via.Fig. 1 is formed by using existing TSV technique
The photo of TSV structure.As shown in figure 1, TSV structure (including filling after through silicon via and groove in communication) in through silicon via
Surface surface is formed with pit 10, exists and will cause influence to subsequent connecting line technics again and semiconductor devices production.
Summary of the invention
The problem to be solved in the present invention is to be formed using existing TSV electro-plating method on the surface that TSV structure corresponds to through silicon via
The problem of pit.
To solve the above problems, the present invention provides a kind of TSV electro-plating methods characterized by comprising
A silicon base is provided, the groove that through silicon via is formed in the silicon base and is connected to the through silicon via is described
Groove is set to the surface of the silicon base；Seed layer is formed in the inner wall of the through silicon via and the groove；By the silicon substrate
The electroplate liquid containing additive is immersed at bottom, and under conditions of the first current value, plating forms the first metal layer, first metal
Layer covers the seed layer but does not fill up the through silicon via；Under conditions of the second current value, plating forms second metal layer,
The second metal layer covers the first metal layer but does not fill up the through silicon via；And the condition in third current value
Under, plating forms third metal layer, until filling up the through silicon via and the groove；Wherein, first current value is less than institute
The second current value is stated, second current value is less than the third current value.
Optionally, the additive includes smoothing agent, inhibitor and accelerator.The smoothing agent is in the electroplate liquid
Weight ratio is 4%~6%, and weight ratio of the inhibitor in the electroplate liquid is 1.5%~3.5%, the acceleration
Weight ratio of the agent in the electroplate liquid is 8%~12%.
Optionally, the silicon base is immersed into electroplate liquid and standing containing additive, so that the smoothing agent is located at institute
The opening of groove is stated, the inhibitor is located at the bottom of the groove and the accelerator is located in the through silicon via.
Optionally, first current value is 3~5 amperes, and second current value is 5~8 amperes, the third electric current
Value is 10~15 amperes.
Optionally, the aperture of the through silicon via is greater than 1 μm.Electroplating time under the first current value is 2~6 seconds,
Electroplating time under two current values is 1~2 minute, and the electroplating time under third current value is 3~5 minutes.
It optionally, further include forming gold in the inner wall of the through silicon via and the groove before forming the seed layer
Belong to barrier layer.
Optionally, the seed layer, the first metal layer, the second metal layer and the third metal layer include gold
Belong to copper.
It optionally, further include that planarization process is carried out to the silicon base, exposes non-shape after the formation of third metal layer
At the silicon substrate surface for having the through silicon via and the groove.
TSV electro-plating method provided by the invention, is added additive in electroplate liquid, in silicon base through silicon via and and its
The groove of connection is electroplated, and electroplating process is divided into three phases by adjusting electroplating current, is changed through silicon via and is connected therewith
Metal deposition rates in logical groove, and finally fill up through silicon via and groove, it is not formed at the top of plating metal
The pit of correspondence through silicon via, after removing the mistake electroplated layer for being higher than silicon substrate surface, the available TSV with flat surfaces
Structure.
Detailed description of the invention
Fig. 1 is the photo that existing TSV technique is formed by TSV structure.
Fig. 2 is the flow diagram of TSV electro-plating method of the embodiment of the present invention.
Fig. 3 a to Fig. 3 f is the diagrammatic cross-section of each step of TSV electro-plating method of the embodiment of the present invention.
Fig. 4 is the photo that TSV structure is formed by using the TSV electro-plating method of the embodiment of the present invention.
Description of symbols:
10- pit；
100- silicon base；
110- through silicon via；
120- groove；
101- seed layer；
102- the first metal layer；
103- second metal layer；
104- third metal layer；
130- crosses electroplated layer；
140-TSV structure.
Specific embodiment
At present in the TSV technique of integrated circuit, it usually needs to include small size through silicon via (bottom part aperture diameter about 20~
100nm), the groove above large scale through silicon via (bottom part aperture diameter be greater than 1 μm) and through silicon via is filled, the gold being generally filled with
Category is copper (Cu).But it has been found that using current TSV electro-plating method, especially for large-sized through silicon via, electricity
The surface that TSV structure after the completion of plating is right against through silicon via is formed with pit, and by measuring, the depth of pit can even reach 6
~10 μm, thus it is subsequent not can be removed carrying out CMP process yet, pit 10 as shown in figure 1 is still to remain by CMP process
Pit.The presence of pit 10 will affect the flatness of silicon base, to it is subsequent be routed again (Redistribution Layer,
RDL) layer and semiconductor devices production will cause influence.
A kind of TSV electro-plating method is present embodiments provided, the electroplating process of through silicon via and its groove of top is divided into three
A stage carries out, and is gradually increased in the current range of setting by plating in control three phases, so that being in different location
Additive electroplating velocity is had an impact, from the through silicon via of lower part along the radially upper groove plating filling shape in communication in hole
When at TSV structure, through silicon via is different with the fill rate of groove, finally the electricity right above the top of plating metal, through silicon via
Plating metal tip height is more than or equal to the height of surrounding plating metal, so that pit 10 as shown in Figure 1 is eliminated, it is subsequent
After handling by CMP process, the TSV structure with flat surfaces can be formed.
TSV electro-plating method of the invention is described in further detail below in conjunction with the drawings and specific embodiments.Under
The explanation in face, advantages and features of the invention will become apparent from.It should be noted that attached drawing is all made of very simplified form and makes
With non-accurate ratio, only for the purpose of facilitating and clarifying the purpose of the embodiments of the invention.
The present embodiment is using copper as plating metal, however, the present invention is not limited thereto, in other embodiments of the invention, can be with
Different packing materials is selected according to application purpose difference, such as can also fill tungsten (W) and polysilicon (poly-Si) conduction
Material.
Fig. 2 is the flow diagram of the present embodiment TSV electro-plating method, comprising:
S1: a silicon base, the groove for being formed with through silicon via in the silicon base and being connected to the through silicon via, institute are provided
State the surface that groove is set to the silicon base；
S2: seed layer is formed in the inner wall of the through silicon via and the groove；
S3: immersing the electroplate liquid containing additive for the silicon base, and under conditions of the first current value, plating forms the
One metal layer, the first metal layer cover the seed layer but do not fill up the through silicon via；
S4: under conditions of the second current value, plating forms second metal layer, and the second metal layer covers the first metal
Layer but do not fill up the through silicon via；
S5: under conditions of third current value, plating forms third metal layer, until filling up the through silicon via and the ditch
Slot；Wherein, the first current value is less than third current value less than the second current value, the second current value.
Fig. 3 a to Fig. 3 f is the diagrammatic cross-section of the through silicon via of each step of the present embodiment TSV electro-plating method.Below in conjunction with Fig. 1
And Fig. 3 a to Fig. 3 e is illustrated the present embodiment TSV electro-plating method.
As shown in Fig. 1 and Fig. 3 a, step S1 is executed, a silicon base 100 is provided, is formed with through silicon via in silicon base 100
110, and the groove 120 being connected to through silicon via 110 is also formed in silicon base 100, groove 120 is set to silicon base 100
Surface.
Through silicon via 110 and the forming method of groove 120 can apply method well known to those skilled in the art.For example, can
Through silicon via 110 and groove 120 are formed to be melted in silicon base 100 by etching or laser.In the present embodiment, groove 120
It is set to the surface of silicon base 100, through silicon via 110 in communication is extended a distance up perpendicular to the side of silicon base 100,
But not through silicon base 100.
As shown in Fig. 1 and Fig. 3 b, step S2 is executed, forms seed layer 101 in the inner wall of through silicon via 110 and groove 120.It can
To pass through physical vapour deposition (PVD) (PVD), plasma enhanced chemical vapor deposition (PECVD) or metallo-organic compound chemistry gas
Mutually the techniques such as deposition (MOCVD) deposit seed layer 110 on the inner wall of through silicon via 110 and groove 120.Seed layer in the present embodiment
The material of 101 seed layers 110 includes copper (Cu), and seed layer 101 is in addition to the inner wall of covering through silicon via 110 and groove 120,
Also cover the non-TSV region surface of silicon base 100.
Before deposited seed layer 101, insulating layer (its material can also be formed in the inner wall of through silicon via 110 and groove 120
E.g. silica, SiO2), so that the plating metal and the silicon base 100 that are subsequently formed are kept apart, in addition, in deposition kind
Metal adhesion layers or metal barrier can also be formed in the inner wall of through silicon via 110 and groove 120 before sublayer 101, metal is viscous
Attached layer is, for example, the composite layer of titanium (Ti) and titanium nitride (TiN), and metal barrier is, for example, tantalum (Ta), and metal adhesion layers can be used
In the adhesiveness of enhancing plating metal and silicon base 100, metal barrier is used to that plating metal atom is prevented to seep to silicon base 100
Thoroughly.
As shown in Fig. 1 and Fig. 3 c, step S3 is executed, carries out first stage plating, silicon base 100 is immersed into electroplate liquid,
Under conditions of first current value, plating forms the first metal layer 102, and the first metal layer 102 covers seed layer 101 but do not fill up
Through silicon via 110.
Contain additive in the present embodiment in electroplate liquid, specifically may include smoothing agent L, inhibitor S and accelerator A, wherein
Weight ratio of the smoothing agent L in electroplate liquid be 4%~6%, weight ratio of the inhibitor S in electroplate liquid be 1.5%~
The weight ratio of 3.5%, accelerator A in electroplate liquid is 8%~12%.Wherein, smoothing agent L Preferential adsorption is in groove 120
Apical position (opening), smoothing agent L can inhibit the deposition of high electric field region caused by 100 surface curvature distribution of silicon base,
Inhibit the fast nucleation of prominent surface location；Inhibitor S Preferential adsorption passes through in biggish 120 bottom of groove of electric field ratio
Reduce the current density and deposition rate of the atom site of covered metal surface, come inhibit the metal of 120 bottom of groove from
Son deposition；And accelerator A is adsorbed on 110 bottom of through silicon via, increases the current density of 110 bottom of through silicon via and accelerates through silicon via
The deposition velocity of 110 bottoms, for accelerating the deposition rate of 110 bottom metal ion of through silicon via.
Specifically, can be placed on silicon base 100 in a closed electroplating device, electroplating device includes filling electroplate liquid
Container (or electroplating bath) carries out the container to vacuumize pretreatment first, so that electroplate liquid infiltration through silicon via 110 and groove 120,
Then 10~60 minutes are stood, the to be added dose of inner wall in through silicon via 110 and groove 120 reaches preliminary adsorption equilibrium, then, will
Silicon base 100 and the cathode of electroplating device link together, and are placed in electroplate liquid and as electroplating cathode, followed by opening electricity
The power supply of coating apparatus carries out the deposition reaction of cathodic metal ion.In the present embodiment, plating metal is, for example, copper, in the first electricity
Under conditions of flow valuve, copper ion repairs seed layer 101, and forms the first metal layer 102, and the first metal layer 102 covers
Seed layer 101.
First current value is typically less than the value of 5 amperes (amphere), by being repaired to seed layer 101, protection kind
Sublayer 101 is not plated liquid erosion, and forms the first metal layer 102 in seed layer 110 but do not fill up through silicon via
110.Through silicon via 110 is completely covered in the first metal layer 102 and groove 120 is covered with the inner wall of seed layer 101, in the present embodiment,
About 150~200 angstroms of the thickness of the first metal layer 102In the present embodiment, in first stage electroplating process, the first current value
It is preferred that 3~5 amperes, cathode revolving speed is 90~120 revs/min (rpm) in electroplating process, and the electroplating time under the first current value is about
2~6 seconds (sec), for example, 5.5 seconds.
As shown in Fig. 1 and Fig. 3 d, step S4 is executed, carries out second stage plating, under conditions of the second current value, is formed
Second metal layer 103, second metal layer 103 cover the first metal layer 102.The thickness of second metal layer 103 about 3500~4500
AngstromSecond current value is greater than the first current value, typically larger than or equal to 5 amperes (ampere), and second metal layer
103 are completely covered the first metal layer 102 but do not fill up through silicon via 110.In the present embodiment, the second current value is 5~8 amperes,
Cathode revolving speed remains as 90~120 revs/min, electroplating time about 1~2 minute, preferably from about 90 seconds in second stage electroplating process.
As shown in Fig. 1 and Fig. 3 e, step S5 is executed, phase III plating is carried out, under conditions of third current value, in silicon
Third metal layer 104 is formed in through-hole 110 and groove 120, until filling up through silicon via 110 and groove 120.
In phase III electroplating technology, electroplating device increases electric current to third current value, and the third current value is usual
More than or equal to 10 amperes, so that the metal fill velocity in through silicon via 110 is greater than the metal fill velocity of groove 120, and
Gradually through silicon via 110 is filled up.In the present embodiment, third current value be 10~15 amperes, electroplating time about 3~5 minutes, preferably
About 250 seconds, cathode revolving speed was constant, and remaining as revolving speed is 90~120 revs/min.
In three phases electroplating process, current value gradually increases the present embodiment, and the current value of different phase is to through silicon via
110 is different with the influence degree of groove 120.In phase III electroplating process, the inhibitor for being adsorbed in 120 bottom of groove inhibits
Metal ion deposition in groove 120, and in through silicon via 110, due to the presence of accelerator A, metal ion deposition speed
Degree is greater than the deposition velocity in groove 120, when third current value, which continues to, fills up through silicon via 110, the electricity of 110 top of through silicon via
Metallized surfaces can reach at or above other regions of surrounding, avoid generating pit 1 shown in FIG. 1.
After completing to the above-mentioned electroplating technology of through silicon via 110 and groove 120, electricity was formd on 100 surface of silicon base
Coating 130 crosses electroplated layer 130 and is higher than 100 surface of silicon base, need to remove, crosses the thickness of electroplated layer 130 aboutElectroplated layer 130 can be removed using chemical mechanical grinding (CMP) technique to expose non-TSV region
100 surface of silicon base.CMP process is method well known to those skilled in the art, and details are not described herein again.
After CMP process, as illustrated in figure 3f, TSV structure 140 is formd in through silicon via 110 and groove 120, due to
By step S1~S5, the metal ion deposition speed in phase III electroplating process in through silicon via 110 increases, and groove
Metal ion deposition speed in 120 is less than the metal ion deposition speed in through silicon via 110, so that plating metal is corresponding to
The apparent height of through silicon via 110 can be more than or equal to the height that surrounding corresponds to other regions of groove 120, pass through CMP
After technique, available flat TSV structure surface.
Inventor carries out the mistake of electro-coppering using above-mentioned TSV electro-plating method to the silicon base for being formed with through silicon via and groove
Journey, and after removing electroplated layer by CMP process, it is detected to TSV structure section is formed by, obtained Electronic Speculum is shone
Piece does not have shape in the region that plate metal surfaces correspond to through silicon via as shown in figure 4, being formed by its top flat of TSV structure
At the pit 10 being similar in Fig. 1.
In short, TSV electro-plating method described in the present embodiment, additive is added in electroplate liquid, passes through three phases
Electroplating current adjustment, so that the metal deposition rates in through silicon via 110 and groove 120 in communication is changed, and
Finally through silicon via 110 and groove 120 are filled up, there is no the pit of corresponding through silicon via 110 at the top of plating metal,
After removing electroplated layer, it is flat to be formed by 130 surface of TSV structure.
TSV electro-plating method described in the present embodiment can be used for large scale channel (through silicon via 110 on semiconductor element
Aperture be greater than 1 μm) plating, can be used for the plating of small size channel (110 aperture of through silicon via about 20~100nm), with
When the plating of small size channel, the electroplating time in corresponding stage need to only be reduced.
Foregoing description is only the description to present pre-ferred embodiments, not to any restriction of interest field of the present invention,
Anyone skilled in the art without departing from the spirit and scope of the present invention, may be by the methods and techniques of the disclosure above
Content makes possible variation and modification to technical solution of the present invention, therefore, anything that does not depart from the technical scheme of the invention,
Any simple modifications, equivalents, and modifications to the above embodiments according to the technical essence of the invention, belong to this hair
The protection scope of bright technical solution.
Claims (8)
1. a kind of TSV electro-plating method characterized by comprising
One silicon base, the groove that through silicon via is formed in the silicon base and is connected to the through silicon via, the groove are provided
It is set to the surface of the silicon base；
Seed layer is formed in the inner wall of the through silicon via and the groove；
The silicon base is immersed into the electroplate liquid containing additive, under conditions of the first current value, plating forms the first metal
Layer, the first metal layer cover the seed layer but do not fill up the through silicon via, and the additive includes smoothing agent, inhibits
Agent and accelerator, weight ratio of the smoothing agent in the electroplate liquid are 4%~6%, and the inhibitor is in the plating
Weight ratio in liquid is 1.5%~3.5%, and weight ratio of the accelerator in the electroplate liquid is 8%~12%；
Under conditions of the second current value, plating forms second metal layer, and the second metal layer covers the first metal layer
But the through silicon via is not filled up；And
Under conditions of third current value, metal ion deposition speed in the groove be less than the metal in the through silicon via from
Sub- deposition velocity, plating forms third metal layer, until filling up the through silicon via and the groove；
Wherein, first current value is less than second current value, and second current value is less than the third current value.
2. TSV electro-plating method as described in claim 1, which is characterized in that the silicon base is immersed the electricity containing additive
Plating solution is simultaneously stood so that the smoothing agent is located at the opening of the groove, the inhibitor be located at the bottom of the groove with
And the accelerator is located in the through silicon via.
3. TSV electro-plating method as described in claim 1, which is characterized in that first current value is 3~5 amperes, described the
Two current values are 5~8 amperes, and the third current value is 10~15 amperes.
4. TSV electro-plating method as described in claim 1, which is characterized in that the aperture of the through silicon via is greater than 1 μm.
5. TSV electro-plating method as claimed in claim 4, which is characterized in that the electroplating time under the first current value is 2~6
Second, the electroplating time under the second current value is 1~2 minute, and the electroplating time under third current value is 3~5 minutes.
6. such as TSV electro-plating method described in any one of claim 1 to 5, which is characterized in that before forming the seed layer,
It further include forming metal barrier in the inner wall of the through silicon via and the groove.
7. such as TSV electro-plating method described in any one of claim 1 to 5, which is characterized in that the seed layer, first gold medal
Belonging to layer, the second metal layer and the third metal layer includes metallic copper.
8. such as TSV electro-plating method described in any one of claim 1 to 5, which is characterized in that further include being formed in third metal layer
Later, planarization process is carried out to the silicon base, exposes the silicon substrate surface that the through silicon via and the groove is not formed.
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| CN113363152A (en) * | 2020-03-06 | 2021-09-07 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method thereof |
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