CN103258788B - Based on the through hole interconnect architecture manufacture method and products thereof of two-way filling - Google Patents
Based on the through hole interconnect architecture manufacture method and products thereof of two-way filling Download PDFInfo
- Publication number
- CN103258788B CN103258788B CN201310133768.1A CN201310133768A CN103258788B CN 103258788 B CN103258788 B CN 103258788B CN 201310133768 A CN201310133768 A CN 201310133768A CN 103258788 B CN103258788 B CN 103258788B
- Authority
- CN
- China
- Prior art keywords
- blind hole
- layer
- barrier
- hole
- barrier layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses a kind of through hole interconnect architecture manufacture method based on two-way filling, comprising: (a) processes obtained first blind hole on substrate first surface; B () be deposition insulating layer, barrier layer and Seed Layer on the first surface; C () be obtained second blind hole of alignment processing on a second surface, and its degree of depth terminates in the insulating barrier exposed in the first blind hole; D () be deposition insulating layer and barrier layer on a second surface; E () is tiled and is fitted dry film and perform exposure imaging on the barrier layer of second surface; F (), using dry film as mask, performs etching processing to insulating barrier and barrier layer and only retains Seed Layer; G () performs padding.Corresponding through hole interconnect architecture product is also disclosed in the present invention.By the present invention, so that manipulation, high efficiency mode performs filling process, and obtain the good product of filling effect, can break through the bottleneck of existing film technique simultaneously, widen its range of application, and be particularly suited for the occasion meeting superelevation depth-to-width ratio.
Description
Technical field
The invention belongs to technical field of semiconductor encapsulation, more specifically, relate to a kind of through hole interconnect architecture manufacture method based on two-way filling and products thereof.
Background technology
Since the sixties in 20th century, mole (Moore) law is followed in the development of traditional integrated circuit substantially, and researcher utilizes various technology to meet electron trade chasing Moore's Law.But, along with the continuous reduction of characteristic size, the improving constantly of integrated level, seriously hinder further developing of integrated circuit.In order to improve integrated level, solve the problems such as interconnected delay, simultaneously also in order to meet the requirement of the aspects such as performance, frequency range and power consumption, technical staff develops in vertical direction by the new technology of chip-stack and three-dimensional integration technology, wherein silicon through hole (TSV, Through Silicon Via) technology comes into one's own day by day.So-called silicon through hole technology, being by making vertical conducting between chip and chip, between wafer and wafer, realizing New Scheme interconnected between chip thus.The advantage of TSV technology comprises: wire length is suitable with chip thickness, significantly shortens the average interconnect length between module, and information transmission range on chip is reduced, and the passage of information transmission increases; The connection of high density, high-aspect-ratio can be realized, the complicated multi-disc total silicon system integration can be realized; And significantly can reduce RC delay, reduce noise etc.
One of key of TSV technology is that the filling of through hole realizes signal of telecommunication interconnection.Usually conformal plating or bottom-up plating mode is adopted to perform filling through hole in prior art.Conformal plating mode is sputtering seed layer on through-hole wall, then electroplates; This electro-plating method is owing to being that whole through hole is electroplated in the vertical simultaneously, need special electroplating device, and electroplating velocity is slow, require high to electroplate liquid, thicker at the coating of silicon chip surface, and through hole upper and lower port can be there is first close, cause copper post inside to have hole, the defect such as hollow, reduce electrical property and the sealing of chip simultaneously, affect device lifetime.
Bottom-up plating skill mode is that copper deposits from one end of TSV through hole, upwards grows along through hole, the whole through hole of final filling.Bottom-up electro-plating method generally needs to provide a through hole, adopts auxiliary disk as electroplating cathode, or utilizes the characteristic of plating cross growth at disk one face closure silicon through hole, realizes bottom-up plating thus.Compared with electroplating with conformal, bottom-up plating does not need special installation, and speed is fast, and low to the requirement of electroplate liquid, and the coating of silicon chip surface also can control.But Seed Layer makes the extra processing step of general needs in this mode, as made auxiliary disk, auxiliary disk ephemeral key closes; Or need to carry out Seed Layer filling, plating in advance at the electroplated disk back side.In addition, bottom-up growth pattern due to depositional area limited, efficiency is lower.Correspondingly, along with the continuous reduction of characteristic size, the depth-to-width ratio of through hole increase day by day, challenge be it is also proposed to the film technique on traditional insulating barrier and barrier layer.
Summary of the invention
For above defect or the Improvement requirement of prior art, the invention provides manufacture method of a kind of through hole interconnect architecture and products thereof, its purport is by studying and corresponding adjusting process step the growth mechanism of filling through hole material and process, can so that manipulation, high efficiency mode performs filling process, and obtain the good through hole interconnect architecture product of filling effect, widen the range of application of existing film technique simultaneously.
According to one aspect of the present invention, provide a kind of through hole interconnect architecture manufacture method based on two-way filling, it is characterized in that, the method comprises the following steps:
A () processes obtained first blind hole on the first surface of substrate, and make the degree of depth of this first blind hole be not less than its diameter;
(b) deposition insulating layer, barrier layer and Seed Layer successively on the whole substrate first surface of obtained first blind hole of processing;
C (), by back side overlay alignment, on the second surface that substrate is opposite with first surface, processing obtains the second blind hole; The Working position of this second blind hole is corresponding with the first blind hole, and its degree of depth terminates in the insulating barrier exposed in the first blind hole;
(d) deposition insulating layer and barrier layer successively on the whole substrate second surface of obtained second blind hole of processing;
E () to be tiled laminating photosensitive dry film, is then performed exposure and development treatment to it on the barrier layer of silicon chip second surface, and formed and expose the opening of the second blind hole;
F (), to be formed with the dry film of opening as mask, to perform etching processing respectively to two insulating barriers of first, second blind via bottom and two barrier layers, only retains Seed Layer thus;
G () for guiding, to first, second blind hole filled conductive material simultaneously, obtains required through hole interconnect architecture product with the Seed Layer retained thus.
As further preferably, in step (a) and (c), the degree of depth of described blind hole be silicon chip its thickness 1/3 ~ 1/2 between, and the degree of depth of blind hole is 1 ~ 50 times of its diameter.
As further preferably, in step (a) and (c), process obtained blind hole by deep reaction ion etching, laser ablation or wet etching.
As further preferably, in step (b) and (d), the material of described insulating barrier be selected from the mixture of silicon dioxide, silicon nitride, alundum (Al2O3), polyimides, Parylene, polybenzocyclobutene or photoresist and above-mentioned material or complex and preferably adopt thermal oxidation, the mode of physical vapor deposition or chemical vapor deposition formed; Described barrier layer is titanium barrier layer, titanium-tungsten barrier bi-layer, titanium-titanium nitride barrier bi-layer or tantalum-tantalum nitride barrier bi-layer, and preferably adopts the mode of atomic layer deposition, physical vapor deposition or chemical vapor deposition to be formed.
As further preferably, in step (b), the material of described Seed Layer is copper or gold, and adopts the mode of atomic layer deposition, physical vapor deposition or chemical vapor deposition to be formed.
As further preferably, in step (e), after photosensitive dry film exposure imaging form opening diameter be less than the diameter of the second blind hole, make the second blind hole part expose thus.
As further preferably, in step (e), adopt hot pressing mode the tiling of one or more layers photosensitive dry film to be fitted on described barrier layer, and perform exposure by laser, electron beam or ion beam mode; After exposure heating firmly treatment is performed to dry film, be then soaked in developer solution or by spray developing liquid and perform development treatment.
As further preferably, in step (f), adopt the mode of plasma etching, to two insulating barriers and two barrier layers execution etching processing of first, second blind via bottom.
As further preferably, in step (g), described packing material is selected from copper, gold, silver or its mixture, and usually consistent with the Seed Layer described in step (b).
As further preferably, after step (g), also comprise the step removed dry film, pad, the rerouting of line layer and/or make salient point.
As further preferably, the compound semiconductor such as described substrate is selected from the element semiconductor such as silicon, germanium or GaAs, InP, nitrogenize are sowed.
According to another aspect of the present invention, additionally provide corresponding silicon through hole interconnect architecture product.
In general, according to above technical scheme of the present invention compared with prior art, following technical characterstic is mainly possessed:
1, by studying the growth mechanism of filling through hole material and process, due to portion's deposit Seed Layer in the substrate, and simultaneously performing filling for boot media to silicon through hole two ends with it, the efficiency of such filling through hole will increase substantially, and contribute to realizing high-quality filling effect;
2, by performing etching, Film forming operations on substrate two counter surfaces, the bottleneck of existing film technique can be broken through, make insulating barrier, the coverage rate of barrier layer and Seed Layer doubles, strengthen the depth-to-width ratio of silicon hole simultaneously, and be particularly useful for the application scenario of superelevation depth-to-width ratio;
3, by the opening diameter of dry film is formed as the diameter being less than blind hole, the unsettled dry film at blind hole edge contributes to the electric field reducing blind hole opening part, blind hole opening is not easily deposited, and then strengthens with the effect of Seed Layer in the middle part of silicon chip for guiding, fill to through hole two ends simultaneously further;
4, be convenient to manipulation according to manufacture method of the present invention, filling quality is high, and the manufacture craft efficiency of through hole interconnect architecture can be improved, be thus applicable to large batch of suitability for industrialized production purposes.
Accompanying drawing explanation
Fig. 1 is according to the process flow diagram for making silicon through hole interconnect architecture of the present invention;
Fig. 2 a is for being presented at structural representation substrate first surface being processed the first blind hole;
Fig. 2 b be processed with the first blind hole for being presented at substrate first surface on the structural representation of deposition insulating layer, barrier layer and Seed Layer successively;
Fig. 2 c is for being presented at structural representation substrate second surface being processed the second blind hole;
Fig. 2 d be processed with the second blind hole for being presented at substrate second surface on the structural representation on deposition insulating layer, barrier layer successively;
Fig. 2 e is that photosensitive dry film is sticked on the barrier layer for being presented at second surface, and forms the structural representation of dry film opening;
Fig. 2 f is mask for display with dry film, and perform etching processing at the insulating barrier of the first and second blind via bottom and barrier layer, only retain the structural representation of Seed Layer;
Fig. 2 g performs the structural representation of filling at two ends for showing to through hole.
In all of the figs, identical Reference numeral is used for representing identical element or structure, wherein:
4-Seed Layer 5-insulating barrier 6-barrier layer, 1-substrate 2-insulating barrier 3-barrier layer 7-photosensitive dry film
Embodiment
In order to make object of the present invention, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.
Fig. 1 is according to the process flow diagram for making silicon through hole interconnect architecture of the present invention.As shown in fig. 1, mainly comprise the following steps: according to the through hole interconnect architecture manufacture method based on two-way filling of the present invention
First, shown in Fig. 2 a, obtained one or more first blind hole of the upper processing of first surface (being shown as upper surface in figure) on the substrate 1, and make the degree of depth of blind hole be not less than its diameter.From 1 micron to 1000 microns not etc., its cross section is generally circular or square for the diameter of the first blind hole.The degree of depth of the first blind hole be preferably silicon chip its thickness 1/3 ~ 1/2 between, and the degree of depth of blind hole is 1 ~ 50 times of its diameter.First blind hole can be processed obtained by deep reaction ion etching (DRIE), laser ablation or wet etching.Substrate can select semi-conducting material, as the element semiconductor such as silicon, germanium or GaAs, InP, nitrogenize such as to sow at the compound semiconductor.Two surfaces of substrate can there be the semiconductor device, multilayer electricity interlinkage layer or the micro-sensor structure that complete, pad or passivation layer can also be comprised.
Then, shown in Fig. 2 b, deposition insulating layer 2, barrier layer 3 and Seed Layer 4 successively on the whole substrate surface of obtained first blind hole of processing, be formed with the insulating barrier of layer structure, barrier layer and Seed Layer thus successively at other positions of substrate surface of blind via bottom, blind hole sidewall and undressed blind hole.The material of insulating barrier 2 is selected from mixture or the complex of silicon dioxide, silicon nitride, alundum (Al2O3), polyimides, Parylene, polybenzocyclobutene or photoresist and above-mentioned material, and preferably adopt thermal oxidation, the mode of physical vapor deposition (PVD) or chemical vapor deposition (CVD) formed.Barrier layer 3 is titanium barrier layer, titanium-tungsten (Ti-W) barrier bi-layer, titanium-titanium nitride (Ti-TiN) barrier bi-layer or tantalum-tantalum nitride (Ta-TaN) barrier bi-layer, and preferably adopts the modes such as atomic layer deposition (ALD), physical vapor deposition (PVD) or chemical vapor deposition (CVD) to be formed.
Then, as illustrated in fig. 2 c, the second surface that substrate is opposite with first surface carries out alignment.The Working position of this second blind hole is corresponding with the first blind hole, and its degree of depth terminates in insulating barrier 2 place in the first blind hole, namely exposes the insulating barrier 2 that on substrate first surface, the deposit of the first blind via bottom institute is formed.The processing mode of the second blind hole can be identical with the processing mode of the first blind hole.
Then, as shown in fig. 2d, deposition insulating layer 5 and barrier layer 6 successively on the whole substrate second surface of obtained second blind hole of processing, the generation type on insulating barrier 5 and barrier layer 6 and Material selec-tion can identical with on first surface.
Then, as shown in figure 2e, along horizontal direction tiling laminating photosensitive dry film on the surface on the barrier layer 6 of silicon chip second surface, then exposure and development treatment are performed to it, form the opening exposing the second blind hole thus.Dry film is affixed on on-chip by the mode of hot pressing, can paste one or more layers.Dry film is photo-sensitive characteristic, can be negative photoresist or positive photoresist.Expose with specific equipment as mask aligner, or perform with laser, electron beam or ion beam.After exposure, preferably can select to heat by hot plate, baking oven or infrared mode to be affixed on on-chip dry film, carry out post bake step to improve photoetching quality.Development refers to and is soaked in developer solution by the substrate 1 posting dry film, or passes through the method for spray developing liquid, removes a part of dry film, the figure needed for formation.
According to a preferred embodiment of the present invention, in above-mentioned steps, after dry film exposure imaging form opening diameter be set to be less than the diameter of the second blind hole, make the second blind hole part expose thus.In other words, as shown in figure 2e, around blind hole opening, some dry film is vacant state.In this way, because the opening in dry film photoetching is less than the size of blind hole, the unsettled dry film at blind hole edge contributes to the electric field reducing blind hole opening part, makes blind hole opening part not easily be plated deposition, and then can strengthen the effect of bottom-up filling further.
Then, as shown in Fig. 2 f, to be formed with the dry film of opening as mask, preferably to adopt the method for plasma etching to come to perform etching processing to the insulating barrier of two in first, second blind hole 2,5 and two barrier layers 3,6, only retain Seed Layer 4 thus.In addition, can, according to the character of insulating barrier 2, barrier layer 3, insulating barrier 5 and barrier layer 6 material, corresponding etching atmosphere be selected to etch.
Finally, shown in Fig. 2 g, with the Seed Layer 4 retained for guiding, performing to first, second blind hole simultaneously and filling until fill up electric conducting material, being able to high efficiency thus, obtaining required through hole interconnect architecture product in high quality.Filling is generally adopt electric plating method, also can use the method for chemical plating, or the two is combined.The material of filling is generally copper, also can be the mixture of the materials such as gold, silver or other metals, alloy.
In sum, portion's deposit Seed Layer in the substrate in the present invention, and simultaneously perform filling for boot media to silicon through hole two ends with it, the efficiency of such filling through hole will increase substantially, and contribute to realizing high-quality filling effect; In addition, owing to performing etching, Film forming operations on substrate two counter surfaces, the bottleneck of existing film technique can be broken through, make insulating barrier, the coverage rate of barrier layer and Seed Layer doubles, strengthen the depth-to-width ratio of silicon hole simultaneously, and be particularly useful for the application scenario of superelevation depth-to-width ratio.Correspondingly, be convenient to manipulation according to manufacture method of the present invention, filling quality is high, and the manufacture craft efficiency of through hole interconnect architecture can be improved, be thus applicable to large batch of suitability for industrialized production purposes.
Those skilled in the art will readily understand; the foregoing is only preferred embodiment of the present invention; not in order to limit the present invention, all any amendments done within the spirit and principles in the present invention, equivalent replacement and improvement etc., all should be included within protection scope of the present invention.
Claims (4)
1., based on a semiconductor through hole interconnect architecture manufacture method for two-way filling, it is characterized in that, the method comprises the following steps:
A () processes obtained first blind hole on the upper surface of substrate (1), and make the degree of depth of this first blind hole be not less than its diameter, the material of wherein said substrate (1) is selected from silicon, germanium, GaAs or gallium nitride, the diameter of described first blind hole is from 1 micron to 1000 microns, and cross section is circular or square; In addition, the degree of depth of this first blind hole is 1/3 ~ 1/2 of described substrate (1) its thickness, and the degree of depth of this first blind hole is 1 ~ 50 times of himself diameter;
(b) deposit first insulating barrier, the first barrier layer and Seed Layer successively on the whole substrate upper surface of obtained described first blind hole of processing, thus in the bottom of this first blind hole, the sidewall of this first blind hole and other positions of substrate upper surface of this first blind hole undressed are formed with described first insulating barrier (2), the first barrier layer (3) and the Seed Layer (4) of layer structure successively; The material of wherein said first insulating barrier (2) is selected from silicon dioxide, silicon nitride, alundum (Al2O3), polyimides, Parylene or polybenzocyclobutene, and described first barrier layer (3) is titanium barrier layer, titanium-tungsten barrier bi-layer, titanium-titanium nitride barrier bi-layer or tantalum-tantalum nitride barrier bi-layer; The material of described Seed Layer (4) is copper or gold;
C (), by back side overlay alignment, on the lower surface that described substrate (1) is opposite with upper surface, processing obtains the second blind hole; The Working position of this second blind hole is corresponding with described first blind hole, and its degree of depth terminates in described first insulating barrier (2) of exposing the first blind via bottom institute deposit formation on substrate upper surface;
(d) deposit second insulating barrier (5) and the second barrier layer (6) successively on the whole substrate lower surface of obtained described second blind hole of processing, and this second insulating barrier is all corresponding identical with the first barrier layer (3) with described first insulating barrier (2) with the material on the second barrier layer;
E () is on the surface of described second barrier layer (6) of silicon chip lower surface, adopt the mode of hot pressing along horizontal direction tiling laminating photosensitive dry film (7), then exposure and development treatment are performed to it, and to make after exposure imaging form opening diameter be less than the diameter of described second blind hole, described second blind hole part is made to expose thus, also, namely around the second blind hole opening, photosensitive dry film described in some (7) is in vacant state; Then, hot plate, baking oven or infrared mode is adopted to perform firmly treatment to described photosensitive dry film after exposure;
F () is to be formed with the described photosensitive dry film (7) of opening as mask, adopt the mode of plasma etching simultaneously to described first blind hole and the second blind hole separately bottom insulating barrier and barrier layer perform etching processing respectively, only retain described Seed Layer (4) thus; For described second blind hole, its bottom and the bottom of described first blind hole share be retained in the first blind via bottom a part described in Seed Layer (4), and described second barrier layer (6) being in the second blind hole sidewall does not have Seed Layer to cover;
G (), to be retained in Seed Layer in described first blind hole for guiding, to described first blind hole and the second blind hole filled conductive material simultaneously, obtains required through hole interconnect architecture product thus.
2. the method for claim 1, is characterized in that, in step (a) and (c), processes obtained described first blind hole and the second blind hole by deep reaction ion etching, laser ablation or wet etching.
3. the method for claim 1, is characterized in that, in step (b), the mode of the employing atomic layer deposition of described Seed Layer, physical vapor deposition or chemical vapor deposition is formed.
4. the method for claim 1, is characterized in that, after step (g), also comprises the step removed dry film, pad, the rerouting of line layer and/or make salient point.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310133768.1A CN103258788B (en) | 2013-04-17 | 2013-04-17 | Based on the through hole interconnect architecture manufacture method and products thereof of two-way filling |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310133768.1A CN103258788B (en) | 2013-04-17 | 2013-04-17 | Based on the through hole interconnect architecture manufacture method and products thereof of two-way filling |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103258788A CN103258788A (en) | 2013-08-21 |
| CN103258788B true CN103258788B (en) | 2015-09-23 |
Family
ID=48962612
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310133768.1A Expired - Fee Related CN103258788B (en) | 2013-04-17 | 2013-04-17 | Based on the through hole interconnect architecture manufacture method and products thereof of two-way filling |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103258788B (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103985647B (en) * | 2014-05-22 | 2017-02-01 | 中国科学院微电子研究所 | Method for preparing copper cylinder salient points |
| CN105261569A (en) * | 2015-09-02 | 2016-01-20 | 业成光电（深圳）有限公司 | Manufacturing method for blind hole of insulating substrate for electronic apparatus |
| CN108364912B (en) * | 2018-03-12 | 2020-03-17 | 成都海威华芯科技有限公司 | Plane cascade semiconductor chip device and cascade method |
| CN110854065A (en) * | 2019-11-27 | 2020-02-28 | 西安电子科技大学 | Preparation method of TSV (through silicon Via) with high depth-to-width ratio |
| CN111599749B (en) * | 2020-06-01 | 2022-06-24 | 联合微电子中心有限责任公司 | High-depth-width-ratio through type TSV structure, preparation method thereof and silicon adapter plate |
| CN113161289B (en) * | 2021-04-22 | 2023-05-12 | 浙江集迈科微电子有限公司 | Electroplating process of TSV metal column with high depth-to-width ratio |
| CN113967487B (en) * | 2021-10-11 | 2022-12-02 | 华中科技大学 | Nozzle, liquid drop photo-thermal control system and application thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102130042A (en) * | 2010-12-14 | 2011-07-20 | 北京大学 | Method for manufacturing through hole interconnection structure |
| CN102275867A (en) * | 2011-07-12 | 2011-12-14 | 上海先进半导体制造股份有限公司 | Semiconductor device with partially sealed shell and manufacturing method of semiconductor device |
| CN102683308A (en) * | 2011-03-11 | 2012-09-19 | 中国科学院微电子研究所 | Through-silicon-vias structure and formation method thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20100065785A (en) * | 2008-12-08 | 2010-06-17 | 삼성전자주식회사 | A method of chip interconnection using a capillary motion |
-
2013
- 2013-04-17 CN CN201310133768.1A patent/CN103258788B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102130042A (en) * | 2010-12-14 | 2011-07-20 | 北京大学 | Method for manufacturing through hole interconnection structure |
| CN102683308A (en) * | 2011-03-11 | 2012-09-19 | 中国科学院微电子研究所 | Through-silicon-vias structure and formation method thereof |
| CN102275867A (en) * | 2011-07-12 | 2011-12-14 | 上海先进半导体制造股份有限公司 | Semiconductor device with partially sealed shell and manufacturing method of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103258788A (en) | 2013-08-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103258788B (en) | Based on the through hole interconnect architecture manufacture method and products thereof of two-way filling | |
| CN102130042B (en) | Method for manufacturing through hole interconnection structure | |
| CN103258789A (en) | Manufacturing method of through hole interconnection structure and product of through hole interconnection structure | |
| US9324669B2 (en) | Use of electrolytic plating to control solder wetting | |
| CN103681390B (en) | A kind of wafer scale silicon substrate preparation method based on TSV technique | |
| US8455357B2 (en) | Method of plating through wafer vias in a wafer for 3D packaging | |
| CN102364671B (en) | Method for manufacturing silicon through hole | |
| CN102376689A (en) | Through silicon hole structure with step and manufacture process of through silicon hole | |
| JP2004186187A (en) | Semiconductor device and its fabricating process | |
| SE1250374A1 (en) | CTE-adapted interposer and method of manufacturing one | |
| US20120190188A1 (en) | Method for filling a gap | |
| CN102263192A (en) | Light-emitting diode submount, light-emitting diode package, and fabrication method thereof | |
| CN106252241B (en) | The manufacture craft of chip package side wall pad or salient point | |
| CN104952789A (en) | Manufacturing method of adapter plate comprising high-aspect-ratio TSV (through silicon vias) | |
| CN103325700B (en) | A kind ofly realize interconnected method of through hole and products thereof by bottom-up filling | |
| CN109786355A (en) | Galvanic metallization structure | |
| CN103887231B (en) | Self-alignment technology for leak holes and dielectric layer on back of TSV and TSV | |
| JP2001217248A (en) | Method for forming wiring of semiconductor device | |
| CN106206535A (en) | Semiconductor device and the manufacture method of semiconductor device | |
| CN112466846B (en) | TSV structure and preparation method thereof | |
| WO2014067288A1 (en) | Wafer-level through silicon via (tsv) manufacturing method | |
| CN102376629B (en) | Method for realizing through-silicon-via interconnection by suspension photoresist | |
| JP2014078720A (en) | Manufacturing method of through electrode substrate | |
| CN105070698A (en) | Wafer-level tin soldering dimpling point and manufacturing method thereof | |
| CN115312451A (en) | Perforation of superconducting substrates |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20150923 Termination date: 20160417 |