WO2014067288A1

WO2014067288A1 - Wafer-level through silicon via (tsv) manufacturing method

Info

Publication number: WO2014067288A1
Application number: PCT/CN2013/077029
Authority: WO
Inventors: 陈骁; 罗乐; 徐高卫
Original assignee: 中国科学院上海微系统与信息技术研究所
Priority date: 2012-10-30
Filing date: 2013-06-09
Publication date: 2014-05-08
Also published as: CN102903673A

Abstract

A wafer-level through silicon via (TSV) manufacturing method: firstly depositing a silicon oxide insulation layer (102) on the front and back faces of a silicon wafer (101), then forming a TSV pattern on a photoresist (103) on the front and back faces, and transferring the TSV pattern onto the silicon wafer (101); conducting wet etching until a TSV (105) is formed; subsequently, conducting wet etching to remove the oxide layers on both faces of the silicon wafer; using a thermal oxidation process to re-deposit a silicon oxide insulation layer (106) on the front and back faces of the silicon wafer and the side wall of the TSV at the same time; using a magnetron sputtering process to deposit a metal layer TiW/Au (107, 108) on both faces of the silicon wafer; and then using a silicon wafer double-face electroplating process to cover the entire TSV with metal layers to realize double-face conduction. Compared with the technique for interconnecting TSVs having a dry-etched vertical side wall, the present technique has the key advantages of good reliability, high yield and the like, and greatly facilitates subsequent film deposition and electroplating deposition owing to the sloped wet-etched TSV side wall, thus being simple in operation, low in cost and suitable for industrial production.

Description

Wafer-level through-silicon via TSV manufacturing method

Technical field

The invention relates to a wafer-level manufacturing process for fabricating TSV by a wet etching process, which belongs to the field of high-density three-dimensional electronic packaging. Background technique

In order to meet the needs of the development of very large scale integrated circuits (VLSI), novel 3D stacked package technology emerged. It integrates different performance chips and multiple technologies into a single package with minimal size and lightest weight, by creating vertical electrical conduction between the chip and the chip, between the wafer and the wafer. The latest package interconnection technology for interconnecting chips is different from previous IC package bonding and bump overlay technology, which uses TSV (through silicon via) instead of 2D. The CU interconnect enables the chip to be stacked in the three-dimensional direction with the highest density, smallest form factor, and greatly improved chip speed and low power consumption. Therefore, Dr. Tang Heming, General Manager of R&D Center of ASE Group, called TSV the fourth generation after Wire Bonding, TAB and Flip Chip at the Chartered 2007 Technical Symposium. Packaging technology.

The key technology in the 3D package is TSV, which is used to connect the vias on the upper and lower sides of the silicon wafer, and fill the conductors in the vias to form interconnects. In the process of making TSV, TSV with vertical sidewalls in the deep hole is the focus of current research. Because the TSV of vertical shape can be controlled very small due to its size, it can realize the 3D high integration interconnection of fine pitch. However, the TSV fabrication process of the vertical topography is extremely complicated, especially the dry etching forms a vertical deep hole, the PVD realizes continuous uniform coverage of the deep hole sidewall and the bottom seed layer, and the rapid plating realizes the defect-free filling of the deep hole. And the subsequent TSV wafer flattening process is difficult to achieve in traditional microelectronics process, and the reliability is low and the cost is high. This is the key to the current application of TSV technology. Summary of the invention

In view of the above disadvantages of the prior art, an object of the present invention is to provide a method for fabricating a wafer-level through-silicon via TSV, which is used to solve the problem in the prior art that the dry etching technique is expensive and extremely difficult to manufacture. The problem.

To achieve the above and other related objects, the present invention adopts the following technical solutions: A method for fabricating a wafer-level through-silicon via TSV, the method comprising the following steps:

1) providing a silicon wafer;

2) depositing a first silicon oxide insulating layer on both sides of the silicon wafer;

3) forming a TSV pattern on both sides of the structure formed in step 2), the TSV patterns corresponding to each other; 4) using a photoresist as a mask, wet etching a portion of the first silicon oxide insulating layer to expose the silicon wafer;

5) immersing the photoresist wafer after immersing in the etching solution, and simultaneously performing wet etching on the front and back sides of the silicon wafer until a through silicon via TSV is formed;

6) wet etching off the first silicon oxide insulating layer on both sides of the silicon wafer;

7) depositing a second insulating layer of silicon dioxide on both sides of the silicon wafer and the sidewall of the through-silicon via TSV;

8) depositing an adhesion/seed layer on the front and back sides of the silicon wafer on which the silicon dioxide insulating layer is deposited and the sidewalls of the through-silicon via TSV; so that the two adhesion/seed layers are in contact to realize the through-silicon via TSV Pass

9) etching a partial adhesion/seed layer on both sides of the silicon wafer to expose the second silicon oxide insulating layer;

10) Install the chip on the first silicon dioxide insulating layer exposed after step 9), and connect the two sides by wire bonding or flip chip bonding.

Preferably, the thickness of the first silicon oxide insulating layer in the step 2) is 1 to 2 um.

5微米。 The thickness of the photoresist in step 4) is 1. 2-1. 7um.

Preferably, the etching solution in the step 5) is a K0H solution having a temperature of 50 ° C and a K0H concentration of 40 wt%. Preferably, the through silicon via TSV formed in the step 5) is an inverted trapezoid which is symmetrical in the upper and lower directions.

Preferably, the thickness of the second silicon oxide insulating layer in the step 7) is 1 to 2 μm.

Preferably, the adhesion/seed layer in the step 8) is TiW/Au, wherein the adhesion layer TiW has a thickness of 100 nm to 200 nm; and the seed layer Au has a thickness of 200 nm to 300 nm.

The manufacturing process of the present invention can realize a highly integrated package interconnection, which has the key advantages of high reliability and high yield compared with the dry etched vertical sidewall topography TSV interconnection technology, and The TSV sidewall morphology of the wet etching is sloped, which is very favorable for subsequent film deposition and electroplating deposition. Therefore, the process is extremely simple and low in cost, and is suitable for industrial production. DRAWINGS

Fig. 1 is a cross-sectional structural view showing a silicon wafer in which Si0 _{2 is used} as an insulating layer and a photoresist is used as a mask in the present invention.

Fig. 2 is a view showing the cross-sectional structure of the silicon wafer after the completion of B0E in the present invention.

Fig. 3 is a view showing the cross-sectional structure of a silicon wafer obtained by performing K0H wet etching to obtain TSV in the present invention.

Fig. 4 is a view showing the cross-sectional structure of a silicon wafer after thermal oxidation and metal deposition in the present invention.

Fig. 5 is a view showing the cross-sectional structure of the silicon wafer after the plating is completed in the present invention.

6 is a cross-sectional structural view of a silicon substrate after double-sided interconnection of the substrate after the Ion-beam etching in the present invention. Component label description

Wafer 101

First silicon oxide insulating layer 102

Second silicon dioxide insulating layer 106

Photoresist 103

Window 104

Through silicon vias 105

TiW layer 107

Au layer 108

Photoresist pattern 109

Heart thrust 111, 112

The embodiments of the present invention are described below by way of specific specific examples, and those skilled in the art can readily understand other advantages and effects of the present invention from the disclosure of the present disclosure. The invention may be practiced or applied in various other specific embodiments, and the details of the invention may be variously modified or changed without departing from the spirit and scope of the invention.

Please refer to the attached figure. It should be noted that the illustrations provided in this embodiment merely illustrate the basic concept of the present invention in a schematic manner, and only the components related to the present invention are shown in the drawings, instead of the number and shape of components in actual implementation. Dimensional drawing, the actual type of implementation of each component's type, number and proportion can be a random change, and its component layout can be more complicated.

In order to fully embody the advantages and positive effects of the present invention, the present invention will be further described with reference to the accompanying drawings and embodiments.

Step 1, as shown in Figure 1, a conventional silicon wafer 101 (resistivity 1_10 Ohm * cm) with a 4 inch 450 um thick N < 100 Å crystal orientation is used as a substrate for thermal oxidation on both sides of the silicon wafer. - 2 um oxide layer 102. Then, a double-sided lithography process is performed on the silicon wafer, and TSV patterns are respectively formed on the front and back photoresist 103 of the silicon wafer by photolithography, and the TSV patterns on the front and back sides of the silicon wafer are mutually corresponding and completely coincident.

Step 2, which is shown in FIG. 2, using the photoresist 103 provided with the window 104 as a mask, etching the oxide layer 102 with an oxide etch buffer (B0E) to expose bare silicon, and transferring the TSV pattern to bare silicon. on.

Step 3, please refer to Figure 3, the photoresist mask on both sides of the silicon wafer by the wet stripping process (concentrated sulfuric acid) Remove 103, and rinse dry. The silicon wafer was immersed in a 40% K0H solution at 50 ° C, and wet etching was simultaneously performed on both the front and back sides of the silicon wafer 101 until the through silicon vias 105 were formed. Due to the double-sided etching of the silicon wafer, the TSV exhibits an inverted trapezoidal shape in two directions.

Step 4, Referring to Figure 4, the oxide layer 102 on both sides of the silicon wafer is etched away with an oxide etch buffer (B0E). A thermal oxidation process is again used to simultaneously deposit an oxide layer 106 of 1_2 um on both the front and back sides of the wafer and the TSV sidewall. Then, an adhesion layer TiW 107 (thickness: 100-200 nm) and a seed layer Au 108 (thickness: 200-300 nm) are deposited on the front and back sides of the silicon wafer 101 by magnetron sputtering. Since the TSV topography exhibits an inverted trapezoidal shape in two directions, the adhesion/seed layer is deposited on both sides of the silicon wafer, and the entire TSV is completely covered by the adhesion/seed layer to achieve double-sided conduction.

Step 5, as shown in FIG. 5, respectively, a photoresist process is performed on the front and back sides of the silicon wafer 101, and the photoresist is patterned to have a thickness of 7 to 9 urn, and the photoresist pattern 109 formed by photolithography is used as a plating mask.

Step 6, as shown in FIG. 6, after the electroplating, the photoresist mask 109 is wet-removed, and the seed layer TiW/Au 107 under the photoresist mask is etched away by an ion beam (I-beam). And 108, the oxide layer 106 is exposed. After dicing, the chips 111 and 112 are mounted on the front and back sides of each of the silicon substrates, and the double-sided interconnection of the silicon substrates is achieved by wire bonding or flip chip bonding. This step is common knowledge in the art and will not be described here.

The invention firstly deposits a silicon oxide insulating layer on both sides of the silicon wafer by thermal oxidation, and then performs double-sided lithography on the silicon wafer, and lithographically separates the photoresist on the front and back sides of the silicon wafer. The TSV pattern is formed, and the TSV patterns on both sides of the wafer are mutually corresponding and completely coincident. Using a photoresist as a mask, the oxide layer is wet etched to expose bare silicon, that is, the TSV pattern is transferred to bare silicon. After the silicon wafer is removed, the silicon wafer is immersed in the K0H solution, and the silicon-on-silicon via holes are formed by simultaneously performing wet etching on both the front and back sides of the silicon wafer. Since K0H is isotropic double-sided wet etching on the silicon wafer, the corroded TSV exhibits an inverted trapezoidal shape in two directions. Subsequently, the oxide layer on both sides of the silicon wafer is wet etched off. A thermal oxidation process is again used to deposit a layer of silicon oxide on both the front and back sides of the wafer and the TSV sidewalls. A metal layer TiW/Au is deposited on one side of the silicon wafer by a magnetron sputtering process. On the other side of the silicon wafer, a metal layer TiW/Au is also deposited by a sputtering process. Since the TSV morphology exhibits an inverted trapezoidal shape in two directions, the metal layer is deposited on both sides of the silicon wafer, and the entire TSV is completely covered by the metal layer to achieve double-sided conduction. A photoresist pattern is formed on the front and back sides of the silicon wafer, and a photoresist pattern formed by photolithography is used as a plating mask. The silicon wafer double-sided plating process is used, and both the front and back sides of the silicon wafer and the TSV sidewall are plated. After the electroplating is completed, the glue is removed, and the seed layer TiW/Au of the portion under the previous photoresist mask is etched away by an ion beam (I-beam) to expose the oxide layer. After dicing, the chip is mounted on the front and back of each die, and the double-sided interconnection on the substrate is achieved by a wire bonding or flip chip bonding process.

Advantageous Effects of the Invention: The manufacturing process can realize highly integrated package interconnections, and vertical sidewalls of dry etching Compared with the TSV interconnect technology, the technology has the key advantages of high reliability and high yield, and the TSV sidewall morphology is wet-etched, which is very favorable for subsequent film deposition and plating. Deposition, so the process operation is extremely simple, low cost, suitable for industrial production.

In summary, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

The above-described embodiments are merely illustrative of the principles of the invention and its advantages, and are not intended to limit the invention. Modifications or variations of the above-described embodiments may be made by those skilled in the art without departing from the spirit and scope of the invention. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and scope of the inventions are still to be covered by the appended claims.

Claims

Claim

A method for fabricating a wafer-level through-silicon via TSV, the method comprising the steps of:

1) providing a silicon wafer;

3) forming a TSV pattern on both sides of the structure formed in step 2), the TSV patterns corresponding to each other;

4) using a photoresist as a mask, wet etching a portion of the first silicon oxide insulating layer to expose the silicon wafer;

5) immersing the photoresist wafer after immersing in the etching solution, by simultaneously performing wet etching on the front and back sides of the silicon wafer until a through silicon via TSV is formed;

8) then depositing an adhesion/seed layer on the front and back sides of the silicon wafer on which the silicon dioxide insulating layer is deposited and the sidewalls of the through-silicon via TSV; so that the two adhesion/seed layers are in contact to realize the through-silicon via TSV Pass

The method of fabricating a wafer-level through-silicon via TSV according to claim 1, wherein the thickness of the first silicon oxide insulating layer in the step 2) is 1 to 2 μm.

The thickness of the photoresist in the step 4) is 1. 2-1. 7 um, the thickness of the photoresist in the step 4).

The method for manufacturing a wafer-level through-silicon via TSV according to claim 1, wherein the etching solution in the step 5) is a K0H solution, the temperature is 50 ° C, and the K0H concentration is 40 wt %. .

The method for fabricating a wafer-level through-silicon via TSV according to claim 1, wherein the through-silicon via TSV formed in the step 5) is an inverted trapezoid in which the upper and lower directions are symmetrical.

The method of fabricating a wafer-level through-silicon via TSV according to claim 1, wherein the thickness of the silicon dioxide insulating layer in the step 7) is 1 to 2 μm.

The method for fabricating a wafer-level through-silicon via TSV according to claim 1, wherein the adhesion/seed layer in the step 8) is TiW/Au, wherein the adhesion layer TiW has a thickness of 100 nm. ~200nm _; the thickness of the seed layer Au is 200-300nm.