CN105679701B - A kind of method of high-efficiency electroplating filling silicon substrate TSV - Google Patents
A kind of method of high-efficiency electroplating filling silicon substrate TSV Download PDFInfo
- Publication number
- CN105679701B CN105679701B CN201610030998.9A CN201610030998A CN105679701B CN 105679701 B CN105679701 B CN 105679701B CN 201610030998 A CN201610030998 A CN 201610030998A CN 105679701 B CN105679701 B CN 105679701B
- Authority
- CN
- China
- Prior art keywords
- tsv
- wafer
- seed layer
- silicon substrate
- filling silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
Abstract
A kind of method that the present invention discloses high-efficiency electroplating filling silicon substrate TSV, specifically: the etching preparation TSV on wafer；Insulating layer is prepared on the wafer of etching TSV；Seed layer is prepared on the wafer containing insulating layer；Then in wafer Double-face adhesive dry film, single side photoetching, development；Remove the seed layer at TSV wall port position；Dry film, another side photoetching development are pasted in patterned one side；The seed layer at another port position is removed again；Again by photoetching, development；Then bi-directional synchronization plating filling copper, is integrally formed TSV-Cu and TSV-pad without separating interface；Remove dry film photoresist, seed layer.TSV through hole plating fill process is converted two class blind hole plating fill process by the present invention, TSV structure is firmly combined and technique is more flexible, conveniently, high-aspect-ratio TSV through hole plating filling difficulty is greatly reduced, while effectively improving rate of deposition, makes it possible that low-cost high-efficiency prepares TSV.
Description
Technical field
The present invention relates to microelectronics Packaging fields, and in particular, to one kind is based on the efficient fill method of through-hole, i.e., by through-hole
Centre is divided into the method that two blind holes carry out bi-directional synchronization plating filling TSV, and this method is suitable for the low-cost high-efficiency of silicon substrate TSV
Rate filling preparation.
Background technique
With the rapid development of semi-conductor industry, miniaturization, the multifunctional integrated requirement of micro-system are increasingly urgent to,
Have many advantages, such as that high speed interconnection, High Density Integration, miniaturization and homogeneity and heterogeneous function integrate the three-dimension packaging of through silicon via
(3D-TSV), gradually as popular one of the research of semiconductor packaging.Although 3D-TSV encapsulation technology has many excellent
Gesture, but there are still the development that some unfavorable factors restrict 3D-TSV integrated packaging technology at present.Specifically include: preparation process is numerous
It is trivial, complicated, thermomechanical integrity problem, electrical property reliability caused by missing, the power density of design software and method increase
Problem, critical process and plant issue and system testing problem etc..Wherein, 3D-TSV encapsulates the key process technology packet being related to
It includes: etching, zero defect high-aspect-ratio TSV plating filling technique, wafer thinning technique, multilayer alignment and the key of high-aspect-ratio TSV
Conjunction technology etc..These techniques are still immature, to constrain the application and development of 3D-TSV encapsulation technology.
The thermomechanical reliability and electrical property reliability of 3D-TSV encapsulation technology are that the technology realizes batch production
Huge challenge.Caused by the failure mode of 3D-TSV encapsulation technology is mainly thermomechanical load, failure, TSV sheet including solder joint
Layering, removing and crackle etc. between the failure of body, the rupture of chip and fatigue failure, device interfaces.No matter first via process also
It is rear via process, Cu-TSV and TSV-pad are that substep is completed in conventional process.It is natural between Cu-TSV and TSV-pad
There are the residual stress and thermal stress between interface, and TSV filling is blind hole filling, and the wafer carried out after the completion of being electroplated is thinned
Equal subsequent techniques but will lead to the accumulation of residual stress, warpage, directly affect the thermo mechanical stability and electrical property of TSV.With this
Meanwhile traditional TSV through hole filling is because of the higher no holes filling relatively difficult to achieve of control difficulty of deep hole end rate of deposition.
Summary of the invention
For the shortcomings that filling TSV in above-mentioned traditional handicraft or problem, the present invention propose a kind of high-efficiency electroplating filling silicon substrate
The method of TSV.
To achieve the above object, the present invention is implemented with the following technical solutions: the etching preparation TSV first on wafer；It connects
Etching TSV wafer on prepare insulating layer；Secondly seed layer is prepared on the wafer containing insulating layer；Then double in wafer
Face paste dry film, single side photoetching, development；The seed layer at TSV wall port position is removed again；Then it is pasted in patterned one side
Dry film, another side photoetching development；The seed layer at another port position is removed again；Then again by photoetching, development；Then double
Filling copper is electroplated to synchronous, is integrally formed TSV-Cu and TSV-pad without separating interface；Finally remove dry film photoresist, seed
Layer.This method is removed the Some seeds layer of TSV deep hole side wall two-end part by graphical in advance and control etching, avoids electricity
Copper facing is sealed at first at the both ends of through-hole, and through-hole filling is changed into the filling of bi-directional synchronization class blind hole.The process greatly reduces
The difficulty of through-hole TSV filling, improves no holes filling yield, increases fill rate；Save that wafer is thinned, wafer takes simultaneously
It the processes such as holds, enhances the reliability of 3D-TSV encapsulation.
Specifically, a kind of method of high-efficiency electroplating filling silicon substrate TSV, the described method comprises the following steps:
1) spin coating positive photoresist or negtive photoresist on wafer, drying glue carry out photoetching and development to the wafer for having dried glue；
2) deep ion lithographic technique or laser technology are used, etches TSV on the wafer by step 1) processing；
3) high-temperature oxydation or chemical deposition technique are used, carry out thermal oxide in the crystal column surface by step 2) processing or is sunk
Product insulating layer；
4) in the crystal column surface by step 3) processing, seed layer is prepared；
5) photoetching, development are being carried out by step 4 treated crystal column surface double faced adhesive dry film photoresist, then single side；
6) it will carry out TSV side wall Single port position by the patterned wafer of step 5) processing and go seed layer；
7)) dry film will be pasted again in patterned one side by the wafer of step 6) processing, and another side carries out light
It carves, development；
8) TSV side wall another port position will be carried out by step 7) treated wafer go seed layer；
It 9) will be by step 8) treated wafer photolithography, development；
10) TSV-Cu and TSV- will be realized using electroplating technology filling silicon through holes by step 9) treated wafer
Pad is integrally formed；
11) it by the TSV-Cu prepared in step 10) and the integrally formed wafer of TSV-pad, is gone with sodium hydroxide solution
Dry film is simultaneously cleaned with deionized water, is removed seed layer using the mixed liquor of ammonium hydroxide and hydrogen peroxide and is cleaned with deionized water, is prepared
Integrally formed TSV-Cu and TSV-pad.
Preferably, when executing the step 1), 10 μm~50 μm of spin coating positive photoresist or 10 μm~50 μm of negtive photoresist on wafer.
Preferably, when executing the step 2), the TSV that depth-to-width ratio is 2~50 is etched on wafer.
Preferably, when executing the step 3), the insulating layer of thermal oxide or deposition with a thickness of 0.1 μm~2 μm.
Preferably, when executing the step 4), seed layer can may be implemented to stop electricity using double-faced sputter or deposition
Son diffusion, the barrier layer migrated and the seed layer for conducting function, but be not limited to sputter or deposit, seed layer includes but is not limited to
Ti/Cu, implementation method are also not necessarily limited to sputtering, deposition.
Preferably, it when executing the step 5), pastes dry film photoresist and uses hot pressing or technology for applying, but be not limited to it
It can be realized dry film photoresist overlay in the method for crystal column surface.
Preferably, when executing the step 6), the method for going seed layer is: TSV semi-closed state, using vacuum pumping
Applying pressure under vacuum or closed environment reacts etching liquid with seed layer, and the Single port position of TSV side wall is made to go seed layer；
But it is not limited to other wet processes and dry method mode realizes falling off for port position seed layer.
It is highly preferred that the etching length at the TSV wall port position and TSV hole depth rate are in 0.01~0.99 range
Variation.
Preferably, when executing the step 6), it is TSV depth that the length of seed layer is gone to TSV side wall Single port position
1/3~3/7.
Preferably, when executing the step 7), an end closure, another end opening of TSV make TSV form semiclosed shape
State.
Preferably, when executing the step 8), the seed layer length removed to the another port position of TSV side wall is
The 1/3~3/7 of TSV depth.
Preferably, when executing the step 9), photoetching, development again, so that the intermediate position of TSV is sealed at first, with
Realize that mechanism is electroplated in the bi-directional synchronization of class TSV blind hole.
Preferably, it when executing the step 10), using two pieces of copper plates or phosphorous copper lithographic plate as anode, carries out double
To synchronous plating filling.
It is highly preferred that there is seed layer position that realization sealing is electroplated at first among the TSV.
It is highly preferred that the TSV carries out the plating filling of bi-directional synchronization class blind hole from centre to both ends, to guarantee TSV's
Without holes filling.
Preferably, when executing the step 11), the mass concentration of sodium hydrate aqueous solution is 5%~40%；Ammonium hydroxide and
Ammonium hydroxide and dioxygen water volume ratio are between 40:1~1:1 in the mixed liquor of hydrogen peroxide.
The present invention synchronizes electricity from centre to both ends by the TSV of high-aspect-ratio being converted into the TSV of two low depth-to-width ratios
Plating, to realize the preparation without holes filling and TSV-pad of silicon through hole having high depth-to-width ratio.Particularly, the present invention will be difficult to realize
Through-hole is converted into TSV class blind hole filling easy to accomplish without holes filling, and the depth-to-width ratio of the TSV of preparation can be improved nearly one
Times, rate of deposition also substantially increases.
Compared with existing TSV technology, the beneficial effects of the present invention are:
The present invention can efficiently fill high-aspect-ratio TSV on Silicon Wafer, and wherein TSV-Cu and Cu-pad is without separating interface, directly
Binding is closed, so that the good bonding strength of TSV-Cu and Cu-pad, thermo mechanical stability is high, and the electric conductivity of TSV is also preferable, and makes
Standby process flexibility is strong.
Compared with traditional TSVs filling preparation technique, the present invention passes through four graphical and the removal both ends TSV seed layers
The through-hole for being difficult to realize no holes filling filling is changed into the bi-directional synchronization filling for the class blind hole for being easier to realize no holes filling,
The difficulty for greatly reducing TSV through hole filling improves the yield of through-hole filling, increases fill rate, reduces high-aspect-ratio
Plating difficulty and the TSV depth-to-width ratio for improving electrodepositable.Meanwhile eliminate thinning back side of silicon wafer, wafer support, wafer bonding,
The steps necessary of the traditional handicrafts such as the secondary preparation of solution bonding, insulating layer and seed layer, enormously simplifies processing step, reduces
Process costs.
Detailed description of the invention
Upon reading the detailed description of non-limiting embodiments with reference to the following drawings, other feature of the invention,
Objects and advantages will become more apparent upon:
Fig. 1 is the method flow schematic diagram of one embodiment of the invention；
Fig. 2 is the silicon substrate TSV structure sectional view of one embodiment of the invention；
In Fig. 2: 1 being wafer, 2 be insulating layer, 3 be the barrier layer Ti, 4 be Cu seed layer, 5 dry films, 6 be TSV-Cu, 7 be
TSV-pad。
Specific embodiment
The present invention is described in detail combined with specific embodiments below.Following embodiment will be helpful to the technology of this field
Personnel further understand the present invention, but the invention is not limited in any way.It should be pointed out that the ordinary skill of this field
For personnel, without departing from the inventive concept of the premise, various modifications and improvements can be made.These belong to the present invention
Protection scope.
As shown in Figure 1, filling the method flow signal of silicon substrate TSV for a kind of high-efficiency electroplating described in one embodiment of the invention
Figure, following embodiment are carried out referring to the process.
As shown in Fig. 2, the diagrammatic cross-section of the silicon substrate TSV for the preparation of an embodiment through the invention, in figure: 1 be wafer,
2 be insulating layer, 3 be the barrier layer Ti, 4 be Cu seed layer by layer, 5 dry films, 6 be TSV-Cu, 7 be TSV-pad.First on wafer 1
Etching preparation TSV；Then insulating layer 2 is prepared by high-temperature thermal oxidation or chemical deposition on the wafer 1 of etching TSV；Secondly exist
Pass through sputtering or the deposition preparation barrier layer Ti 3 and Cu seed layer 4 on wafer 1 containing insulating layer 2；Then in preparation Ti 3 and Cu
Dry film 5, photoetching, development are pasted on 4 wafer 1；Remove the seed layer of TSV side wall two-end part respectively again；Then again by
Photoetching, development；Then bi-directional synchronization plating filling copper, is integrally formed TSV-Cu 6 and TSV-pad 7；Finally remove dry film 5
Photoresist, seed layer.TSV-Cu and TSV-pad is integrally formed without separating interface.
TSV through hole plating filling is converted two class blind holes plating fill process by the present invention, TSV structure be firmly combined and
Preparation process is more flexible, conveniently, greatly reduces high-aspect-ratio TSV through hole plating filling difficulty, while effectively improving plating
Rate makes it possible that low-cost high-efficiency prepares TSV.
Embodiment 1:
It is graphical using TSV three times the present embodiment provides the method for high-efficiency electroplating filling silicon substrate TSV a kind of, remove TSV side wall
Two-end part seed layer carries out pre-invasion processing before being electroplated, and is carried out using electroplating technology to through silicon via and the region TSV-pad two-way
Synchronous blind hole filling.
The method specifically comprises the following steps:
1) 16 μm of spin coating positive photoresist on Silicon Wafer are subjected to photoetching and development to the wafer for having dried glue with program-control baking oven drying glue；
2) deep ion lithographic technique is used, etches TSV on the wafer by step 1) processing；
3) use high-temperature oxydation, by step 2) processing crystal column surface aoxidized, aoxidized with a thickness of 0.2 μ
m；
4) in the crystal column surface by step 3) processing, two-way sputtering Ti/Cu layers are carried out；
5) photoetching and development are being carried out through step 4) treated wafer double faced adhesive dry film photoresist, then single side；
It 6) will be by the patterned wafer of step 5) processing, in such a way that vacuum pump vacuumizes, so that etching liquid and TSV
The reaction of side wall Single port position seed layer, the length of the TSV side wall Single port position seed layer removed are the 2/5 of TSV depth；
7) dry film will be pasted again in patterned one side by the wafer of step 6) processing, and another side carry out photoetching,
Development；
8) step 6) will be repeated again by step 7) treated wafer；
9) photoetching, development will be carried out by step 8) treated wafer；
10) will by step 9), treated that wafer is placed in electroplate liquid, and wafer is made to be parallel to two anode plates；
11) will be by the silicon substrate TSV of step 10) filling copper, with sodium hydroxide solution, (quality of sodium hydrate aqueous solution is dense
Degree is 5%~40%) it removes dry film and is cleaned with deionized water, use mixed liquor (ammonium hydroxide and the hydrogen peroxide of ammonium hydroxide and hydrogen peroxide
Volume ratio is between 40:1~1:1) it removes Cu seed layer and is cleaned with deionized water, so that integrally formed TSV- be prepared
Cu and TSV-pad.
In the present embodiment, when executing the step 5), pastes dry film photoresist and use hot pressing or technology for applying, but not
It is limited to other realization dry film photoresist overlays in the method for crystal column surface.
In the present embodiment, when executing the step 8), seed layer length that the another port position of TSV side wall is removed
It is the 1/3~3/7 of TSV depth.
In the present embodiment, when executing the step 9), again graphically, so that the intermediate position of TSV is sealed at first, with
Realize that mechanism is electroplated in the bi-directional synchronization of class TSV blind hole.
In the present embodiment, when executing the step 10), using two pieces of copper plates or phosphorous copper lithographic plate as anode, into
The plating filling of row bi-directional synchronization；There is seed layer position that realization sealing is electroplated at first among TSV, is then carried out from centre to both ends double
To syncsort blind hole be electroplated fill, with guarantee TSV without holes filling.
Embodiment 2:
The present embodiment provides a kind of high-efficiency electroplating filling silicon substrate TSV method, before the step of with embodiment 1, it is different
It is: selects negtive photoresist as coating, TSV is etched using laser mode, insulation film is deposited using chemical deposition technique, use is closed
Pressure mode performs etching the seed layer at TSV wall port position.
The method specifically comprises the following steps:
1) 10 μm of spin coating negtive photoresist on Silicon Wafer are subjected to photoetching and development to the wafer for having dried glue with program-control baking oven drying glue；
2) laser technology is used, etches TSV on the wafer by step 1) processing；
3) chemical deposition technique is used, deposits insulation film in the crystal column surface by step 2) processing, what is deposited is exhausted
Edge film with a thickness of 0.21 μm；
4) in the crystal column surface by step 3) processing, two-way sputtering Ti/Cu layers are carried out；
5) photoetching and development are being carried out through step 4) treated wafer double faced adhesive dry film photoresist, then single side；
6) closed container will be placed in by pressure mode, so that etching liquid by the patterned wafer of step 5) processing
It is reacted with TSV side wall Single port position seed layer, the length of the TSV side wall Single port position seed layer removed is TSV depth
1/3；
7) dry film will be pasted again in patterned one side by the wafer of step 6) processing, and another side carry out photoetching,
Development；
8) will be by step 7) treated wafer, repeatedly step 6) again；
9) photoetching, development will be carried out by step 8) treated wafer；
10) 10) wafer Jing Guo step 9) will be placed in electroplate liquid after step 9) processing, and makes wafer flat
Row is in two anode plates；
It 11) will be with sodium hydroxide solution removing dry film and clear with deionized water by the silicon substrate TSV of step 10) filling copper
It washes, simultaneously using the mixed liquor (ammonium hydroxide and dioxygen water volume ratio are between 40:1~1:1) of ammonium hydroxide and hydrogen peroxide removal Cu seed layer
It is cleaned with deionized water, so that integrally formed TSV-Cu and TSV-pad be prepared.
The present invention synchronizes electricity from centre to both ends by the TSV of high-aspect-ratio being converted into the TSV of two low depth-to-width ratios
Plating, to realize the preparation without holes filling and TSV-pad of silicon through hole having high depth-to-width ratio.Particularly, the present invention will be difficult to realize
Through-hole is converted into TSV class blind hole filling easy to accomplish without holes filling, and the depth-to-width ratio of the TSV of preparation can be improved nearly one
Times, rate of deposition also substantially increases.
Specific embodiments of the present invention are described above.It is to be appreciated that the invention is not limited to above-mentioned
Particular implementation, those skilled in the art can make various deformations or amendments within the scope of the claims, this not shadow
Ring substantive content of the invention.
Claims (11)
1. a kind of method of high-efficiency electroplating filling silicon substrate TSV, which is characterized in that the described method comprises the following steps:
1) spin coating positive photoresist or negtive photoresist on wafer, drying glue carry out photoetching and development to the wafer for having dried glue；
2) deep ion lithographic technique or laser technology are used, etches TSV on the wafer by step 1) processing；
3) high-temperature oxydation or chemical deposition technique are used, thermal oxide is carried out in the crystal column surface by step 2) processing or deposition is exhausted
Edge layer；
4) in the crystal column surface by step 3) processing, barrier layer and seed layer are prepared；
5) photoetching, development are being carried out by step 4 treated crystal column surface double faced adhesive dry film photoresist, then single side；
6) it will carry out TSV side wall Single port position by the patterned wafer of step 5) processing and go seed layer；
7) dry film will be pasted again in patterned one side by the wafer of step 6) processing, and another side carries out photoetching, shows
Shadow；
8) TSV side wall another port position will be carried out by step 7) treated wafer go seed layer；
It 9) will be by step 8) treated wafer photolithography, development；
10) TSV-Cu and TSV-pad mono- will be realized using electroplating technology filling silicon through holes by step 9) treated wafer
It is body formed；
11) by the TSV-Cu prepared in step 10) and the integrally formed wafer of TSV-pad, dry film is removed with sodium hydroxide solution
And cleaned with deionized water, remove seed layer using the mixed liquor of ammonium hydroxide and hydrogen peroxide and cleaned with deionized water, obtain one
Molding TSV-Cu and TSV-pad.
2. the method for high-efficiency electroplating filling silicon substrate TSV according to claim 1 a kind of, which is characterized in that described in execution
When step 3), the insulating layer of thermal oxide or deposition with a thickness of 0.1 μm~0.8 μm.
3. the method for high-efficiency electroplating filling silicon substrate TSV according to claim 1 a kind of, which is characterized in that described in execution
When step 5), pastes dry film photoresist and use hot pressing or technology for applying.
4. the method for high-efficiency electroplating filling silicon substrate TSV according to claim 1 a kind of, which is characterized in that described in execution
When step 6), the method for going seed layer is: TSV semi-closed state, using vacuum pump vacuumize or closed environment under apply pressure
So that etching liquid is reacted with seed layer, the Single port position of TSV side wall is made to go seed layer；The etching at TSV wall port position is long
Degree changes in 0.01~0.99 range with TSV hole depth rate.
5. the method for high-efficiency electroplating filling silicon substrate TSV according to claim 4 a kind of, which is characterized in that described in execution
When step 6), it is the 1/3~3/7 of TSV depth that the length of seed layer is gone to TSV side wall Single port position.
6. the method for high-efficiency electroplating filling silicon substrate TSV according to claim 1-5 a kind of, which is characterized in that
When executing the step 7), an end closure, another end opening of TSV make TSV form semi-closed state.
7. the method for high-efficiency electroplating filling silicon substrate TSV according to claim 1-5 a kind of, which is characterized in that
It is the 1/3~3/7 of TSV depth to the seed layer length that the another port position of TSV side wall is removed when executing the step 8).
8. the method for high-efficiency electroplating filling silicon substrate TSV according to claim 1-5 a kind of, which is characterized in that
When executing the step 9), photoetching, development again, so that the intermediate position of TSV is sealed at first, to realize the double of class TSV blind hole
To synchronous plating mechanism.
9. the method for high-efficiency electroplating filling silicon substrate TSV according to claim 1-5 a kind of, which is characterized in that
When executing the step 10), using two pieces of copper plates as anode, bi-directional synchronization plating filling is carried out；There is seed layer among TSV
Realization sealing is electroplated in position at first；TSV carries out the plating filling of bi-directional synchronization class blind hole from centre to both ends, to guarantee the nothing of TSV
Holes filling.
10. the method for high-efficiency electroplating filling silicon substrate TSV according to claim 9 a kind of, which is characterized in that the copper plate
For phosphorous copper lithographic plate.
11. the method for high-efficiency electroplating filling silicon substrate TSV according to claim 1-5 a kind of, which is characterized in that
When executing the step 11), the mass concentration of sodium hydrate aqueous solution is 5%~40%；In the mixed liquor of ammonium hydroxide and hydrogen peroxide
Ammonium hydroxide and dioxygen water volume ratio are between 40:1~1:1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610030998.9A CN105679701B (en) | 2016-01-18 | 2016-01-18 | A kind of method of high-efficiency electroplating filling silicon substrate TSV |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610030998.9A CN105679701B (en) | 2016-01-18 | 2016-01-18 | A kind of method of high-efficiency electroplating filling silicon substrate TSV |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105679701A CN105679701A (en) | 2016-06-15 |
| CN105679701B true CN105679701B (en) | 2019-01-11 |
Family
ID=56301364
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610030998.9A Active CN105679701B (en) | 2016-01-18 | 2016-01-18 | A kind of method of high-efficiency electroplating filling silicon substrate TSV |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105679701B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109273403B (en) * | 2018-09-27 | 2021-04-20 | 中国电子科技集团公司第五十四研究所 | TSV hole filling method |
| CN110854065A (en) * | 2019-11-27 | 2020-02-28 | 西安电子科技大学 | Preparation method of TSV (through silicon Via) with high depth-to-width ratio |
| CN112820693B (en) * | 2020-12-31 | 2022-03-04 | 广东工业大学 | Preparation method of embedded three-dimensional interconnection structure based on nano metal |
| CN113161289B (en) * | 2021-04-22 | 2023-05-12 | 浙江集迈科微电子有限公司 | Electroplating process of TSV metal column with high depth-to-width ratio |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102903673A (en) * | 2012-10-30 | 2013-01-30 | 中国科学院上海微系统与信息技术研究所 | Method for manufacturing wafer-level through silicon via (TSV) |
| CN104600059A (en) * | 2015-02-03 | 2015-05-06 | 华进半导体封装先导技术研发中心有限公司 | TSV (Through Silicon Via) hole structure with IPD and machining method thereof |
| CN105070682A (en) * | 2015-07-17 | 2015-11-18 | 上海交通大学 | Method of preparing silicon switch plate efficiently |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102024782B (en) * | 2010-10-12 | 2012-07-25 | 北京大学 | Three-dimensional vertical interconnecting structure and manufacturing method thereof |
-
2016
- 2016-01-18 CN CN201610030998.9A patent/CN105679701B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102903673A (en) * | 2012-10-30 | 2013-01-30 | 中国科学院上海微系统与信息技术研究所 | Method for manufacturing wafer-level through silicon via (TSV) |
| CN104600059A (en) * | 2015-02-03 | 2015-05-06 | 华进半导体封装先导技术研发中心有限公司 | TSV (Through Silicon Via) hole structure with IPD and machining method thereof |
| CN105070682A (en) * | 2015-07-17 | 2015-11-18 | 上海交通大学 | Method of preparing silicon switch plate efficiently |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105679701A (en) | 2016-06-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105679701B (en) | A kind of method of high-efficiency electroplating filling silicon substrate TSV | |
| CN104025225B (en) | Energy storing structure, the method and micromodule and system comprising energy storing structure that manufacture supporting structure for energy storing structure | |
| CN102484095B (en) | Vias and conductive routing layers in semiconductor substrates | |
| CN111769076B (en) | TSV adapter plate for 2.5D packaging and preparation method thereof | |
| CN105070682B (en) | A kind of method for efficiently preparing silicon pinboard | |
| CN104347492A (en) | Manufacturing methods for through hole structure with high depth-to-width ratio and multi-chip interconnection | |
| CN105529299B (en) | A method of plating filling silicon substrate TSV pinboard | |
| WO2014067288A1 (en) | Wafer-level through silicon via (tsv) manufacturing method | |
| CN107195801B (en) | A kind of OLED minitype displayer and its anode linkage method | |
| CN103560096B (en) | A kind of method that under low temperature, compound semiconductor carries out being bonded with silicon-based semiconductor | |
| CN104617033B (en) | Wafer-level packaging method | |
| CN106117472B (en) | The method of one-step method chemical graft organic insulating film in through silicon via | |
| CN111524819A (en) | Glass carrier plate windowing process and double-sided metallization process in 2.5D and 3D packaging | |
| EP4086940A2 (en) | Superconducting through substrate vias | |
| CN103280435B (en) | Realize the interconnected microelectronic chip of high-density silicon through hole and manufacture method thereof | |
| CN109037149A (en) | The preparation method of zero defect silicon through hole structure | |
| CN106128998A (en) | Semiconductor vertical copper-connection is filled the preparation method of the TSV structure of organic polymer | |
| CN106252276B (en) | Manufacturing method based on TSV technology switch matrix radio frequency unit | |
| CN105826215B (en) | The forming method of semiconductor structure | |
| CN105405826B (en) | A kind of copper pillar bumps encapsulating structure and preparation method thereof | |
| CN108461465A (en) | A kind of through-silicon via structure and preparation method thereof | |
| WO2021253513A1 (en) | Silicon through-hole structure for three-dimensional integrated circuit packaging and fabrication method therefor | |
| CN111524820B (en) | Wafer double-sided lead-tin alloy bump forming process | |
| KR20110087129A (en) | Method for manufacturing through silicon via(tsv) | |
| CN104370271A (en) | Micro-electromechanical systems (MEMS) device assembling technology |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |