CN105679701A - Method for efficiently electroplating and filling silicon-based TSV - Google Patents
Method for efficiently electroplating and filling silicon-based TSV Download PDFInfo
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- CN105679701A CN105679701A CN201610030998.9A CN201610030998A CN105679701A CN 105679701 A CN105679701 A CN 105679701A CN 201610030998 A CN201610030998 A CN 201610030998A CN 105679701 A CN105679701 A CN 105679701A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
Abstract
The invention discloses a method for efficiently electroplating and filling silicon-based TSV. The method specifically comprises the steps of etching and preparing the TSV on a wafer; preparing an insulating layer on the wafer for etching the TSV; preparing a seed layer on the wafer containing the insulating layer; enabling dry films to the adhered to the two surfaces of the wafer, and performing single-surface photoetching and developing; removing the seed layer from the TSV side wall port position; enabling the dry film to be adhered to the patterned surface and developing the other surface; removing the seed layer from the other port position again; then performing photoetching and developing again; next, performing bisynchronous electroplate copper filling to enable TSV-Cu and TSV-pad to be integrally molded without a separating interface; and removing the dry films, the photoresist and the seed layers. According to the method, the TSV through hole electroplating filling process is converted into two blind-hole-like electroplating filling processes, so that the TSV structure can be firmly combined; the process is more flexible and convenient; the high-aspect-ratio TSV through hole electroplating filling difficulty is greatly lowered; and meanwhile, the electroplating efficiency is effectively improved, and the low-cost and efficient TSV preparation can be realized.
Description
Technical field
The present invention relates to microelectronics Packaging field, specifically, it relates to a kind of based on the efficient fill method of through hole, namely carry out, by being divided into two blind holes in the middle of through hole, the method that TSV is filled in bi-directional synchronization plating, the low-cost high-efficiency that the method is applicable to silicon base TSV fills preparation.
Background technology
Along with the develop rapidly of semi-conductor industry, miniaturization, the multifunctional integrated requirement of micro-system is day by day urgent, the three-dimension packaging (3D-TSV) with the advantage silicon through hole such as high-speed interconnect, High Density Integration, miniaturization and homogeneity and heterogeneous function integration, progressively one of research of hot topic becoming semiconductor packaging. Although 3D-TSV encapsulation technology has many advantages, but still there is the development of some unfavorable factors restriction 3D-TSV integration packaging technology at present. Specifically comprise: preparation technology is loaded down with trivial details, complicated, thermomechanical reliability problem, electrical property reliability problem, critical process and plant issue and the system testing difficult problem etc. that the disappearance of design software and method, power density increase cause. Wherein, the key process technology that 3D-TSV encapsulation relates to comprises: the etching of high aspect ratio TSV, zero defect high aspect ratio TSV electroplate filling technique, wafer thinning technique, multilayer alignment and bonding techniques etc. These techniques are still immature, thus constrain the application & development of 3D-TSV encapsulation technology.
The thermomechanical reliability of 3D-TSV encapsulation technology and electrical property reliability are the huge challenges that this Technology realizes batch production. The failure mode of 3D-TSV encapsulation technology mainly thermomechanical load cause, comprise the inefficacy of solder joint, the inefficacy of TSV itself, chip break and fatigue lost efficacy, layering between device interfaces, peel off and crackle etc. No matter first via process or after via process, Cu-TSV and TSV-pad completes step by step in conventional process. Unrelieved stress between natural Presence of an interface and thermal stresses between Cu-TSV and TSV-pad, and TSV filling is that blind hole is filled, and the wafer carried out after having electroplated subtracts the thin accumulation, the warpage that wait subsequent technique more can cause unrelieved stress, directly affect thermo mechanical stability and the electrical property of TSV.Meanwhile, traditional TSV through hole is filled because the higher more difficult realization of control difficulty of deep hole end plating speed is without holes filling.
Summary of the invention
For shortcoming or the problem of filling TSV in above-mentioned traditional technology, the present invention proposes a kind of method that high-efficiency electroplating fills silicon base TSV.
For achieving the above object, the present invention realizes by the following technical solutions: first etching preparation TSV on wafer; Then on the wafer of etching TSV, insulation layer is prepared; Secondly Seed Layer is being prepared containing on the wafer of insulation layer; Then at wafer Double-face adhesive dry film, one side photoetching, development; Again remove the Seed Layer at TSV wall port position; Then dry film, another side photoetching development is pasted in patterned one side; Again remove the Seed Layer at position, another port; And then by photoetching, development; Then copper is filled in bi-directional synchronization plating, makes TSV-Cu and TSV-pad one-body molded without separating interface; Finally remove dry film photoresist material, Seed Layer. The part Seed Layer of TSV deep hole sidewall two-end part is removed by the method by graphical in advance and control etching, avoids electro-coppering to seal at first at the two ends of through hole, filling through hole is changed into bi-directional synchronization class blind hole and fills. This process greatly reduces the difficulty that through hole TSV fills, it is to increase without the good rate of holes filling, increases fill rate; Save wafer simultaneously and subtract the processes such as thin, wafer holds, enhance the reliability of 3D-TSV encapsulation.
Concrete, a kind of high-efficiency electroplating fills the method for silicon base TSV, and described method comprises the following steps:
1) revolving the positive glue of painting or negative glue on wafer, drying glue, carries out photoetching and development to the wafer having dried glue;
2) deep ion lithographic technique or laser technology is adopted, through step 1) wafer that processes etches TSV;
3) high temperature oxidation or chemical deposition technique is adopted, through step 2) crystal column surface that processes carries out thermooxidizing or depositing insulating layer;
4) through step 3) crystal column surface that processes, preparation Seed Layer;
5) crystal column surface double faced adhesive dry film photoresist material after processing through step 4, then one side carries out photoetching, development;
6) will through step 5) the patterned wafer that processes, carry out TSV sidewall Single port position and go Seed Layer;
7)) will through step 6) wafer that processes, again paste dry film in patterned one side, and another side carries out photoetching, development;
8) will through step 7) wafer repeating step 6 again after process);
9) will through step 8) wafer photolithography after process, development;
10) will through step 9) wafer after process, adopt electroplating technology filling silicon through holes, it is achieved TSV-Cu and TSV-pad is one-body molded;
11) by step 10) in the integrated wafer of TSV-Cu and TSV-pad for preparing, remove dry film with sodium hydroxide solution and by washed with de-ionized water, the mixed solution of ammoniacal liquor and hydrogen peroxide is used to remove Cu Seed Layer and by washed with de-ionized water, prepare integrated TSV-Cu and TSV-pad.
Preferably, in the described step 1 of execution) time, wafer revolves and is coated with 10 μm～50 μm, positive glue or 10 μm～50 μm, negative glue.
Preferably, in the described step 2 of execution) time, wafer etches the degree of depth than the TSV being 2～50.
Preferably, in the described step 3 of execution) time, the thickness of the insulation layer of thermooxidizing or deposition is 0.1 μm～0.8 μm.
Preferably, in the described step 4 of execution) time, Seed Layer can adopt double-faced sputter or deposition can realize block electrons diffusion, the blocking layer moved and conduct the Seed Layer of function, but it is not limited to sputtering or deposition, Seed Layer includes but not limited to Ti/Cu, it is achieved method is also not limited to sputtering, deposition.
Preferably, in the described step 5 of execution) time, paste dry film photoresist material and adopt hot pressing or technology for applying, but be not limited to other and can realize the method that dry film photoresist material is covered in crystal column surface.
Preferably, performing described step 6) time, go the method for Seed Layer to be: TSV semi-closed state, apply pressure under adopting vacuum pump evacuation or closed environment and etching liquid is reacted with Seed Layer, make the Single port position of TSV sidewall go Seed Layer; But it is not limited to other wet method and dry method mode realizes coming off of port position Seed Layer.
More preferably, etching length and the TSV hole depth rate at described TSV wall port position change in 0.01～0.99 scope.
Preferably, in the described step 6 of execution) time, go the length of Seed Layer to be the 1/3～3/7 of the TSV degree of depth at TSV sidewall Single port position.
Preferably, in the described step 7 of execution) time, an end closure of TSV, the other end opening, make TSV form semi-closed state.
Preferably, performing described step 8) time, the Seed Layer length position, another port of TSV sidewall removed is the 1/3～3/7 of the TSV degree of depth.
Preferably, in the described step 9 of execution) time, photoetching again, development so that the middle position of TSV is sealed at first, to realize the bi-directional synchronization plating mechanism of class TSV blind hole.
Preferably, in the described step 10 of execution) time, adopt two pieces of copper flat boards or phosphorous copper lithographic plate as anode, carry out bi-directional synchronization plating and fill.
More preferably, there is Seed Layer position to electroplate at first in the middle of described TSV and realize sealing.
More preferably, described TSV carries out the plating of bi-directional synchronization class blind hole by centre and fills to two ends, with ensure TSV without holes filling.
Preferably, in the described step 11 of execution) time, the mass concentration of aqueous sodium hydroxide solution is 5%～40%; In the mixed solution of ammoniacal liquor and hydrogen peroxide, ammoniacal liquor and hydrogen peroxide volume ratio are between 40:1～1:1.
The present invention, by the TSV that the TSV of high aspect ratio is converted into two low dark wide ratios, is synchronously electroplated to two ends by centre, with realize silicon through hole having high depth-to-width ratio without the preparation of holes filling and TSV-pad. Especially, the TSV class blind hole that the through hole being difficult to realize is converted into easily realization without holes filling is filled by the present invention, and the dark wide ratio of the TSV of preparation can improve one times nearly, and plating speed also increases greatly.
Compared with existing TSV technology, the invention has the beneficial effects as follows:
The present invention efficiently can fill high aspect ratio TSV on Silicon Wafer, and wherein TSV-Cu and Cu-pad is without separating interface, directly combines, make the good bonding strength of TSV-Cu and Cu-pad, thermo mechanical stability height, the conductivity of TSV is also better, and preparation process handiness is strong.
Compared with tradition TSVs filling preparation technique, the present invention's Seed Layer that is graphical by four times and that remove TSV two ends realizes the filling through hole without holes filling by being difficult to and is changed into the bi-directional synchronization filling relatively easily realizing the class blind hole without holes filling, greatly reduce the difficulty that TSV through hole is filled, improve the good rate of filling through hole, increase fill rate, reduce high aspect ratio plating difficulty and improve the deeply wide ratio of TSV of electrodepositable. Meanwhile, eliminate thinning back side of silicon wafer, wafer support, the bonding of wafer, the necessary step of the traditional technology such as two preparations of separating bonding, insulation layer and Seed Layer, enormously simplify processing step, reduce technique cost.
Accompanying drawing explanation
By reading with reference to the detailed description that non-limiting example is done by the following drawings, the other features, objects and advantages of the present invention will become more obvious:
Fig. 1 is the method flow schematic diagram of one embodiment of the invention;
Fig. 2 is the silicon base TSV structure sectional view of one embodiment of the invention;
In Fig. 2: 1 be wafer, 2 be insulation layer, 3 be Ti blocking layer, 4 be Cu Seed Layer, 5 dry films, 6 be TSV-Cu, 7 for TSV-pad.
Embodiment
Below in conjunction with specific embodiment, the present invention is described in detail. The technician contributing to this area is understood the present invention by following examples further, but does not limit the present invention in any form. It should be appreciated that to those skilled in the art, without departing from the inventive concept of the premise, it is also possible to make some distortion and improvement. These all belong to protection scope of the present invention.
As shown in Figure 1, for a kind of high-efficiency electroplating described in one embodiment of the invention fills the method flow schematic diagram of silicon base TSV, following examples carry out with reference to this flow process.
As shown in Figure 2, be the diagrammatic cross-section of silicon base TSV prepared by one embodiment of the invention, in figure: 1 be wafer, 2 be insulation layer, 3 be Ti blocking layer, 4 for Cu seed layer by layer, 5 dry films, 6 are TSV-Cu, 7 are TSV-pad. First etching preparation TSV on wafer 1; Then on the wafer 1 of etching TSV, insulation layer 2 is prepared by high-temperature thermal oxidation or electroless plating; Secondly by sputtering or deposit preparation Ti blocking layer 3 and Cu Seed Layer 4 on the wafer 1 containing insulation layer 2; Then on the wafer 1 of preparation Ti3 and Cu4, dry film 5, photoetching, development is pasted; Again remove the Seed Layer of TSV sidewall two-end part respectively; And then by photoetching, development; Then copper is filled in bi-directional synchronization plating, makes TSV-Cu6 and TSV-pad7 one-body molded; Finally remove dry film 5 photoresist material, Seed Layer. TSV-Cu and TSV-pad is one-body molded without separating interface.
TSV through hole is electroplated filling and is converted into two class blind hole plating fill process by the present invention, TSV structure combines firmly and preparation technology is more flexible, convenience, greatly reduce the plating of high aspect ratio TSV through hole and fill difficulty, effectively improving plating speed, making low-cost high-efficiency prepare TSV becomes possibility simultaneously.
Embodiment 1:
The present embodiment provides a kind of high-efficiency electroplating to fill the method for silicon base TSV, adopt three TSV graphical, go TSV sidewall two-end part Seed Layer, before plating, carry out pre-invasion process, adopt electroplating technology that silicon through hole and TSV-pad region are carried out bi-directional synchronization blind hole filling.
Described method specifically comprises the steps:
1) it is coated with 16 μm, positive glue by Silicon Wafer revolves, with program control baking oven drying glue, the wafer having dried glue is carried out photoetching and development;
2) deep ion lithographic technique is adopted, through step 1) wafer that processes etches TSV;
3) high temperature oxidation is adopted, through step 2) crystal column surface that processes is oxidized, and the thickness being oxidized is 0.2 μm;
4) through step 3) crystal column surface that processes, carry out two-way sputtered with Ti/Cu layer;
5) through step 4) wafer double faced adhesive dry film photoresist material after process, then one side carries out photoetching and development;
6) will through step 5) the patterned wafer that processes, utilize vacuum pump evacuation mode so that etching liquid and the reaction of TSV sidewall Single port position Seed Layer, the length of the TSV sidewall Single port position Seed Layer removed is the 2/5 of the TSV degree of depth;
7) will through step 6) wafer that processes, again paste dry film in patterned one side, and another side carries out photoetching, development;
8) will through step 7) wafer repeating step 6 again after process);
9) will through step 8) wafer after process, carry out photoetching, development;
10) by through step 9) wafer after process is positioned in electroplate liquid, and makes wafer be parallel to two positive plates;
11) will through step 10) fill the silicon base TSV of copper, remove dry film with sodium hydroxide solution (mass concentration of aqueous sodium hydroxide solution is 5%～40%) and by washed with de-ionized water, the mixed solution (ammoniacal liquor and hydrogen peroxide volume ratio are between 40:1～1:1) of ammoniacal liquor and hydrogen peroxide is used to remove Cu Seed Layer and by washed with de-ionized water, thus prepare integrated TSV-Cu and TSV-pad.
In the present embodiment, the step 5 described in performing) time, paste dry film photoresist material and adopt hot pressing or technology for applying, but be not limited to other and realize the method that dry film photoresist material is covered in crystal column surface.
In the present embodiment, performing described step 8) time, the Seed Layer length position, another port of TSV sidewall removed is the 1/3～3/7 of the TSV degree of depth.
In the present embodiment, in the described step 9 of execution) time, again graphically so that the middle position of TSV is sealed at first, to realize the bi-directional synchronization plating mechanism of class TSV blind hole.
In the present embodiment, in the described step 10 of execution) time, adopt two pieces of copper flat boards or phosphorous copper lithographic plate as anode, carry out bi-directional synchronization plating and fill; Have in the middle of TSV Seed Layer position to electroplate at first and realize sealing, then carry out the plating of bi-directional synchronization class blind hole by centre to two ends and fill, with ensure TSV without holes filling.
Embodiment 2:
The present embodiment provides a kind of high-efficiency electroplating to fill the method for silicon base TSV, step above is with embodiment 1, the difference is that: select negative glue as coating, laser mode is adopted to etch TSV, adopt chemical deposition technique deposition insulation film, adopt airtight mode of exerting pressure the Seed Layer at TSV wall port position to be etched.
Described method specifically comprises the steps:
1) it is coated with negative 10 μm, glue by Silicon Wafer revolves, with program control baking oven drying glue, the wafer having dried glue is carried out photoetching and development;
2) laser technology is adopted, through step 1) wafer that processes etches TSV;
3) chemical deposition technique is adopted, through step 2) crystal column surface that processes deposition insulation film, the thickness of the insulation film deposited is 0.21 μm;
4) through step 3) crystal column surface that processes, carry out two-way sputtered with Ti/Cu layer;
5) through step 4) wafer double faced adhesive dry film photoresist material after process, then one side carries out photoetching and development;
6) will through step 5) the patterned wafer that processes, it is placed in encloses container by the mode of exerting pressure so that etching liquid and the reaction of TSV sidewall Single port position Seed Layer, the length of the TSV sidewall Single port position Seed Layer removed is the 1/3 of the TSV degree of depth;
7) will through step 6) wafer that processes, again paste dry film in patterned one side, and another side carries out photoetching, development;
8) will through step 7) wafer after process, repeating step 6 again);
9) will through step 8) wafer after process, carry out photoetching, development;
10) will through step 9) after process 10) by through step 9) and wafer be positioned in electroplate liquid, and make wafer be parallel to two positive plates;
11) will through step 10) fill the silicon base TSV of copper, remove dry film with sodium hydroxide solution and by washed with de-ionized water, the mixed solution (ammoniacal liquor and hydrogen peroxide volume ratio are between 40:1～1:1) of ammoniacal liquor and hydrogen peroxide is used to remove Cu Seed Layer and by washed with de-ionized water, thus prepare integrated TSV-Cu and TSV-pad.
The present invention, by the TSV that the TSV of high aspect ratio is converted into two low dark wide ratios, is synchronously electroplated to two ends by centre, with realize silicon through hole having high depth-to-width ratio without the preparation of holes filling and TSV-pad. Especially, the TSV class blind hole that the through hole being difficult to realize is converted into easily realization without holes filling is filled by the present invention, and the dark wide ratio of the TSV of preparation can improve one times nearly, and plating speed also increases greatly.
Above specific embodiments of the invention are described. It is understood that the present invention is not limited to above-mentioned particular implementation, those skilled in the art can make various distortion or amendment within the scope of the claims, and this does not affect the flesh and blood of the present invention.
Claims (10)
1. the method for a high-efficiency electroplating filling silicon base TSV, it is characterised in that, described method comprises the following steps:
1) revolving the positive glue of painting or negative glue on wafer, drying glue, carries out photoetching and development to the wafer having dried glue;
2) deep ion lithographic technique or laser technology is adopted, through step 1) wafer that processes etches TSV;
3) high temperature oxidation or chemical deposition technique is adopted, through step 2) crystal column surface that processes carries out thermooxidizing or depositing insulating layer;
4) through step 3) crystal column surface that processes, preparation blocking layer and Seed Layer;
5) crystal column surface double faced adhesive dry film photoresist material after processing through step 4, then one side carries out photoetching, development;
6) will through step 5) the patterned wafer that processes, carry out TSV sidewall Single port position and go Seed Layer;
7) will through step 6) wafer that processes, again paste dry film in patterned one side, and another side carries out photoetching, development;
8) will through step 7) wafer repeating step 6 again after process);
9) will through step 8) wafer photolithography after process, development;
10) will through step 9) wafer after process, adopt electroplating technology filling silicon through holes, it is achieved TSV-Cu and TSV-pad is one-body molded;
11) by step 10) in the integrated wafer of TSV-Cu and TSV-pad for preparing, remove dry film with sodium hydroxide solution and by washed with de-ionized water, the mixed solution of ammoniacal liquor and hydrogen peroxide is used to remove Cu Seed Layer and by washed with de-ionized water, obtain integrated TSV-Cu and TSV-pad.
2. a kind of high-efficiency electroplating according to claim 1 fills the method for silicon base TSV, it is characterised in that, in the described step 3 of execution) time, the thickness of the insulation layer of thermooxidizing or deposition is 0.1 μm～0.8 μm.
3. a kind of high-efficiency electroplating according to claim 1 fills the method for silicon base TSV, it is characterised in that, in the described step 5 of execution) time, paste dry film photoresist material and adopt hot pressing or technology for applying.
4. a kind of high-efficiency electroplating according to claim 1 fills the method for silicon base TSV, it is characterized in that, in the described step 6 of execution) time, the method of Seed Layer is gone to be: TSV semi-closed state, apply pressure under adopting vacuum pump evacuation or closed environment and make etching liquid and Seed Layer reaction, make the Single port position of TSV sidewall go Seed Layer; The etching length at TSV wall port position and TSV hole depth rate change in 0.01～0.99 scope.
5. a kind of high-efficiency electroplating according to claim 4 fills the method for silicon base TSV, it is characterised in that, in the described step 6 of execution) time, go the length of Seed Layer to be the 1/3～3/7 of the TSV degree of depth at TSV sidewall Single port position.
6. a kind of high-efficiency electroplating according to the arbitrary item of claim 1-5 fills the method for silicon base TSV, it is characterised in that, performing described step 7) time, an end closure of TSV, the other end opening, make TSV form semi-closed state.
7. a kind of high-efficiency electroplating according to the arbitrary item of claim 1-5 fills the method for silicon base TSV, it is characterised in that, performing described step 8) time, the Seed Layer length position, another port of TSV sidewall removed is the 1/3～3/7 of the TSV degree of depth.
8. a kind of high-efficiency electroplating according to the arbitrary item of claim 1-5 fills the method for silicon base TSV, it is characterized in that, in the described step 9 of execution) time, photoetching again, development, the middle position of TSV is sealed at first, to realize the bi-directional synchronization plating mechanism of class TSV blind hole.
9. a kind of high-efficiency electroplating according to the arbitrary item of claim 1-5 fills the method for silicon base TSV, it is characterised in that, performing described step 10) time, adopts that two blocks of copper are dull and stereotyped or phosphorous copper lithographic plate as anode, carry out bi-directional synchronization plating filling; There is Seed Layer position to electroplate at first in the middle of TSV and realize sealing; TSV carries out the plating of bi-directional synchronization class blind hole by centre and fills to two ends, with ensure TSV without holes filling.
10. a kind of high-efficiency electroplating according to the arbitrary item of claim 1-5 fills the method for silicon base TSV, it is characterised in that, performing described step 11) time, the mass concentration of aqueous sodium hydroxide solution is 5%～40%; In the mixed solution of ammoniacal liquor and hydrogen peroxide, ammoniacal liquor and hydrogen peroxide volume ratio are between 40:1～1:1.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109273403A (en) * | 2018-09-27 | 2019-01-25 | 中国电子科技集团公司第五十四研究所 | A kind of TSV filling perforation method |
| CN110854065A (en) * | 2019-11-27 | 2020-02-28 | 西安电子科技大学 | Preparation method of TSV (through silicon Via) with high depth-to-width ratio |
| CN112820693A (en) * | 2020-12-31 | 2021-05-18 | 广东工业大学 | Preparation method of embedded three-dimensional interconnection structure based on nano metal |
| CN113161289A (en) * | 2021-04-22 | 2021-07-23 | 浙江集迈科微电子有限公司 | Electroplating process of TSV (through silicon via) metal column with high depth-to-width ratio |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102903673A (en) * | 2012-10-30 | 2013-01-30 | 中国科学院上海微系统与信息技术研究所 | Method for manufacturing wafer-level through silicon via (TSV) |
| US20140342502A1 (en) * | 2010-10-12 | 2014-11-20 | Peking University | Three-Dimensional Vertically Interconnected Structure and Fabricating Method Thereof |
| CN104600059A (en) * | 2015-02-03 | 2015-05-06 | 华进半导体封装先导技术研发中心有限公司 | TSV (Through Silicon Via) hole structure with IPD and machining method thereof |
| CN105070682A (en) * | 2015-07-17 | 2015-11-18 | 上海交通大学 | Method of preparing silicon switch plate efficiently |
-
2016
- 2016-01-18 CN CN201610030998.9A patent/CN105679701B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20140342502A1 (en) * | 2010-10-12 | 2014-11-20 | Peking University | Three-Dimensional Vertically Interconnected Structure and Fabricating Method Thereof |
| CN102903673A (en) * | 2012-10-30 | 2013-01-30 | 中国科学院上海微系统与信息技术研究所 | Method for manufacturing wafer-level through silicon via (TSV) |
| CN104600059A (en) * | 2015-02-03 | 2015-05-06 | 华进半导体封装先导技术研发中心有限公司 | TSV (Through Silicon Via) hole structure with IPD and machining method thereof |
| CN105070682A (en) * | 2015-07-17 | 2015-11-18 | 上海交通大学 | Method of preparing silicon switch plate efficiently |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109273403A (en) * | 2018-09-27 | 2019-01-25 | 中国电子科技集团公司第五十四研究所 | A kind of TSV filling perforation method |
| CN109273403B (en) * | 2018-09-27 | 2021-04-20 | 中国电子科技集团公司第五十四研究所 | TSV hole filling method |
| CN110854065A (en) * | 2019-11-27 | 2020-02-28 | 西安电子科技大学 | Preparation method of TSV (through silicon Via) with high depth-to-width ratio |
| CN112820693A (en) * | 2020-12-31 | 2021-05-18 | 广东工业大学 | Preparation method of embedded three-dimensional interconnection structure based on nano metal |
| CN112820693B (en) * | 2020-12-31 | 2022-03-04 | 广东工业大学 | Preparation method of embedded three-dimensional interconnection structure based on nano metal |
| CN113161289A (en) * | 2021-04-22 | 2021-07-23 | 浙江集迈科微电子有限公司 | Electroplating process of TSV (through silicon via) metal column with high depth-to-width ratio |
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