WO2024001432A1 - Panel-level fan-out double-sided interconnection packaging method and encapsulation structure - Google Patents

Panel-level fan-out double-sided interconnection packaging method and encapsulation structure Download PDF

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Publication number
WO2024001432A1
WO2024001432A1 PCT/CN2023/088661 CN2023088661W WO2024001432A1 WO 2024001432 A1 WO2024001432 A1 WO 2024001432A1 CN 2023088661 W CN2023088661 W CN 2023088661W WO 2024001432 A1 WO2024001432 A1 WO 2024001432A1
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layer
chip
interconnect
plastic
conductive
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PCT/CN2023/088661
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French (fr)
Chinese (zh)
Inventor
霍炎
王鑫璐
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矽磐微电子(重庆)有限公司
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Publication of WO2024001432A1 publication Critical patent/WO2024001432A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02373—Layout of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02379—Fan-out arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods

Definitions

  • the present invention relates to the technical field of semiconductor packaging, and in particular to a packaging method for panel-level fan-out double-sided interconnection, an packaging structure and a method for preparing an interconnect for semiconductor packaging.
  • double-sided interconnect products often use lead frames or prefabricated PCB substrates to connect the front and back sides of the chip.
  • Figure 1 shows a semiconductor structure packaged using the Copper clip process.
  • a lead frame 100 is used as a carrier board in a traditional package.
  • the back side of the chip 101 is welded to the lead frame 100 through solder 102, and then the chip lead on the front side of the chip 101 is wire bonded (for example, through a copper sheet 103).
  • the pads are connected to the pins of the lead frame 100 to form a double-sided conductive structure, and then the chip 101 and the lead frame 100 are packaged as a whole using a plastic packaging material 104 .
  • the chip is welded to the lead frame in the above-mentioned traditional package to the chip can be peeled off and bonded to the carrier board, and the leads
  • the frame structure is not suitable for panel-level fan-out packaging, so the interconnection between the front and back of the chip is usually carried out by laser drilling and deep-hole electroplating interconnection (that is, deep-hole laser plating).
  • This type of method is very important for laser processing and electroplating processes. The requirements are extremely high and there are many limiting factors, such as limiting the hole diameter and hole depth to a certain range.
  • laser and electroplating deep holes take a long time, making it impossible to achieve large-scale and high-yield processing. mass production.
  • the object of the present invention is to provide a panel-level fan-out type double-sided interconnection packaging method, an packaging structure and a preparation method of interconnectors for semiconductor packaging, which can avoid the use of traditional laser drilling and deep hole electroplating. This method achieves double-sided interconnection, shortens the packaging cycle and improves production efficiency.
  • the present invention provides a packaging method for panel-level fan-out double-sided interconnection.
  • the packaging method includes:
  • the interconnection body includes a conductive structure and a plastic packaging material isolating the conductive structure, and both opposite end surfaces of the interconnection body expose part of the conductive structure;
  • a first plastic sealing layer is formed on the top surface of the third carrier board, and the first plastic sealing layer covers at least the side of the chip and the side of the interconnect;
  • a first rewiring layer electrically connected to the chip front side and the interconnect body is formed, and a second rewiring layer electrically connected to the chip back side and the interconnect body is formed.
  • pasting the chip and the interconnect on the top surface of the third carrier board includes: making the front side of the chip face the third carrier board;
  • the forming a first rewiring layer electrically connected to the chip front and the interconnect includes: removing the third carrier board to expose the chip pins on the chip front and one end surface of the interconnect ; A first rewiring layer is formed on the front side of the chip, and the first rewiring layer is connected to the chip pins and the conductive structure.
  • the conductive structure includes conductive pillars; the method of providing an interconnection includes: providing a first carrier board, and forming a plastic sealing board on the top surface of the first carrier board, with the back side of the plastic sealing board facing the The first carrier board; forming a conductive layer, the conductive layer covering the front side of the plastic sealing board; setting a second carrier board on the side of the conductive layer away from the plastic sealing board, and removing the first carrier board, Expose the back side of the plastic sealing board; form a plurality of via holes in the plastic sealing board, the plurality of via holes penetrate the plastic sealing board and expose part of the conductive layer; use the conductive layer as a conductive seed layer , forming the plurality of conductive pillars by electroplating from the bottom of the plurality of via holes toward the hole openings, and the conductive pillars fill the corresponding via holes; and removing the second carrier plate and the conductive pillars layer, cutting the plastic board to form a plurality of interconnected bodies.
  • using the conductive layer as a conductive seed layer and electroplating from the bottom of the plurality of via holes toward the hole openings to form the plurality of conductive pillars includes: using the conductive layer as a conductive seed layer. , an electroplating material layer is formed by electroplating from the bottom of the plurality of via holes toward the hole opening, and the electroplating material layer Protruding the opening of the via hole; and removing the portion of the electroplating material layer protruding from the opening of the via hole to form the plurality of conductive pillars.
  • the conductive structure includes an interconnected multi-layer circuit pattern layer; the method of providing an interconnection includes: providing a plastic sealing board, the plastic sealing board having an opposite front and a back; forming a third layer on the front of the plastic sealing board.
  • a circuit pattern layer forming a plurality of first via holes in the plastic sealing board, the plurality of first via holes penetrating the plastic sealing board and exposing part of the first circuit pattern layer;
  • a circuit pattern layer serves as a conductive seed layer.
  • the plurality of first conductive pillars are electroplated from the bottom of the plurality of first via holes toward the hole opening. The first conductive pillars fill the corresponding first conductive pillars.
  • forming a first plastic layer on the top surface of the third carrier board, the first plastic layer covering at least the side of the chip and the side of the interconnect includes: forming the first plastic layer , the first plastic encapsulation layer covers the top surface of the third carrier board, the side and back of the chip, and the side and other end surface of the interconnect.
  • the original thickness of the interconnect is equal to the original thickness of the chip; forming a second rewiring layer electrically connected to the back side of the chip and the interconnect includes: grinding the first plastic layer away from the chip The front surface removes part of the thickness of the first plastic encapsulation layer, while exposing the back side of the chip and the other end surface of the interconnect, forming a second rewiring layer electrically connected to the back side of the chip and the interconnect. ;
  • the original thickness of the interconnect is greater than the original thickness of the chip; forming a second rewiring layer electrically connected to the backside of the chip and the interconnect includes: grinding the first plastic layer away from the chip Remove part of the thickness of the first plastic sealing layer from the front surface to expose the other end surface of the interconnector; continue grinding the first plastic sealant layer and the other end surface of the interconnector until the backside of the chip is exposed. Forming a second rewiring layer electrically connected to the backside of the chip and the interconnect;
  • the original thickness of the interconnect is smaller than the thickness of the chip; forming a second rewiring layer electrically connected to the back of the chip and the interconnect includes: grinding the first plastic layer away from the front of the chip Remove part of the thickness of the first plastic sealing layer from the surface to expose the back of the chip. Continue grinding the back of the chip and the first plastic sealing layer to expose the other end surface of the interconnector to form a connection with the chip. A second redistribution layer electrically connected to the interconnect on the back side.
  • the material of the first plastic sealing layer is the same as the material of the plastic sealing material in the interconnected body.
  • the number of the chips and the interconnects is multiple, and the plurality of interconnects include a plurality of first interconnects and a plurality of second interconnects; the formation is related to the front surface of the chip and the After forming a first rewiring layer electrically connected to the interconnects and a second rewiring layer electrically connected to the backside of the chip and the interconnects, a portion of the chips are connected to the corresponding first interconnects Or the second interconnects are electrically connected, and a part of the chips are electrically connected to the corresponding first interconnects and the second interconnects; or each of the chips is electrically connected to the corresponding first interconnects.
  • the Internet and the Chapter Two interconnections are electrically connected.
  • the present invention also provides an encapsulation structure, which includes a chip, an interconnect, a first plastic encapsulation layer, a first rewiring layer and a second rewiring layer.
  • the interconnection body includes a conductive structure and a plastic packaging material that isolates the conductive structure. Both opposite end surfaces of the interconnection body expose part of the conductive structure; the first plastic packaging layer covers at least the side surface of the chip and the The side of the interconnect; the interconnect and the first plastic encapsulation layer are formed in different steps; the first rewiring layer is electrically connected to the front side of the chip and the interconnect; the second rewiring layer is electrically connected to the interconnect. The backside of the chip is electrically connected to the interconnect.
  • the present invention also provides a method for preparing interconnects for semiconductor packaging, including:
  • first carrier board Provides a first carrier board, and form a plastic sealing plate on the top surface of the first carrier board, with the back side of the plastic sealing board facing the first carrier board;
  • a second carrier plate is provided on the side of the conductive layer away from the plastic sealing board, and the first carrier board is removed to expose the back side of the plastic sealing board;
  • a plurality of via holes are formed in the plastic packaging board, and the plurality of via holes penetrate the plastic packaging board and expose part of the conductive layer;
  • the plurality of conductive pillars are formed by electroplating from the bottom of the plurality of via holes toward the hole openings, and the conductive pillars fill the corresponding via holes;
  • the second carrier board and the conductive layer are removed, and the plastic sealing board is cut to form a plurality of interconnections.
  • electroplating from the bottom of the plurality of via holes toward the hole openings to form the plurality of conductive pillars includes:
  • electroplating from the bottom of the plurality of via holes toward the openings forms an electroplating material layer, and the electroplating material layer protrudes from the openings of the via holes;
  • the portion of the electroplating material layer protruding from the opening of the via hole is removed to form the plurality of conductive pillars.
  • the present invention also provides a method for preparing interconnects for semiconductor packaging, including:
  • plastic sealing board having opposite front and back sides;
  • a plurality of first via holes are formed in the plastic packaging board, and the plurality of first via holes penetrate the plastic packaging board and expose part of the first circuit pattern layer;
  • the plurality of first conductive pillars are electroplated from the bottom of the plurality of first via holes toward the hole openings, and the first conductive pillars fill the corresponding the first via hole;
  • a second circuit pattern layer is formed on the back side of the plastic board, and the second circuit pattern layer is connected to the plurality of first conductive pillars;
  • a plurality of second via holes are formed in the plastic sealing material layer, and each of the plurality of second via holes exposes part of the second circuit pattern layer;
  • the plurality of second conductive pillars are electroplated from the bottom of the plurality of second via holes toward the hole openings, and the second conductive pillars fill the corresponding the second via hole;
  • a third circuit pattern layer is formed on the surface of the plastic sealing material layer facing away from the second circuit pattern layer, and the third circuit pattern layer is connected to the plurality of second conductive pillars;
  • a cutting process is performed to form a plurality of interconnected bodies.
  • the panel-level fan-out double-sided interconnection packaging method, packaging structure and preparation method of interconnectors for semiconductor packaging of the present invention have the following advantages: (1) Deep hole laser in the existing technology Electroplating technology is limited by too many conditions and factors, which has a great impact on product yield, and the flow capacity is low, which can easily lead to chip scrapping.
  • This application uses pre-prepared interconnects to realize double-sided interconnection of chips, which can avoid the use of traditional deep holes.
  • Laser plating realizes double-sided interconnection, which can avoid problems such as dry film residue at the bottom of deep-hole plating holes and copper discontinuity in the holes that affect product performance and yield.
  • the interconnector is highly versatile, and the same interconnector can be used for similar products. There is no need to design specific interconnects for each product. You only need to change the leads of the first rewiring layer and/or the second rewiring layer, which greatly saves design costs; (4) Because the interconnects made in advance can Any thickness, and part of the thickness of the interconnect can be removed during the packaging process, thereby adapting to the needs of different chips, so that the chip thickness is not limited during the packaging process.
  • Figure 1 shows a semiconductor structure packaged using the Copper clip process.
  • Figures 2 to 10 are step-by-step structural diagrams of an advanced packaging process.
  • Figure 11 shows a packaging method for panel-level fan-out double-sided interconnection according to an embodiment of the present invention.
  • 12 to 25 are schematic step-by-step structural diagrams of a panel-level fan-out double-sided interconnection packaging method according to an embodiment of the present invention.
  • 26 to 31 are step-by-step cross-sectional structural diagrams of manufacturing interconnects according to an embodiment of the present invention.
  • FIG. 32 is a schematic diagram of a semiconductor structure packaged using a panel-level fan-out double-sided interconnection packaging method according to an embodiment of the present invention.
  • FIGS. 2 to 10 show a step-by-step structural diagram of the advanced packaging process. The advanced packaging process will be described below in conjunction with FIGS. 2 to 10 .
  • a first adhesive layer 201a is provided on the top surface of the first carrier board 200a, and then the cut chips 202 are rearranged on the top surface of the first carrier board 200a through die bonding.
  • the chip 202 faces down, and the chip 202 and the first adhesive layer 201a are detachably fixed.
  • a first plastic sealing layer 203 is formed on the top surface of the first carrier board 200a, and the first plastic sealing layer 203 covers the first adhesive layer 201a and the chip 202.
  • a second adhesive layer 201b and a second carrier plate 200b are sequentially placed on the side of the first plastic sealing layer 203 close to the back of the chip 202, and then the carrier plate is turned over and the first carrier plate 200a and the first adhesive layer are removed.
  • the junction layer 201a exposes the chip pins 202a on the front side of the chip 202.
  • a first rewiring layer 204 is formed on the front surface of the chip 202 , and the first rewiring layer 204 is connected to the chip pin 202 a.
  • a third adhesive layer 201 c and a third carrier plate 200 c are sequentially formed on the side of the first rewiring layer 204 away from the chip 202 , the second carrier plate 200 b and the second adhesive layer 201 b are removed, and a laser is used to The drilling process forms a deep hole 205 in the first plastic sealing layer 203, and the deep hole 205 penetrates the first plastic sealing layer 203. And a portion of the first rewiring layer 204 is exposed.
  • the surface of the first plastic encapsulation layer 203 close to the back of the chip 202 is polished to expose the back of the chip 202 .
  • a blind hole 206 is formed in the first plastic encapsulation layer 203 on a side close to the back side of the chip 202 through a laser process, and the blind hole 206 exposes part of the back side of the chip 202 .
  • the advanced packaging process will be described below by taking the example of grinding the surface of the first plastic encapsulation layer 203 close to the back of the chip 202 to expose the back of the chip 202 .
  • a second rewiring layer 207 is formed on the backside of the chip 202 through an electroplating process.
  • the second rewiring layer 207 covers the backside of the chip 202 and covers the surface of the deep hole 205 .
  • the second rewiring layer 207 is connected to the second rewiring layer 207 .
  • the wiring layer 204 is electrically connected.
  • the method of forming the second rewiring layer 207 includes: forming a seed layer on the first plastic layer 203, and the seed layer covers the inner surface of the deep hole 205; forming a patterned mask layer on the seed layer, and then performing a pattern plating process.
  • An electroplating material layer is formed; the patterned mask layer is removed, and part of the seed layer is removed by etching to form the second rewiring layer 207 .
  • a second plastic sealing layer 208 is formed.
  • the second plastic sealing layer 208 covers the second rewiring layer 207 and the surface of the first plastic sealing layer 203 away from the front surface of the chip 202 , and fills the deep hole 205 .
  • the method of using panel-level deep hole drilling and electroplating interconnection that is, using deep hole laser plating process to achieve interconnection, will have the following limitations: (1) Due to laser drilling, especially when drilling deep holes, the upper and lower apertures of the opening cannot be made. into the same size, so the hole wall will have a larger inclination angle. When the upper hole diameter is constant, the greater the thickness of the plastic sealing layer, the smaller the bottom hole.
  • the thickness of the plastic sealing layer exceeds 500 microns, the flowable cross-sectional area of the deep hole will It cannot meet the product requirements, and the thickness of the plastic sealing layer mainly depends on the thickness of the chip. Therefore, limited by the laser capability, the thickness of the packaged chip cannot be too thick. Usually the thickness of the chip needs to be below 500 microns, which has a greater impact on product diversity.
  • this embodiment provides a panel-level fan-out type double-sided interconnection packaging method.
  • the packaging method for panel-level fan-out double-sided interconnection proposed by the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are in a very simplified form and use imprecise proportions, and are only used to conveniently and clearly assist in explaining the embodiments of the present invention.
  • Figure 11 shows a packaging method for panel-level fan-out double-sided interconnection according to an embodiment of the present invention.
  • the packaging method of panel-level fan-out double-sided interconnection in this embodiment includes:
  • the interconnector includes a conductive structure and a plastic packaging material isolating the conductive structure, and both opposite end surfaces of the interconnector expose part of the conductive structure;
  • S3 form a first plastic sealing layer on the top surface of the third carrier board, and the first plastic sealing layer covers at least the side of the chip and the side of the interconnect;
  • S4 Form a first rewiring layer electrically connected to the front side of the chip and the interconnection body, and form a second rewiring layer electrically connected to the back side of the chip and the interconnection body.
  • steps in the flowchart of FIG. 11 are shown in sequence as indicated by arrows, these steps are not necessarily executed in the order indicated by arrows. Unless explicitly stated in this article, there is no strict order restriction on the execution of these steps, and these steps can be executed in other orders. Moreover, at least some of the steps in Figure 11 may include multiple steps or stages. These steps or stages are not necessarily executed at the same time, but may be executed at different times. The execution order of these steps or stages is also It does not necessarily need to be performed sequentially, but may be performed in turn or alternately with other steps or at least part of steps or stages in other steps.
  • FIGS. 12 to 25 are schematic step-by-step structural diagrams of a panel-level fan-out double-sided interconnection packaging method according to an embodiment of the present invention.
  • Figures 12 to 17 and Figures 19 to 25 are schematic cross-sectional structural views
  • Figure 18 is a schematic plan view.
  • the panel-level fan-out of this embodiment will be described below in conjunction with Figures 12 to 25.
  • the packaging method of type double-sided interconnection is explained.
  • an interconnect 305 is provided.
  • the interconnect 305 is pre-made before packaging the chip, and the number of the provided interconnect 305 can be multiple.
  • the interconnect 305 includes a conductive structure and a molding material isolating the conductive structure.
  • the conductive structure in the interconnect 305 includes conductive pillars 304 .
  • the method of providing the interconnection 305 may include steps S11 to S16.
  • Substep S11 As shown in Figure 12, a first carrier board 300a is provided, and a plastic sealing plate 302 is formed on the top surface of the first carrier board 300a, with the back side of the plastic sealing board 302 facing the first carrier board 300a. Specifically, a first adhesive layer 301a is provided between the first carrier plate 300a and the plastic sealing plate 302, that is, the plastic sealing plate 302 is pasted on the first carrier plate 300a through the first adhesive layer 301a.
  • the "adhesive layer” mentioned in this application is a "debondable adhesive layer".
  • the first carrier plate 300a and the plastic sealing plate 302 fixed by the first adhesive layer 301a can subsequently be connected to each other. Detach.
  • Step S12 As shown in FIG. 13, a conductive layer 303 is formed, and the conductive layer 303 covers the front surface of the plastic sealing plate 302.
  • the formation method of the conductive layer 303 may include: forming a thin film layer on the front side of the plastic sealing plate 302 through a sputtering process or a chemical plating process.
  • the thin film layer is, for example, a titanium layer or a copper layer or a titanium-copper layer, and then electroplating on the thin film layer. Copper forms a conductive layer 303 of a set thickness.
  • the conductive layer 303 with a certain thickness can be formed quickly, which helps to ensure the conductive effect of the conductive layer 303.
  • the thin film layer is electroplated with copper; but it is not limited to this. In other embodiments, the thin film layer is electroplated with nickel or other metals.
  • the conductive layer 303 may also be formed only through a sputtering process or a chemical plating process.
  • Sub-step S13 As shown in Figure 14, set a second carrier plate 300b on the side of the conductive layer 303 away from the plastic sealing plate 302, and remove the first carrier plate 300a and the first adhesive layer 301a to expose The back side of the plastic sealing board 302 .
  • a second adhesive layer 301b may be disposed between the second carrier plate 300b and the conductive layer 303.
  • a plurality of conductive holes 302 a are formed in the plastic sealing plate 302 , and the plurality of conductive holes 302 a penetrate the plastic sealing plate 302 and expose part of the conductive layer 303 .
  • a plurality of the conductive holes 302a can be formed by opening holes from the side of the plastic sealing plate 302 away from the second carrier plate 300b toward the second carrier plate 300b through a laser process, and the conductive layer 303 can be used as a base for laser openings.
  • Material i.e. barrier layer).
  • Sub-step S15 As shown in Figure 15, using the conductive layer 303 as a conductive seed layer, electroplating from the bottom of the plurality of via holes 302a toward the hole openings forms the plurality of conductive pillars 304. The conductive pillars 304 fills the corresponding via hole 302a.
  • the method of electroplating to form the multiple conductive pillars 304 from the bottoms of the multiple via holes 302a toward the openings may include: Layer 303 serves as a conductive seed layer, and is electroplated from the bottoms of the plurality of via holes 302a toward the openings to form an electroplating material layer, and the electroplating material layer protrudes from the openings of the via holes 302a; using methods including but not limited to grinding The portion of the plating material layer protruding from the opening of the via hole 302a is removed to form a plurality of conductive pillars 304.
  • the method of forming the plurality of conductive pillars 304 may include: using the conductive layer 303 as a conductive seed layer, electroplating from the bottom of the plurality of via holes 302a toward the hole opening to form an electroplating material layer, and the electroplating material layer
  • the via holes 302a are not filled; grinding removes part of the thickness of the plastic board 302 to reduce the depth of the via holes 302a so that the plating material layers in all via holes 302a are flush with the back of the plastic board. During the grinding process , part of the thickness of the layer of electroplated material can be removed.
  • Step S16 As shown in Figures 16 and 17, remove the second carrier board 300b, the second adhesive layer 301b and the conductive layer 303, cut the plastic board 302, and form a plurality of interconnectors 305 (also known as " Internet dummy die").
  • the conductive layer 303 can be polished and removed using a chemical mechanical polishing process. But it is not limited to this, other suitable processes can be selected to remove the conductive layer 303 according to the material of the conductive layer 303 .
  • the cross-sectional shape of the conductive pillars 304 in the interconnect 305 may be circular. But it is not limited thereto.
  • the cross-sectional shape of the conductive pillar 304 may also be square or elliptical.
  • the size of the interconnect 305 (such as length, width and height) and the size of the conductive pillars 304 inside it can be designed according to product requirements, and the number of conductive pillars 304 in the interconnect 305 can also be set as needed. Try to make it as easy as possible during the design process.
  • the interconnector 305 can meet the needs of most double-sided conduction products, which will help increase the applicable scope of the interconnector 305.
  • the conductive structure in the interconnect includes interconnected multi-layer circuit pattern layers; with reference to Figures 26 to 31, a method of providing an interconnect may include:
  • a plastic sealing board 302 is provided, and the plastic sealing board 302 has an opposite front and a back; a first circuit pattern layer 312 is formed on the front surface 3021 of the plastic sealing board.
  • the first circuit pattern layer 312 includes a plurality of A conductive pad (Pad), which can be interconnected with one end of the chip later;
  • a plurality of first via holes 313 are formed in the plastic board 302 , and the plurality of first via holes 313 penetrate the plastic board 302 and expose part of the first circuit pattern layer. 312;
  • the plurality of first conductive pillars 314 are formed by electroplating from the bottom of the plurality of first via holes 313 toward the hole openings.
  • the first conductive pillars 314 The corresponding first via hole 313 is filled and the top surface of the first conductive pillar 314 is flush with the back surface 3022 of the plastic board;
  • a second circuit pattern layer 315 is formed on the back surface 3022 of the plastic sealing board, and the second circuit pattern layer 315 is connected to the plurality of first conductive pillars 314;
  • a plastic sealing material layer 316 covering the second circuit pattern layer 315 can be formed by lamination or pressing, and a plurality of second via holes 317 are formed in the plastic sealing material layer 316 . Each second via hole 317 exposes part of the second circuit pattern layer 315;
  • a plurality of second conductive pillars 318 are formed by electroplating from the bottoms of the plurality of second via holes 317 toward the hole openings.
  • the second conductive pillars 318 The corresponding second via holes 317 are filled, and a third circuit pattern layer 319 is formed on the surface of the plastic sealing material layer 316 facing away from the second circuit pattern layer 315.
  • the third circuit pattern layer 319 is connected to the The plurality of second conductive pillars 318 are connected;
  • a cutting process is performed to form a plurality of interconnected bodies. Specifically, divide the plastic sealing board 302, the plastic sealing material layer 316, the first circuit pattern layer 312, the plurality of first conductive pillars 314, the second circuit pattern layer 315, the plurality of second conductive pillars 318 and the third circuit pattern layer 319, Multiple interconnections are formed.
  • An interconnect may be formed that includes interconnected multi-layer line pattern layers.
  • the pattern of the line pattern layer in the interconnect is not limited to the pattern shown in Fig. 31.
  • the conductive pillars in the above-mentioned interconnects are all formed by reverse conduction plating.
  • the so-called reverse Surface conduction plating refers to a plating method that uses the conductive layer at the bottom of the via hole as a conductive seed layer and plating from the bottom of the via hole toward the hole opening to form a conductive pillar that fills the via hole.
  • Traditional chemical plating and electroplating can only plate copper on the walls of deep holes and cannot fill the entire hole.
  • This application uses reverse conduction plating to form conductive pillars in the interconnect, so that the conductive pillars can completely cover the conductive holes.
  • Filling and leveling ensures that the cross-sectional area of the conductive material (such as copper) in the hole meets the requirements, so that each interconnect has good flow capacity and can also avoid
  • conductive material such as copper
  • each interconnect has good flow capacity and can also avoid
  • deep-hole laser plating it can avoid a series of problems that affect product performance and yield, such as dry film residue at the bottom of deep-hole plating holes, discontinuous copper in the holes, inability of plating to fill deep holes, and frame-like implantation, etc. It is conducive to establishing a stable interconnection channel and improving product yield.
  • the packaging method of the panel-level fan-out double-sided interconnection of the present application will be described below by taking the interconnection body 305 in FIG. 17 as an example. But it is not limited to this, the interconnector can also be other structures.
  • step S2 is performed. As shown in FIG. 19 , the chip 306 and the interconnect 305 are pasted on the top surface of the third carrier 300 c. One end surface of the interconnect 305 is pasted on the third carrier board 300c, wherein one end surface of the conductive pillar 304 is also pasted on the third carrier board 300c.
  • a third adhesive layer 301c is formed on the third carrier board 300c, and the chip 306 and the interconnect 305 are fixed to the third carrier board 300c through the third adhesive layer 301c.
  • the third adhesive layer 301c is a debondable adhesive layer.
  • Chip pins 306a are formed on the front side of the chip 306.
  • the backside of chip 306 is a contact pad.
  • the number of chips 306 and interconnects 305 pasted on the third carrier board 300c is multiple.
  • step S2 the front side of the chip 306 is directed toward the third carrier plate 300c, that is, the chip 306 is pasted face down on the top surface of the third carrier plate 300c.
  • the chip 306 can also be pasted on the top surface of the third carrier 300c with the back side facing downward.
  • Step S3 is performed to form a first plastic sealing layer on the top surface of the third carrier board 300c.
  • the first plastic sealing layer covers at least the side of the chip 306 and the side of the interconnect 305.
  • the first plastic encapsulation layer 307 is formed to cover the top surface of the third carrier 300 c , the back surface of the chip 306 and the other end surface of the interconnect 305 .
  • the first plastic sealing layer 307 can be formed by lamination.
  • thermal expansion coefficient of the material of the first plastic sealing layer 307 and the thermal expansion coefficient of the plastic sealing material in the interconnection body 305 can be similar.
  • the physical and chemical properties of the plastic packaging material in the interconnect 305 and the first plastic packaging layer 307 can be the same.
  • the material of the first plastic sealing layer 307 is the same as the material of the plastic sealing material in the interconnect 305 , for example, they can both be epoxy resin molding compound (MC-Epoxy Molding Compound, EMC).
  • the chip 306 is pasted face down on the third carrier board 300c, and the chip pins 306a on the front surface of the chip 306 can be exposed after removing the third carrier board 300c and the third adhesive layer 301c. There is no need to grind the first plastic encapsulation layer 307, so that the front side of the chip 306 can be effectively protected, which is beneficial to improving the packaging yield.
  • step S3 a first rewiring layer electrically connected to the front surface of the chip 306 and the interconnect 305 is formed.
  • the third carrier board 300c and the third adhesive layer 301c are removed to expose the chip pins 306a on the front side of the chip 306 and one end surface of the interconnect 305 .
  • a fourth adhesive layer 301d can be sequentially provided on the front surface 3071 of the first plastic sealing layer. and fourth carrier plate 300d.
  • a first rewiring layer 308 is formed on the front side of the chip 306.
  • the first rewiring layer 308 is in contact with the chip pins 306a and the conductive structures (such as conductive pillars 304) of the interconnect 305. connect.
  • the chip 306 Before forming the first rewiring layer 308, the chip 306 may be turned over so that the front side of the chip 306 faces upward.
  • the method of forming the first rewiring layer 308 may include: forming a seed layer covering the backside 3072 of the first molding layer, the chip pins 306a and the end surfaces of the interconnect 305; on the seed layer A patterned mask layer is formed, and the patterned mask layer is used as a mask to perform electroplating to form an electroplating layer; the patterned mask layer is removed, and the exposed seed layer is etched to form the first rewiring layer 308 .
  • the material of the first rewiring layer 308 may include copper.
  • a second plastic encapsulation layer 309 may be formed on the front side of the chip 306 , and the second plastic encapsulation layer 309 covers the first rewiring layer 308 and The back side 3072 of the first molding layer (that is, the surface of the first molding layer 307 close to the first rewiring layer 308).
  • the material of the second plastic sealing layer 309 is the same as the material of the first plastic sealing layer 307 .
  • the second plastic sealing layer 309 can be formed by lamination.
  • the fifth adhesive layer 301e and the fifth carrier plate 300e are sequentially provided on the surface of the second plastic sealing layer 309 facing away from the first plastic sealing layer 307; remove The fourth carrier plate 300d and the fourth adhesive layer 301d expose the front side 3071 of the first plastic sealing layer.
  • a second rewiring layer electrically connected to the backside of the chip 306 and the interconnect 305 is formed. It should be noted that this application takes the example of forming the first rewiring layer 308 first and then forming the second rewiring layer. However, it is not limited to this. The first rewiring layer 308 can also be formed after the second rewiring layer is formed. .
  • the original thickness of the interconnect 305 is greater than the original thickness of the chip 306 .
  • Forming a second rewiring layer electrically connected to the back side of the chip 306 and the interconnect 305 includes: as shown in Figure 23, grinding the front side 3071 of the first plastic encapsulation layer, that is, grinding the first plastic encapsulation layer 307 away from the front side of the chip 306 surface, remove part of the thickness of the first plastic sealing layer 307 to expose the other end surface of the interconnect 305; as shown in Figure 24, a blind hole 310 is formed in the first plastic sealing layer, and the blind hole 310 exposes the chip 306 Part of the backside; as shown in Figure 25, a second rewiring layer 311 electrically connected to the backside of the chip 306 and the interconnect 305 is formed.
  • the second rewiring layer 311 fills the blind hole 310 and covers the inner surface of the blind hole 310. .
  • part of the thickness of the interconnect 305 can also be ground and removed, so that the remaining first plastic layer on the back of the chip 306
  • the thickness is within the set range, which helps to reduce the depth of the blind hole 310 and reduce the thickness of the product.
  • the grinding surface of the first plastic sealing layer 307 is at a certain distance from the back of the chip 306, which can effectively protect the chip 306. back.
  • the original thickness of the interconnect 305 is greater than the original thickness of the chip 306 .
  • formed with The second rewiring layer 311 electrically connected to the back of the chip 306 and the interconnect 305 includes: grinding the front 3071 of the first plastic layer to remove part of the thickness of the first plastic layer 307 to expose the interconnect 305 The other end face; continue to grind the first plastic encapsulation layer 307 and the other end face of the interconnector 305 until the backside of the chip 306 is exposed; form a third electrically connected backside of the chip 306 and the interconnection body 305 Second rewiring layer 311.
  • the original thickness of the interconnect 305 is equal to the original thickness of the chip 306 .
  • Forming the second rewiring layer 311 electrically connected to the backside of the chip 306 and the interconnect 305 includes: grinding the front side 3071 of the first plastic encapsulation layer to remove part of the thickness of the first plastic encapsulation layer 307 while exposing all The back surface of the chip 306 and the other end surface of the interconnect 305 form a second rewiring layer 311 electrically connected to the back surface of the chip 306 and the interconnect 305 .
  • the original thickness of the interconnect 305 is smaller than the original thickness of the chip 306 .
  • Forming the second rewiring layer 311 electrically connected to the backside of the chip 306 and the interconnect 305 includes: grinding the front side 3071 of the first plastic encapsulation layer to remove part of the thickness of the first plastic encapsulation layer 307 to expose the The back side of the chip 306; and continue to grind the front side 3071 of the first plastic sealing layer and the back side of the chip 306 to expose the other end surface of the interconnect 305; forming an electrical connection with the back side of the chip 306 and the interconnect 305.
  • the backside of the chip 306 needs to be allowed to be ground, otherwise grinding the backside of the chip may cause the chip to be scrapped.
  • the panel-level fan-out double-sided interconnection packaging method of this embodiment may also include: forming a third plastic encapsulation layer (not shown in the figure), a third The plastic encapsulation layer covers the second rewiring layer 311.
  • FIG. 32 is a schematic diagram of a semiconductor structure packaged using a panel-level fan-out double-sided interconnection packaging method according to an embodiment of the present invention.
  • the multiple interconnects include a plurality of first interconnects 320 and a plurality of second interconnects 321.
  • a plurality of interconnects are formed on the back side of the chip 306. After the second rewiring layer 311, a portion of the chips 306 are electrically connected to the corresponding first interconnects 320 or the second interconnects 321, and a portion of the chips 306 are electrically connected to the corresponding first interconnects 320 and the second interconnects 321. connect. But it is not limited to this.
  • each chip has a corresponding first interconnect 320 and a second interconnect 321; after forming the second rewiring layer 311 on the back side of the chip 306, each chip 306 with the corresponding first interconnect 320 and The second interconnect 321 is electrically connected.
  • the number of interconnects corresponding to the chip 306 is not limited to one or two, but can also be three or more.
  • the types of interconnects corresponding to the chip 306 are not limited to one or two types, but may also be three or more types.
  • the panel-level fan-out double-sided interconnection packaging method of the present application has the following advantages: (1) In the existing technology, the deep-hole laser plating technology is limited by too many conditions and factors, which affects the product yield. If it is too large and has low flow capacity, it will easily lead to chip scrapping; this application uses pre-prepared interconnects to realize double-sided interconnection of chip 306, which can avoid the use of traditional deep-hole laser plating to achieve double-sided interconnection, thereby avoiding deep holes.
  • Bond method is pasted on the top surface of the third carrier board 300c, so that multiple interconnectors produced at one time can be used for several batches of chip packaging, and the plastic sealing layer on each carrier board with the chip 306 pasted is avoided, that is,
  • the first plastic encapsulation layer 307 is subjected to deep-hole laser plating, which ensures the stability of the interconnection channels in the package and greatly speeds up the processing speed of chip packaging, which is beneficial to shortening the packaging cycle and improving production efficiency; (3) Versatility of the interconnector Strong, the same interconnect can be used for similar products. There is no need to design a specific interconnect for each product.
  • the interconnects produced in advance can be of any thickness, part of the thickness of the interconnects can also be removed during the packaging process, thereby adapting to the needs of different chips 306, so that the chip thickness is not limited during the packaging process.
  • the encapsulation structure can be formed using the above-mentioned panel-level fan-out double-sided interconnection encapsulation method.
  • the encapsulation structure includes a chip 306 , an interconnect 305 , a first plastic encapsulation layer 307 , a first rewiring layer 308 and a second rewiring layer 311 .
  • the interconnector 305 and the first plastic encapsulation layer 307 are formed in different steps.
  • the interconnect 305 includes a conductive structure 304 and a plastic encapsulation material isolating the conductive structure 304. Part of the conductive structure 304 is exposed on two opposite end surfaces of the interconnect 305.
  • first plastic sealing layer 307 covers at least the sides of the chip 306 and the sides of the interconnect 305 .
  • the first rewiring layer 308 is located on the back side 3072 of the first plastic encapsulation layer and is electrically connected to the front side of the chip 306 and the interconnect 305 .
  • the second rewiring layer 311 is located on the front side 3071 of the first plastic encapsulation layer and is electrically connected to the back side of the chip 306 and the interconnect 305 .

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Abstract

The present invention provides a panel-level fan-out double-sided interconnection packaging method. The packaging method comprises: providing an interconnect, the interconnect comprising a conductive structure and a plastic packaging material; attaching a chip and the interconnect to the top surface of a third carrier board, one end surface of the interconnect being attached to the third carrier board; forming a first plastic packaging layer on the top surface of the third carrier board, the first plastic packaging layer at least coating the side surface of the chip and the side surface of the interconnect; and forming a first rewiring layer electrically connected to the front surface of the chip and the interconnect, and forming a second rewiring layer electrically connected to the back surface of the chip and the interconnect. Thus, double-sided interconnection of the chip can be achieved by avoiding the manner of traditional deep-hole laser electroplating, and a packaging period can be shortened. The present invention also provides an encapsulation structure and a preparation method for an interconnect for semiconductor packaging.

Description

面板级扇出型双面互联的封装方法和包封结构Encapsulation method and encapsulation structure of panel-level fan-out double-sided interconnection 技术领域Technical field
本发明涉及半导体封装技术领域，特别涉及一种面板级扇出型双面互联的封装方法、一种包封结构和一种用于半导体封装的互联体的制备方法。The present invention relates to the technical field of semiconductor packaging, and in particular to a packaging method for panel-level fan-out double-sided interconnection, an packaging structure and a method for preparing an interconnect for semiconductor packaging.
背景技术Background technique
双面互联产品在扇出型(Fan-out)封装中，常使用引线框架(Lead Frame)或预制PCB基板等方式进行芯片正反面的导通。In fan-out packages, double-sided interconnect products often use lead frames or prefabricated PCB substrates to connect the front and back sides of the chip.
图1示出了一种采用Copper clip工艺封装的半导体结构。参考图1，传统封装中采用引线框架100作为载板，将芯片101背面通过焊料102焊接在引线框架100上，再通过引线键合的方式(例如通过铜片103)将芯片101正面的芯片引脚(pad)与引线框架100的引脚相连，形成双面导通的结构，然后再使用塑封材料104将芯片101和引线框架100包裹封装成为一个整体。Figure 1 shows a semiconductor structure packaged using the Copper clip process. Referring to Figure 1, a lead frame 100 is used as a carrier board in a traditional package. The back side of the chip 101 is welded to the lead frame 100 through solder 102, and then the chip lead on the front side of the chip 101 is wire bonded (for example, through a copper sheet 103). The pads are connected to the pins of the lead frame 100 to form a double-sided conductive structure, and then the chip 101 and the lead frame 100 are packaged as a whole using a plastic packaging material 104 .
但是，传统的封装工艺存在着封装体可靠性优势不高，性能表现不佳等一系列的问题；而且，由于每个产品必须设计对应的引线框架，产品迭代困难。However, the traditional packaging process has a series of problems such as low package reliability and poor performance. Moreover, because each product must design a corresponding lead frame, product iteration is difficult.
使用面板级扇出型封装工艺制作双面互联产品时，由于工艺方法的差异，即由上述传统封装中将芯片焊接在引线框架上转变为将芯片可被剥离的粘合在载板上，引线框架结构不适用于面板级扇出型封装，所以芯片正反面的互联通常采用镭射开孔和深孔电镀互联的方式(即深孔镭射电镀的方式)进行，这类方式对于镭射加工和电镀工艺要求极高，且限制因素众多，例如限制孔径和孔深需在一定范围等等，另一方面在加工单片产品时，镭射和电镀深孔所耗费时间长，无法实现大规模以及高良率的量产。When using the panel-level fan-out packaging process to make double-sided interconnected products, due to the difference in process methods, the chip is welded to the lead frame in the above-mentioned traditional package to the chip can be peeled off and bonded to the carrier board, and the leads The frame structure is not suitable for panel-level fan-out packaging, so the interconnection between the front and back of the chip is usually carried out by laser drilling and deep-hole electroplating interconnection (that is, deep-hole laser plating). This type of method is very important for laser processing and electroplating processes. The requirements are extremely high and there are many limiting factors, such as limiting the hole diameter and hole depth to a certain range. On the other hand, when processing single-piece products, laser and electroplating deep holes take a long time, making it impossible to achieve large-scale and high-yield processing. mass production.
发明内容Contents of the invention
本发明的目的是提供一种面板级扇出型双面互联的封装方法、一种包封结构和一种用于半导体封装的互联体的制备方法，可以避免采用传统镭射开孔和深孔电镀的方式实现双面互联，且可以缩短封装周期，提高生产效率。 The object of the present invention is to provide a panel-level fan-out type double-sided interconnection packaging method, an packaging structure and a preparation method of interconnectors for semiconductor packaging, which can avoid the use of traditional laser drilling and deep hole electroplating. This method achieves double-sided interconnection, shortens the packaging cycle and improves production efficiency.
为了实现上述目的，本发明一方面提供一种面板级扇出型双面互联的封装方法。所述封装方法包括：In order to achieve the above object, on the one hand, the present invention provides a packaging method for panel-level fan-out double-sided interconnection. The packaging method includes:
提供互联体和第三载板，所述互联体包括导电结构和隔离所述导电结构的塑封材料，所述互联体的两个相对端面均露出部分所述导电结构；Provide an interconnection body and a third carrier board, the interconnection body includes a conductive structure and a plastic packaging material isolating the conductive structure, and both opposite end surfaces of the interconnection body expose part of the conductive structure;
将芯片和所述互联体粘贴在所述第三载板的顶面上，所述互联体的一端面粘贴在所述第三载板上；Paste the chip and the interconnect on the top surface of the third carrier board, and paste one end surface of the interconnect on the third carrier board;
在所述第三载板顶面形成第一塑封层，所述第一塑封层至少包覆所述芯片的侧面以及所述互联体的侧面；以及A first plastic sealing layer is formed on the top surface of the third carrier board, and the first plastic sealing layer covers at least the side of the chip and the side of the interconnect; and
形成与所述芯片正面和所述互联体电连接的第一再布线层，以及形成与所述芯片背面和所述互联体电连接的第二再布线层。A first rewiring layer electrically connected to the chip front side and the interconnect body is formed, and a second rewiring layer electrically connected to the chip back side and the interconnect body is formed.
可选的，所述将芯片和所述互联体粘贴在所述第三载板的顶面上，包括：使所述芯片的正面朝向所述第三载板；Optionally, pasting the chip and the interconnect on the top surface of the third carrier board includes: making the front side of the chip face the third carrier board;
所述形成与所述芯片正面和所述互联体电连接的第一再布线层，包括：去除所述第三载板，露出所述芯片正面上的芯片引脚以及所述互联体的一端面；在所述芯片的正面一侧形成第一再布线层，所述第一再布线层与所述芯片引脚和所述导电结构相连接。The forming a first rewiring layer electrically connected to the chip front and the interconnect includes: removing the third carrier board to expose the chip pins on the chip front and one end surface of the interconnect ; A first rewiring layer is formed on the front side of the chip, and the first rewiring layer is connected to the chip pins and the conductive structure.
可选的，所述导电结构包括导电柱；所述提供互联体的方法包括：提供第一载板，并在所述第一载板的顶面形成塑封板，所述塑封板的背面朝向所述第一载板；形成导电层，所述导电层覆盖所述塑封板的正面；在所述导电层远离所述塑封板的一侧设置第二载板，并去除所述第一载板，露出所述塑封板的背面；在所述塑封板中形成多个导通孔，所述多个导通孔贯穿所述塑封板且露出部分所述导电层；以所述导电层作为导电种子层，从所述多个导通孔的孔底朝向孔口电镀形成所述多个导电柱，所述导电柱填满对应的所述导通孔；以及去除所述第二载板和所述导电层，切割所述塑封板，形成多个所述互联体。Optionally, the conductive structure includes conductive pillars; the method of providing an interconnection includes: providing a first carrier board, and forming a plastic sealing board on the top surface of the first carrier board, with the back side of the plastic sealing board facing the The first carrier board; forming a conductive layer, the conductive layer covering the front side of the plastic sealing board; setting a second carrier board on the side of the conductive layer away from the plastic sealing board, and removing the first carrier board, Expose the back side of the plastic sealing board; form a plurality of via holes in the plastic sealing board, the plurality of via holes penetrate the plastic sealing board and expose part of the conductive layer; use the conductive layer as a conductive seed layer , forming the plurality of conductive pillars by electroplating from the bottom of the plurality of via holes toward the hole openings, and the conductive pillars fill the corresponding via holes; and removing the second carrier plate and the conductive pillars layer, cutting the plastic board to form a plurality of interconnected bodies.
可选的，所述以所述导电层作为导电种子层，从所述多个导通孔的孔底朝向孔口电镀形成所述多个导电柱，包括：以所述导电层作为导电种子层，从所述多个导通孔的孔底朝向孔口电镀形成电镀材料层，且所述电镀材料层 凸出所述导通孔的孔口；以及去除所述电镀材料层凸出于所述导通孔孔口的部分，形成所述多个导电柱。Optionally, using the conductive layer as a conductive seed layer and electroplating from the bottom of the plurality of via holes toward the hole openings to form the plurality of conductive pillars includes: using the conductive layer as a conductive seed layer. , an electroplating material layer is formed by electroplating from the bottom of the plurality of via holes toward the hole opening, and the electroplating material layer Protruding the opening of the via hole; and removing the portion of the electroplating material layer protruding from the opening of the via hole to form the plurality of conductive pillars.
可选的，所述导电结构包括互联的多层线路图形层；所述提供互联体的方法包括：提供塑封板，所述塑封板具有相对的正面和背面；在所述塑封板的正面形成第一线路图形层；在所述塑封板中形成多个第一导通孔，所述多个第一导通孔贯穿所述塑封板且均露出部分所述第一线路图形层；以所述第一线路图形层作为导电种子层，从所述多个第一导通孔的孔底朝向孔口电镀形成所述多个第一导电柱，所述第一导电柱填满对应的所述第一导通孔；在所述塑封板的背面形成第二线路图形层，所述第二线路图形层与所述多个第一导电柱相连接；形成覆盖所述第二线路图形层的塑封材料层；在所述塑封材料层中形成多个第二导通孔，所述多个第二导通孔均露出部分所述第二线路图形层；以所述第二线路图形层作为导电种子层，从所述多个第二导通孔的孔底朝向孔口电镀形成所述多个第二导电柱，所述第二导电柱填满对应的所述第二导通孔；在所述塑封材料层背向所述第二线路图形层的表面形成第三线路图形层，所述第三线路图形层与所述多个第二导电柱相连接；以及执行切割工艺，形成多个所述互联体。Optionally, the conductive structure includes an interconnected multi-layer circuit pattern layer; the method of providing an interconnection includes: providing a plastic sealing board, the plastic sealing board having an opposite front and a back; forming a third layer on the front of the plastic sealing board. A circuit pattern layer; forming a plurality of first via holes in the plastic sealing board, the plurality of first via holes penetrating the plastic sealing board and exposing part of the first circuit pattern layer; A circuit pattern layer serves as a conductive seed layer. The plurality of first conductive pillars are electroplated from the bottom of the plurality of first via holes toward the hole opening. The first conductive pillars fill the corresponding first conductive pillars. Through holes; forming a second circuit pattern layer on the back of the plastic sealing board, the second circuit pattern layer being connected to the plurality of first conductive pillars; forming a plastic sealing material layer covering the second circuit pattern layer ; Forming a plurality of second via holes in the plastic sealing material layer, each of the plurality of second via holes exposing part of the second circuit pattern layer; using the second circuit pattern layer as a conductive seed layer, The plurality of second conductive pillars are formed by electroplating from the bottoms of the plurality of second via holes toward the hole openings, and the second conductive pillars fill the corresponding second via holes; in the plastic packaging material A third circuit pattern layer is formed on a surface of the layer facing away from the second circuit pattern layer, and the third circuit pattern layer is connected to the plurality of second conductive pillars; and a cutting process is performed to form a plurality of interconnections. .
可选的，所述在所述塑封材料层背向所述第二线路图形层的表面形成第三线路图形层之后，重复执行形成塑封材料层、形成导通孔、在导通孔中形成导电柱、以及在塑封材料层上形成线路图形层的步骤，以形成多层的互联体。Optionally, after forming the third circuit pattern layer on the surface of the molding material layer facing away from the second circuit pattern layer, repeatedly forming the molding material layer, forming the via hole, and forming the conductive layer in the via hole pillars, and the step of forming a circuit pattern layer on the plastic material layer to form a multi-layer interconnect.
可选的，所述在所述第三载板顶面形成第一塑封层，所述第一塑封层至少包覆所述芯片的侧面以及所述互联体的侧面，包括：形成第一塑封层，所述第一塑封层覆盖所述第三载板的顶面、所述芯片的侧面和背面以及所述互联体的侧面和另一端面。Optionally, forming a first plastic layer on the top surface of the third carrier board, the first plastic layer covering at least the side of the chip and the side of the interconnect includes: forming the first plastic layer , the first plastic encapsulation layer covers the top surface of the third carrier board, the side and back of the chip, and the side and other end surface of the interconnect.
可选的，所述互联体的原始厚度大于所述芯片的原始厚度；所述形成与所述芯片背面和所述互联体电连接的第二再布线层，包括：研磨所述第一塑封层远离所述芯片正面的表面去除所述第一塑封层的部分厚度，同时去除所述互联体的部分厚度，露出所述互联体的另一端面，在所述第一塑封层中形 成盲孔，所述盲孔露出所述芯片的部分背面，以及形成与所述芯片背面和所述互联体电连接的第二再布线层，所述第二再布线层填充所述盲孔且覆盖所述盲孔的内表面；Optionally, the original thickness of the interconnect is greater than the original thickness of the chip; forming a second rewiring layer electrically connected to the back side of the chip and the interconnect includes: grinding the first plastic encapsulation layer Remove part of the thickness of the first plastic encapsulation layer from the surface away from the front surface of the chip, and simultaneously remove part of the thickness of the interconnect body, exposing the other end surface of the interconnect body, and forming a shape in the first plastic encapsulation layer. forming a blind hole, the blind hole exposing part of the backside of the chip, and forming a second rewiring layer electrically connected to the backside of the chip and the interconnect, the second rewiring layer filling the blind hole and Cover the inner surface of the blind hole;
或者，or,
所述互联体的原始厚度等于所述芯片的原始厚度；所述形成与所述芯片背面和所述互联体电连接的第二再布线层，包括：研磨所述第一塑封层远离所述芯片正面的表面去除所述第一塑封层的部分厚度，同时露出所述芯片的背面以及所述互联体的另一端面，形成与所述芯片背面和所述互联体电连接的第二再布线层；The original thickness of the interconnect is equal to the original thickness of the chip; forming a second rewiring layer electrically connected to the back side of the chip and the interconnect includes: grinding the first plastic layer away from the chip The front surface removes part of the thickness of the first plastic encapsulation layer, while exposing the back side of the chip and the other end surface of the interconnect, forming a second rewiring layer electrically connected to the back side of the chip and the interconnect. ;
或者，or,
所述互联体的原始厚度大于所述芯片的原始厚度；所述形成与所述芯片背面和所述互联体电连接的第二再布线层，包括：研磨所述第一塑封层远离所述芯片正面的表面去除所述第一塑封层的部分厚度，露出所述互联体的另一端面；继续研磨所述第一塑封层和所述互联体的另一端面，直至露出所述芯片的背面，形成与所述芯片背面和所述互联体电连接的第二再布线层；The original thickness of the interconnect is greater than the original thickness of the chip; forming a second rewiring layer electrically connected to the backside of the chip and the interconnect includes: grinding the first plastic layer away from the chip Remove part of the thickness of the first plastic sealing layer from the front surface to expose the other end surface of the interconnector; continue grinding the first plastic sealant layer and the other end surface of the interconnector until the backside of the chip is exposed. Forming a second rewiring layer electrically connected to the backside of the chip and the interconnect;
或者，or,
所述互联体的原始厚度小于所述芯片的厚度；所述形成与所述芯片背面和所述互联体电连接的第二再布线层，包括：研磨所述第一塑封层远离所述芯片正面的表面去除所述第一塑封层的部分厚度，露出所述芯片的背面，继续研磨所述芯片的背面和所述第一塑封层，露出所述互联体的另一端面，形成与所述芯片背面和所述互联体电连接的第二再布线层。The original thickness of the interconnect is smaller than the thickness of the chip; forming a second rewiring layer electrically connected to the back of the chip and the interconnect includes: grinding the first plastic layer away from the front of the chip Remove part of the thickness of the first plastic sealing layer from the surface to expose the back of the chip. Continue grinding the back of the chip and the first plastic sealing layer to expose the other end surface of the interconnector to form a connection with the chip. A second redistribution layer electrically connected to the interconnect on the back side.
可选的，所述第一塑封层的材质和所述互联体中塑封材料的材质相同。Optionally, the material of the first plastic sealing layer is the same as the material of the plastic sealing material in the interconnected body.
可选的，所述芯片和所述互联体的数量均为多个，多个所述互联体包括多个第一互联体和多个第二互联体；所述形成与所述芯片正面和所述互联体电连接的第一再布线层，以及形成与所述芯片背面和所述互联体电连接的第二再布线层之后之后，部分数量的所述芯片与对应的所述第一互联体或所述第二互联体电连接，部分数量的所述芯片与对应的所述第一互联体和所述第二互联体电连接；或者，每颗所述芯片均与对应的所述第一互联体和所述第 二互联体电连接。Optionally, the number of the chips and the interconnects is multiple, and the plurality of interconnects include a plurality of first interconnects and a plurality of second interconnects; the formation is related to the front surface of the chip and the After forming a first rewiring layer electrically connected to the interconnects and a second rewiring layer electrically connected to the backside of the chip and the interconnects, a portion of the chips are connected to the corresponding first interconnects Or the second interconnects are electrically connected, and a part of the chips are electrically connected to the corresponding first interconnects and the second interconnects; or each of the chips is electrically connected to the corresponding first interconnects. The Internet and the Chapter Two interconnections are electrically connected.
本发明另一方面还提供一种包封结构，该包封结构包括芯片、互联体、第一塑封层、第一再布线层和第二再布线层。所述互联体包括导电结构和隔离所述导电结构的塑封材料，所述互联体的两个相对端面均露出部分所述导电结构；所述第一塑封层至少包覆所述芯片的侧面以及所述互联体的侧面；所述互联体和所述第一塑封层在不同的步骤中形成；第一再布线层与所述芯片正面和所述互联体电连接；第二再布线层与所述芯片背面和所述互联体电连接。In another aspect, the present invention also provides an encapsulation structure, which includes a chip, an interconnect, a first plastic encapsulation layer, a first rewiring layer and a second rewiring layer. The interconnection body includes a conductive structure and a plastic packaging material that isolates the conductive structure. Both opposite end surfaces of the interconnection body expose part of the conductive structure; the first plastic packaging layer covers at least the side surface of the chip and the The side of the interconnect; the interconnect and the first plastic encapsulation layer are formed in different steps; the first rewiring layer is electrically connected to the front side of the chip and the interconnect; the second rewiring layer is electrically connected to the interconnect. The backside of the chip is electrically connected to the interconnect.
本发明另一方面还提供一种用于半导体封装的互联体的制备方法，包括：On the other hand, the present invention also provides a method for preparing interconnects for semiconductor packaging, including:
提供第一载板，并在所述第一载板的顶面形成塑封板，所述塑封板的背面朝向所述第一载板；Provide a first carrier board, and form a plastic sealing plate on the top surface of the first carrier board, with the back side of the plastic sealing board facing the first carrier board;
形成导电层，所述导电层覆盖所述塑封板的正面；Forming a conductive layer covering the front surface of the plastic sealing board;
在所述导电层远离所述塑封板的一侧设置第二载板，并去除所述第一载板，露出所述塑封板的背面；A second carrier plate is provided on the side of the conductive layer away from the plastic sealing board, and the first carrier board is removed to expose the back side of the plastic sealing board;
在所述塑封板中形成多个导通孔，所述多个导通孔贯穿所述塑封板且露出部分所述导电层；A plurality of via holes are formed in the plastic packaging board, and the plurality of via holes penetrate the plastic packaging board and expose part of the conductive layer;
以所述导电层作为导电种子层，从所述多个导通孔的孔底朝向孔口电镀形成所述多个导电柱，所述导电柱填满对应的所述导通孔；以及Using the conductive layer as a conductive seed layer, the plurality of conductive pillars are formed by electroplating from the bottom of the plurality of via holes toward the hole openings, and the conductive pillars fill the corresponding via holes; and
去除所述第二载板和所述导电层，切割所述塑封板，形成多个所述互联体。The second carrier board and the conductive layer are removed, and the plastic sealing board is cut to form a plurality of interconnections.
可选的，所述以所述导电层作为导电种子层，从所述多个导通孔的孔底朝向孔口电镀形成所述多个导电柱，包括：Optionally, using the conductive layer as a conductive seed layer, electroplating from the bottom of the plurality of via holes toward the hole openings to form the plurality of conductive pillars includes:
以所述导电层作为导电种子层，从所述多个导通孔的孔底朝向孔口电镀形成电镀材料层，且所述电镀材料层凸出所述导通孔的孔口；以及Using the conductive layer as a conductive seed layer, electroplating from the bottom of the plurality of via holes toward the openings forms an electroplating material layer, and the electroplating material layer protrudes from the openings of the via holes; and
去除所述电镀材料层凸出于所述导通孔孔口的部分，形成所述多个导电柱。The portion of the electroplating material layer protruding from the opening of the via hole is removed to form the plurality of conductive pillars.
本发明另一方面还提供一种用于半导体封装的互联体的制备方法，包括：On the other hand, the present invention also provides a method for preparing interconnects for semiconductor packaging, including:
提供塑封板，所述塑封板具有相对的正面和背面； Provide a plastic sealing board, the plastic sealing board having opposite front and back sides;
在所述塑封板的正面形成第一线路图形层；Form a first circuit pattern layer on the front side of the plastic sealing board;
在所述塑封板中形成多个第一导通孔，所述多个第一导通孔贯穿所述塑封板且均露出部分所述第一线路图形层；A plurality of first via holes are formed in the plastic packaging board, and the plurality of first via holes penetrate the plastic packaging board and expose part of the first circuit pattern layer;
以所述第一线路图形层作为导电种子层，从所述多个第一导通孔的孔底朝向孔口电镀形成所述多个第一导电柱，所述第一导电柱填满对应的所述第一导通孔；Using the first circuit pattern layer as a conductive seed layer, the plurality of first conductive pillars are electroplated from the bottom of the plurality of first via holes toward the hole openings, and the first conductive pillars fill the corresponding the first via hole;
在所述塑封板的背面形成第二线路图形层，所述第二线路图形层与所述多个第一导电柱相连接；A second circuit pattern layer is formed on the back side of the plastic board, and the second circuit pattern layer is connected to the plurality of first conductive pillars;
形成覆盖所述第二线路图形层的塑封材料层；Forming a plastic sealing material layer covering the second circuit pattern layer;
在所述塑封材料层中形成多个第二导通孔，所述多个第二导通孔均露出部分所述第二线路图形层；A plurality of second via holes are formed in the plastic sealing material layer, and each of the plurality of second via holes exposes part of the second circuit pattern layer;
以所述第二线路图形层作为导电种子层，从所述多个第二导通孔的孔底朝向孔口电镀形成所述多个第二导电柱，所述第二导电柱填满对应的所述第二导通孔；Using the second circuit pattern layer as a conductive seed layer, the plurality of second conductive pillars are electroplated from the bottom of the plurality of second via holes toward the hole openings, and the second conductive pillars fill the corresponding the second via hole;
在所述塑封材料层背向所述第二线路图形层的表面形成第三线路图形层，所述第三线路图形层与所述多个第二导电柱相连接；以及A third circuit pattern layer is formed on the surface of the plastic sealing material layer facing away from the second circuit pattern layer, and the third circuit pattern layer is connected to the plurality of second conductive pillars; and
执行切割工艺，形成多个所述互联体。A cutting process is performed to form a plurality of interconnected bodies.
可选的，所述在所述塑封材料层背向所述第二线路图形层的表面形成第三线路图形层之后，重复执行形成塑封材料层、形成导通孔、在导通孔中形成导电柱、以及在塑封材料层上形成线路图形层的步骤，以形成多层的互联体。Optionally, after forming the third circuit pattern layer on the surface of the molding material layer facing away from the second circuit pattern layer, repeatedly forming the molding material layer, forming the via hole, and forming the conductive layer in the via hole pillars, and the step of forming a circuit pattern layer on the plastic material layer to form a multi-layer interconnect.
与现有技术相比，本发明的面板级扇出型双面互联的封装方法、包封结构和用于半导体封装的互联体的制备方法具有以下优势：(1)现有技术中深孔镭射电镀技术受限条件及因素过多，对于产品良率影响过大，且通流能力低，容易导致芯片报废；本申请利用预先制备的互联体实现芯片的双面互联，可以避免采用传统深孔镭射电镀的方式实现双面互联，进而可以避免深孔电镀孔底干膜残留和孔内铜不连续等影响产品性能及良率的问题，有利于建立稳定的互联通道，提高产品良率；(2)现有技术中为了实现双面互联，需对 每张粘贴有芯片的载板上的塑封层进行深孔镭射电镀，生产效率低，而本发明中互联体在芯片封装前提前制作，并且芯片和提前准备的互联体采用贴片(Die Bond)的方式粘贴在第三载板的顶面上，从而一次制作的多个互联体可用于数批芯片封装，且避免了对每张粘贴有芯片的载板上的塑封层进行深孔镭射电镀，保证了封装中互联通道的稳定性并极大地加快了芯片封装的加工速度，有利于缩短封装周期，提高生产效率；(3)互联体的通用性强，针对类似产品可以通用同一种互联体，无需为每种产品设计特定的互联体，只需更改第一再布线层和/或第二再布线层的引线即可，极大地节省了设计成本；(4)因提前制作的互联体可以为任意厚度，还可以在封装过程中去除部分厚度的互联体，从而可以适应不同芯片的需求，使得封装过程中芯片厚度不受限制。Compared with the existing technology, the panel-level fan-out double-sided interconnection packaging method, packaging structure and preparation method of interconnectors for semiconductor packaging of the present invention have the following advantages: (1) Deep hole laser in the existing technology Electroplating technology is limited by too many conditions and factors, which has a great impact on product yield, and the flow capacity is low, which can easily lead to chip scrapping. This application uses pre-prepared interconnects to realize double-sided interconnection of chips, which can avoid the use of traditional deep holes. Laser plating realizes double-sided interconnection, which can avoid problems such as dry film residue at the bottom of deep-hole plating holes and copper discontinuity in the holes that affect product performance and yield. It is conducive to establishing stable interconnection channels and improving product yield; ( 2) In order to achieve double-sided interconnection in the existing technology, it is necessary to The plastic sealing layer on each carrier board with a chip attached is subjected to deep-hole laser plating, which results in low production efficiency. However, in the present invention, the interconnector is made in advance before the chip is packaged, and the chip and the prepared interconnector are die bonded. pasted on the top surface of the third carrier board, so that multiple interconnects produced at one time can be used for several batches of chip packaging, and it avoids the need for deep-hole laser plating of the plastic sealing layer on each carrier board with chips pasted on it. It ensures the stability of the interconnection channel in the package and greatly speeds up the processing speed of chip packaging, which is beneficial to shortening the packaging cycle and improving production efficiency; (3) The interconnector is highly versatile, and the same interconnector can be used for similar products. There is no need to design specific interconnects for each product. You only need to change the leads of the first rewiring layer and/or the second rewiring layer, which greatly saves design costs; (4) Because the interconnects made in advance can Any thickness, and part of the thickness of the interconnect can be removed during the packaging process, thereby adapting to the needs of different chips, so that the chip thickness is not limited during the packaging process.
附图说明Description of drawings
图1为一种采用Copper clip工艺封装的半导体结构。Figure 1 shows a semiconductor structure packaged using the Copper clip process.
图2至图10为一种先进封装工艺的分步骤结构示意图。Figures 2 to 10 are step-by-step structural diagrams of an advanced packaging process.
图11为本发明一实施例的面板级扇出型双面互联的封装方法。Figure 11 shows a packaging method for panel-level fan-out double-sided interconnection according to an embodiment of the present invention.
图12至图25为本发明一实施例的面板级扇出型双面互联的封装方法的分步骤结构示意图。12 to 25 are schematic step-by-step structural diagrams of a panel-level fan-out double-sided interconnection packaging method according to an embodiment of the present invention.
图26至图31为本发明一实施例制作互联体的分步骤剖面结构示意图。26 to 31 are step-by-step cross-sectional structural diagrams of manufacturing interconnects according to an embodiment of the present invention.
图32为利用本发明一实施例的面板级扇出型双面互联的封装方法封装形成的半导体结构示意图。FIG. 32 is a schematic diagram of a semiconductor structure packaged using a panel-level fan-out double-sided interconnection packaging method according to an embodiment of the present invention.
附图标记说明：
(图1)100-引线框架；101-芯片；102-焊料；103-铜片；104-塑封材料；
(图2至图10)200a-第一载板；200b-第二载板；200c-第三载板；201a-
第一粘结层；201b-第二粘结层；201c-第三粘结层；202-芯片；203-第一塑封层；204-第一再布线层；205-深孔；206-盲孔；207-第二再布线层；208-第二塑封层；
(图12至图32)300a-第一载板；300b-第二载板；300c-第三载板；300d-
第四载板；300e-第五载板；301a-第一粘结层；301b-第二粘结层；301c-第三粘结层；301d-第四粘结层；301e-第五粘结层；302-塑封板；3021-塑封板的正面；3022-塑封板的背面；302a-导通孔；303-导电层；304-导电柱；305-互联体；306-芯片；306a-芯片引脚；307-第一塑封层；3071-第一塑封层的正面；3072-第一塑封层的背面；308-第一再布线层；309-第二塑封层；310-盲孔；311-第二再布线层；312-第一线路图形层；313-第一导通孔；314-第一导电柱；315-第二线路图形层；316-塑封材料层；317-第二导通孔；318-第二导电柱；319-第三线路图形层；320-第一互联体；321-第二互联体。Explanation of reference symbols:
(Figure 1) 100-lead frame; 101-chip; 102-solder; 103-copper sheet; 104-plastic packaging material;
(Figure 2 to Figure 10) 200a-first carrier board; 200b-second carrier board; 200c-third carrier board; 201a-
First adhesive layer; 201b-second adhesive layer; 201c-third adhesive layer; 202-chip; 203-first plastic encapsulation layer; 204-first rewiring layer; 205-deep hole; 206-blind hole ; 207-The second rewiring layer; 208-The second plastic encapsulation layer;
(Figure 12 to Figure 32) 300a-first carrier board; 300b-second carrier board; 300c-third carrier board; 300d-
The fourth carrier board; 300e-the fifth carrier board; 301a-the first adhesive layer; 301b-the second adhesive layer; 301c-the third adhesive layer; 301d-the fourth adhesive layer; 301e-the fifth adhesive layer layer; 302-plastic board; 3021-front side of plastic board; 3022-backside of plastic board; 302a-via hole; 303-conductive layer; 304-conductive pillar; 305-interconnect; 306-chip; 306a-chip lead feet; 307-the first plastic packaging layer; 3071-the front side of the first plastic packaging layer; 3072-the back side of the first plastic packaging layer; 308-the first rewiring layer; 309-the second plastic packaging layer; 310-blind hole; 311-th Second rewiring layer; 312-first circuit pattern layer; 313-first via hole; 314-first conductive pillar; 315-second circuit pattern layer; 316-plastic sealing material layer; 317-second via hole; 318-the second conductive pillar; 319-the third circuit pattern layer; 320-the first interconnector; 321-the second interconnector.
具体实施方式Detailed ways
在介绍本发明的面板级扇出型双面互联的封装方法、包封结构和用于半导体封装的互联体的制备方法之前，首先介绍一种现有的先进封装工艺，该先进封装工艺通过镭射打孔和深孔电镀进行互联。图2至图10示出了该先进封装工艺的分步骤结构示意图，以下结合图2至图10对该先进封装工艺进行说明。Before introducing the packaging method, packaging structure and interconnect body for semiconductor packaging of the present invention, an existing advanced packaging process is first introduced. The advanced packaging process uses laser Drilling and deep hole plating for interconnection. FIGS. 2 to 10 show a step-by-step structural diagram of the advanced packaging process. The advanced packaging process will be described below in conjunction with FIGS. 2 to 10 .
如图2所述，在第一载板200a的顶面设置第一粘结层201a，再将切割好的芯片202通过贴片(Die Bond)方式重新排布在第一载板200a的顶面上，芯片202正面朝下，且芯片202和第一粘结层201a为可脱离固定。As shown in Figure 2, a first adhesive layer 201a is provided on the top surface of the first carrier board 200a, and then the cut chips 202 are rearranged on the top surface of the first carrier board 200a through die bonding. On the top, the chip 202 faces down, and the chip 202 and the first adhesive layer 201a are detachably fixed.
如图3所示，在第一载板200a的顶面上形成第一塑封层203，第一塑封层203覆盖第一粘结层201a和芯片202。As shown in Figure 3, a first plastic sealing layer 203 is formed on the top surface of the first carrier board 200a, and the first plastic sealing layer 203 covers the first adhesive layer 201a and the chip 202.
如图4所示，在第一塑封层203靠近芯片202背面的一侧上依次设置第二粘结层201b和第二载板200b，再翻转载板并去除第一载板200a和第一粘结层201a，露出芯片202正面上的芯片引脚202a。As shown in Figure 4, a second adhesive layer 201b and a second carrier plate 200b are sequentially placed on the side of the first plastic sealing layer 203 close to the back of the chip 202, and then the carrier plate is turned over and the first carrier plate 200a and the first adhesive layer are removed. The junction layer 201a exposes the chip pins 202a on the front side of the chip 202.
如图5所示，在芯片202的正面上形成第一再布线层204，第一再布线层204与芯片引脚202a相连接。As shown in FIG. 5 , a first rewiring layer 204 is formed on the front surface of the chip 202 , and the first rewiring layer 204 is connected to the chip pin 202 a.
如图6所示，在第一再布线层204远离芯片202的一侧依次形成第三粘结层201c和第三载板200c，去除第二载板200b和第二粘结层201b，使用镭射打孔工艺在第一塑封层203中形成深孔205，深孔205贯穿第一塑封层203 并露出部分第一再布线层204。As shown in FIG. 6 , a third adhesive layer 201 c and a third carrier plate 200 c are sequentially formed on the side of the first rewiring layer 204 away from the chip 202 , the second carrier plate 200 b and the second adhesive layer 201 b are removed, and a laser is used to The drilling process forms a deep hole 205 in the first plastic sealing layer 203, and the deep hole 205 penetrates the first plastic sealing layer 203. And a portion of the first rewiring layer 204 is exposed.
如图7所示，研磨第一塑封层203靠近芯片202背面的表面，露出芯片202的背面。或者，如图8所示，通过镭射工艺在第一塑封层203中靠近芯片202背面的一侧形成盲孔206，盲孔206露出芯片202的部分背面。以下以研磨第一塑封层203靠近芯片202背面的表面，露出芯片202的背面为例继续对该先进封装工艺进行说明。As shown in FIG. 7 , the surface of the first plastic encapsulation layer 203 close to the back of the chip 202 is polished to expose the back of the chip 202 . Alternatively, as shown in FIG. 8 , a blind hole 206 is formed in the first plastic encapsulation layer 203 on a side close to the back side of the chip 202 through a laser process, and the blind hole 206 exposes part of the back side of the chip 202 . The advanced packaging process will be described below by taking the example of grinding the surface of the first plastic encapsulation layer 203 close to the back of the chip 202 to expose the back of the chip 202 .
如图9所示，通过电镀工艺在芯片202的背面上形成第二再布线层207，第二再布线层207覆盖芯片202的背面且覆盖深孔205的表面，第二再布线层207与第一再布线层204电连接。形成第二再布线层207的方法包括：在第一塑封层203上形成种子层，种子层覆盖深孔205的内表面；在种子层上形成图形化的掩模层，再进行图形电镀工艺，形成电镀材料层；去除图形化的掩模层，刻蚀去除部分种子层，形成第二再布线层207。As shown in FIG. 9 , a second rewiring layer 207 is formed on the backside of the chip 202 through an electroplating process. The second rewiring layer 207 covers the backside of the chip 202 and covers the surface of the deep hole 205 . The second rewiring layer 207 is connected to the second rewiring layer 207 . The wiring layer 204 is electrically connected. The method of forming the second rewiring layer 207 includes: forming a seed layer on the first plastic layer 203, and the seed layer covers the inner surface of the deep hole 205; forming a patterned mask layer on the seed layer, and then performing a pattern plating process. An electroplating material layer is formed; the patterned mask layer is removed, and part of the seed layer is removed by etching to form the second rewiring layer 207 .
如图10所示，形成第二塑封层208，第二塑封层208覆盖第二再布线层207和第一塑封层203远离芯片202正面的表面，且填满深孔205。As shown in FIG. 10 , a second plastic sealing layer 208 is formed. The second plastic sealing layer 208 covers the second rewiring layer 207 and the surface of the first plastic sealing layer 203 away from the front surface of the chip 202 , and fills the deep hole 205 .
上述先进封装工艺在制作双面互联产品时，因为单面增层的原因，无法像传统框架封装结构一样在封装前一次性将芯片正反面连接，只能通过再布线层及构建互联通道的方式来满足双面互联需求。而利用面板级打深孔和电镀互联的方式，即利用深孔镭射电镀工艺实现互联，会存在以下限制：(1)由于镭射打孔，尤其是打深孔时，开孔的上下孔径无法做成相同尺寸，所以孔壁会存在一个较大倾角，上孔径一定时，塑封层的厚度越大，底孔越小，例如在塑封层厚度超过500微米时，深孔的可通流截面积会无法满足产品要求，且塑封层的厚度主要取决于芯片的厚度，因此，受限于镭射能力，封装的芯片厚度不能过厚，通常需要芯片的厚度在500微米以下，对于产品的多样性有较大限制；(2)镭射开孔效率低，整板镭射时间随孔的深度和尺寸的增大而增长；(3)镭射孔若出现开孔不良，则与该镭射孔位置相对应的芯片只能报废，造成良率损失；(4)深孔电镀时，容易产生孔内电镀不良的问题，影响产品良率；(5)产品整体制作周期长。When the above-mentioned advanced packaging technology is used to produce double-sided interconnected products, due to the single-sided layer addition, it is impossible to connect the front and back of the chip at one time before packaging like the traditional frame packaging structure. The only way is to rewire the layer and build an interconnection channel. To meet the needs of double-sided interconnection. However, the method of using panel-level deep hole drilling and electroplating interconnection, that is, using deep hole laser plating process to achieve interconnection, will have the following limitations: (1) Due to laser drilling, especially when drilling deep holes, the upper and lower apertures of the opening cannot be made. into the same size, so the hole wall will have a larger inclination angle. When the upper hole diameter is constant, the greater the thickness of the plastic sealing layer, the smaller the bottom hole. For example, when the thickness of the plastic sealing layer exceeds 500 microns, the flowable cross-sectional area of the deep hole will It cannot meet the product requirements, and the thickness of the plastic sealing layer mainly depends on the thickness of the chip. Therefore, limited by the laser capability, the thickness of the packaged chip cannot be too thick. Usually the thickness of the chip needs to be below 500 microns, which has a greater impact on product diversity. Large limitation; (2) The efficiency of laser hole opening is low, and the laser time of the entire board increases with the increase of the depth and size of the hole; (3) If the laser hole is poorly opened, the chip corresponding to the laser hole position will only It can be scrapped, resulting in yield loss; (4) When deep hole electroplating, it is easy to cause problems with poor plating in the hole, affecting product yield; (5) The overall production cycle of the product is long.
另外，若采用传统的封装工艺通过框架互联时，则需额外增加框架贴片 设备，且框架植入在先进封装中也存在信赖性、良率等一些问题，并且框架需跟随产品特制化，增加了产品成本。In addition, if the traditional packaging process is used to interconnect through the frame, additional frame patches are required. Equipment, and the frame implantation in advanced packaging also has some problems such as reliability and yield, and the frame needs to be customized according to the product, which increases the product cost.
为了解决上述问题，本实施例提供一种面板级扇出型双面互联的封装方法。以下结合附图和具体实施例对本发明提出的面板级扇出型双面互联的封装方法作进一步详细说明。根据下面的说明，本发明的优点和特征将更清楚。需说明的是，附图均采用非常简化的形式且均使用非精准的比例，仅用以方便、明晰地辅助说明本发明实施例的目的。In order to solve the above problem, this embodiment provides a panel-level fan-out type double-sided interconnection packaging method. The packaging method for panel-level fan-out double-sided interconnection proposed by the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are in a very simplified form and use imprecise proportions, and are only used to conveniently and clearly assist in explaining the embodiments of the present invention.
图11为本发明一实施例的面板级扇出型双面互联的封装方法。如图11所示，本实施例的面板级扇出型双面互联的封装方法包括：Figure 11 shows a packaging method for panel-level fan-out double-sided interconnection according to an embodiment of the present invention. As shown in Figure 11, the packaging method of panel-level fan-out double-sided interconnection in this embodiment includes:
S1，提供互联体和第三载板，所述互联体包括导电结构和隔离所述导电结构的塑封材料，所述互联体的两个相对端面均露出部分所述导电结构；S1, provide an interconnector and a third carrier board, the interconnector includes a conductive structure and a plastic packaging material isolating the conductive structure, and both opposite end surfaces of the interconnector expose part of the conductive structure;
S2，将芯片和所述互联体粘贴在所述第三载板的顶面上，所述互联体的一端面粘贴在所述第三载板上；S2. Paste the chip and the interconnector on the top surface of the third carrier board, and paste one end surface of the interconnector on the third carrier board;
S3，在所述第三载板顶面形成第一塑封层，所述第一塑封层至少包覆所述芯片的侧面以及所述互联体的侧面；S3, form a first plastic sealing layer on the top surface of the third carrier board, and the first plastic sealing layer covers at least the side of the chip and the side of the interconnect;
S4，形成与所述芯片正面和所述互联体电连接的第一再布线层，以及形成与所述芯片背面和所述互联体电连接的第二再布线层。S4: Form a first rewiring layer electrically connected to the front side of the chip and the interconnection body, and form a second rewiring layer electrically connected to the back side of the chip and the interconnection body.
应该理解的是，虽然图11的流程图中的各个步骤按照箭头的指示依次显示，但是这些步骤并不是必然按照箭头指示的顺序依次执行。除非本文中有明确的说明，这些步骤的执行并没有严格的顺序限制，这些步骤可以以其它的顺序执行。而且，图11中的至少一部分步骤可以包括多个步骤或者多个阶段，这些步骤或者阶段并不必然是在同一时刻执行完成，而是可以在不同的时刻执行，这些步骤或者阶段的执行顺序也不必然是依次进行，而是可以与其它步骤或者其它步骤中的步骤或者阶段的至少一部分轮流或者交替地执行。It should be understood that although various steps in the flowchart of FIG. 11 are shown in sequence as indicated by arrows, these steps are not necessarily executed in the order indicated by arrows. Unless explicitly stated in this article, there is no strict order restriction on the execution of these steps, and these steps can be executed in other orders. Moreover, at least some of the steps in Figure 11 may include multiple steps or stages. These steps or stages are not necessarily executed at the same time, but may be executed at different times. The execution order of these steps or stages is also It does not necessarily need to be performed sequentially, but may be performed in turn or alternately with other steps or at least part of steps or stages in other steps.
图12至图25为本发明一实施例的面板级扇出型双面互联的封装方法的分步骤结构示意图。其中，图12至图17以及图19至图25均为剖面结构示意图，图18为平面示意图。以下结合图12至图25对本实施例的面板级扇出 型双面互联的封装方法进行说明。12 to 25 are schematic step-by-step structural diagrams of a panel-level fan-out double-sided interconnection packaging method according to an embodiment of the present invention. Among them, Figures 12 to 17 and Figures 19 to 25 are schematic cross-sectional structural views, and Figure 18 is a schematic plan view. The panel-level fan-out of this embodiment will be described below in conjunction with Figures 12 to 25. The packaging method of type double-sided interconnection is explained.
参考图17和图18，步骤S1中，提供互联体305，互联体305在封装芯片之前预先制作，且提供的互联体305的数量可以为多个。所述互联体305包括导电结构和隔离所述导电结构的塑封材料。Referring to Figures 17 and 18, in step S1, an interconnect 305 is provided. The interconnect 305 is pre-made before packaging the chip, and the number of the provided interconnect 305 can be multiple. The interconnect 305 includes a conductive structure and a molding material isolating the conductive structure.
一实施例中，参考图17和图18，互联体305中的导电结构包括导电柱304。参考图12至图18，提供互联体305的方法可以包括分步骤S11～S16。In one embodiment, referring to FIGS. 17 and 18 , the conductive structure in the interconnect 305 includes conductive pillars 304 . Referring to FIGS. 12 to 18 , the method of providing the interconnection 305 may include steps S11 to S16.
分步骤S11：如图12所示，提供第一载板300a，并在所述第一载板300a的顶面形成塑封板302，塑封板302的背面朝向第一载板300a。具体的，第一载板300a与塑封板302之间设置有第一粘结层301a，即塑封板302通过第一粘结层301a粘贴在第一载板300a上。需要说明的是，本申请提及的“粘结层”均为“可解键的粘结层”，例如，通过第一粘结层301a固定的第一载板300a和塑封板302后续可以相互脱离。Substep S11: As shown in Figure 12, a first carrier board 300a is provided, and a plastic sealing plate 302 is formed on the top surface of the first carrier board 300a, with the back side of the plastic sealing board 302 facing the first carrier board 300a. Specifically, a first adhesive layer 301a is provided between the first carrier plate 300a and the plastic sealing plate 302, that is, the plastic sealing plate 302 is pasted on the first carrier plate 300a through the first adhesive layer 301a. It should be noted that the "adhesive layer" mentioned in this application is a "debondable adhesive layer". For example, the first carrier plate 300a and the plastic sealing plate 302 fixed by the first adhesive layer 301a can subsequently be connected to each other. Detach.
分步骤S12：如图13所述，形成导电层303，所述导电层303覆盖所述塑封板302的正面。导电层303的形成方法可以包括：在塑封板302的正面通过溅镀(sputter)工艺或化镀工艺形成薄膜层，薄膜层例如为钛层或铜层或钛铜层，再在薄膜层上电镀铜形成设定厚度的导电层303。通过溅镀工艺(或化镀工艺)与电镀工艺的结合，可以较快的形成一定厚度的导电层303，有助于确保导电层303的导电效果。本实施例中，薄膜层上电镀的是铜；但不限于此，在其它实施例中，薄膜层上电镀的可以是镍等其它金属。所述导电层303也可以仅通过溅镀工艺或化镀工艺形成。Step S12: As shown in FIG. 13, a conductive layer 303 is formed, and the conductive layer 303 covers the front surface of the plastic sealing plate 302. The formation method of the conductive layer 303 may include: forming a thin film layer on the front side of the plastic sealing plate 302 through a sputtering process or a chemical plating process. The thin film layer is, for example, a titanium layer or a copper layer or a titanium-copper layer, and then electroplating on the thin film layer. Copper forms a conductive layer 303 of a set thickness. Through the combination of the sputtering process (or chemical plating process) and the electroplating process, the conductive layer 303 with a certain thickness can be formed quickly, which helps to ensure the conductive effect of the conductive layer 303. In this embodiment, the thin film layer is electroplated with copper; but it is not limited to this. In other embodiments, the thin film layer is electroplated with nickel or other metals. The conductive layer 303 may also be formed only through a sputtering process or a chemical plating process.
分步骤S13：如图14所示，在所述导电层303远离所述塑封板302的一侧设置第二载板300b，并去除所述第一载板300a和第一粘结层301a，露出所述塑封板302的背面。所述第二载板300b与所述导电层303之间可以设置有第二粘结层301b。Sub-step S13: As shown in Figure 14, set a second carrier plate 300b on the side of the conductive layer 303 away from the plastic sealing plate 302, and remove the first carrier plate 300a and the first adhesive layer 301a to expose The back side of the plastic sealing board 302 . A second adhesive layer 301b may be disposed between the second carrier plate 300b and the conductive layer 303.
分步骤S14：继续参考图14，在所述塑封板302中形成多个导通孔302a，所述多个导通孔302a贯穿所述塑封板302且露出部分所述导电层303。具体的，可以通过镭射工艺从塑封板302远离第二载板300b的一侧朝向所述第二载板300b开孔形成多个所述导通孔302a，导电层303可以作为镭射开孔的基 材(即阻挡层)。Substep S14: Continuing to refer to FIG. 14 , a plurality of conductive holes 302 a are formed in the plastic sealing plate 302 , and the plurality of conductive holes 302 a penetrate the plastic sealing plate 302 and expose part of the conductive layer 303 . Specifically, a plurality of the conductive holes 302a can be formed by opening holes from the side of the plastic sealing plate 302 away from the second carrier plate 300b toward the second carrier plate 300b through a laser process, and the conductive layer 303 can be used as a base for laser openings. Material (i.e. barrier layer).
分步骤S15：如图15所示，以所述导电层303作为导电种子层，从所述多个导通孔302a的孔底朝向孔口电镀形成所述多个导电柱304，所述导电柱304填满对应的所述导通孔302a。Sub-step S15: As shown in Figure 15, using the conductive layer 303 as a conductive seed layer, electroplating from the bottom of the plurality of via holes 302a toward the hole openings forms the plurality of conductive pillars 304. The conductive pillars 304 fills the corresponding via hole 302a.
为了确保导电柱304填满对应的导通孔302a，以导电层303作为导电种子层，从多个导通孔302a的孔底朝向孔口电镀形成多个导电柱304的方法可以包括：以导电层303作为导电种子层，从多个导通孔302a的孔底朝向孔口电镀形成电镀材料层，且所述电镀材料层凸出导通孔302a的孔口；使用包括但不限于研磨的方式去除电镀材料层凸出于导通孔302a孔口的部分，形成多个导电柱304。In order to ensure that the conductive pillars 304 fill the corresponding via holes 302a, using the conductive layer 303 as the conductive seed layer, the method of electroplating to form the multiple conductive pillars 304 from the bottoms of the multiple via holes 302a toward the openings may include: Layer 303 serves as a conductive seed layer, and is electroplated from the bottoms of the plurality of via holes 302a toward the openings to form an electroplating material layer, and the electroplating material layer protrudes from the openings of the via holes 302a; using methods including but not limited to grinding The portion of the plating material layer protruding from the opening of the via hole 302a is removed to form a plurality of conductive pillars 304.
一些实施例中，形成多个导电柱304的方法可以包括：以导电层303作为导电种子层，从多个导通孔302a的孔底朝向孔口电镀形成电镀材料层，且所述电镀材料层未填满导通孔302a；研磨去除塑封板302的部分厚度，以减小导通孔302a的深度，使得所有导通孔302a中的电镀材料层与塑封板的背面齐平，在研磨的过程中，可以去除电镀材料层的部分厚度。In some embodiments, the method of forming the plurality of conductive pillars 304 may include: using the conductive layer 303 as a conductive seed layer, electroplating from the bottom of the plurality of via holes 302a toward the hole opening to form an electroplating material layer, and the electroplating material layer The via holes 302a are not filled; grinding removes part of the thickness of the plastic board 302 to reduce the depth of the via holes 302a so that the plating material layers in all via holes 302a are flush with the back of the plastic board. During the grinding process , part of the thickness of the layer of electroplated material can be removed.
分步骤S16：如图16和图17所示，去除所述第二载板300b、第二粘结层301b和导电层303，切割塑封板302，形成多个互联体305(也可称为“互联dummy die”)。其中，在去除第二载板300b和第二粘结层301b后，可以利用化学机械研磨工艺研磨去除导电层303。但不限于此，根据导电层303的材料可以选择其它适合的工艺去除导电层303。Step S16: As shown in Figures 16 and 17, remove the second carrier board 300b, the second adhesive layer 301b and the conductive layer 303, cut the plastic board 302, and form a plurality of interconnectors 305 (also known as " Internet dummy die"). After removing the second carrier plate 300b and the second adhesive layer 301b, the conductive layer 303 can be polished and removed using a chemical mechanical polishing process. But it is not limited to this, other suitable processes can be selected to remove the conductive layer 303 according to the material of the conductive layer 303 .
如图18所示，互联体305中的导电柱304的横截面形状可以为圆形。但不限于此，导电柱304的横截面形状还可以为方形或椭圆形等。互联体305的尺寸(例如长度、宽度和高度)以及其内部的导电柱304的尺寸可以根据产品需求设计，且互联体305中导电柱304的数量也可以根据需要设置，在设计过程中尽量使得互联体305可以满足大多数的双面导通的产品需求，如此有利于增大互联体305的适用范围。As shown in FIG. 18 , the cross-sectional shape of the conductive pillars 304 in the interconnect 305 may be circular. But it is not limited thereto. The cross-sectional shape of the conductive pillar 304 may also be square or elliptical. The size of the interconnect 305 (such as length, width and height) and the size of the conductive pillars 304 inside it can be designed according to product requirements, and the number of conductive pillars 304 in the interconnect 305 can also be set as needed. Try to make it as easy as possible during the design process. The interconnector 305 can meet the needs of most double-sided conduction products, which will help increase the applicable scope of the interconnector 305.
为了满足多芯片、多引脚以及互联结构复杂的产品需求，还可以在互联体内特制线路来完成双面互联的制作，增加先进板级封装的产品多样性。一 实施例中，互联体中的导电结构包括互联的多层线路图形层；参考图26至图31，提供互联体的方法可以包括：In order to meet the needs of products with multi-chips, multi-pins and complex interconnect structures, special lines can also be made in the interconnect to complete the production of double-sided interconnects, increasing the product diversity of advanced board-level packaging. one In embodiments, the conductive structure in the interconnect includes interconnected multi-layer circuit pattern layers; with reference to Figures 26 to 31, a method of providing an interconnect may include:
如图26所示，提供塑封板302，所述塑封板302具有相对的正面和背面；在所述塑封板的正面3021形成第一线路图形层312，作为示例，第一线路图形层312包括多个导电垫(Pad)，该导电垫后续可以与芯片的一端互联；As shown in Figure 26, a plastic sealing board 302 is provided, and the plastic sealing board 302 has an opposite front and a back; a first circuit pattern layer 312 is formed on the front surface 3021 of the plastic sealing board. As an example, the first circuit pattern layer 312 includes a plurality of A conductive pad (Pad), which can be interconnected with one end of the chip later;
如图27所示，在所述塑封板302中形成多个第一导通孔313，所述多个第一导通孔313贯穿所述塑封板302且均露出部分所述第一线路图形层312；As shown in FIG. 27 , a plurality of first via holes 313 are formed in the plastic board 302 , and the plurality of first via holes 313 penetrate the plastic board 302 and expose part of the first circuit pattern layer. 312;
如图28所示，以第一线路图形层312作为导电种子层，从多个第一导通孔313的孔底朝向孔口电镀形成所述多个第一导电柱314，第一导电柱314填满对应的第一导通孔313且第一导电柱314的顶面与塑封板的背面3022齐平；As shown in FIG. 28 , using the first circuit pattern layer 312 as a conductive seed layer, the plurality of first conductive pillars 314 are formed by electroplating from the bottom of the plurality of first via holes 313 toward the hole openings. The first conductive pillars 314 The corresponding first via hole 313 is filled and the top surface of the first conductive pillar 314 is flush with the back surface 3022 of the plastic board;
如图29所示，在所述塑封板的背面3022形成第二线路图形层315，所述第二线路图形层315与所述多个第一导电柱314相连接；As shown in Figure 29, a second circuit pattern layer 315 is formed on the back surface 3022 of the plastic sealing board, and the second circuit pattern layer 315 is connected to the plurality of first conductive pillars 314;
如图30所示，可以通过层压或压合的方式形成覆盖第二线路图形层315的塑封材料层316，在所述塑封材料层316中形成多个第二导通孔317，所述多个第二导通孔317均露出部分所述第二线路图形层315；As shown in FIG. 30 , a plastic sealing material layer 316 covering the second circuit pattern layer 315 can be formed by lamination or pressing, and a plurality of second via holes 317 are formed in the plastic sealing material layer 316 . Each second via hole 317 exposes part of the second circuit pattern layer 315;
如图31所示，以第二线路图形层315作为导电种子层，从多个第二导通孔317的孔底朝向孔口电镀形成多个第二导电柱318，所述第二导电柱318填满对应的所述第二导通孔317，在所述塑封材料层316背向所述第二线路图形层315的表面形成第三线路图形层319，所述第三线路图形层319与所述多个第二导电柱318相连接；As shown in FIG. 31 , using the second circuit pattern layer 315 as a conductive seed layer, a plurality of second conductive pillars 318 are formed by electroplating from the bottoms of the plurality of second via holes 317 toward the hole openings. The second conductive pillars 318 The corresponding second via holes 317 are filled, and a third circuit pattern layer 319 is formed on the surface of the plastic sealing material layer 316 facing away from the second circuit pattern layer 315. The third circuit pattern layer 319 is connected to the The plurality of second conductive pillars 318 are connected;
接着，执行切割工艺，形成多个所述互联体。具体的，分割塑封板302、塑封材料层316、第一线路图形层312、多个第一导电柱314、第二线路图形层315、多个第二导电柱318和第三线路图形层319，形成多个互联体。Then, a cutting process is performed to form a plurality of interconnected bodies. Specifically, divide the plastic sealing board 302, the plastic sealing material layer 316, the first circuit pattern layer 312, the plurality of first conductive pillars 314, the second circuit pattern layer 315, the plurality of second conductive pillars 318 and the third circuit pattern layer 319, Multiple interconnections are formed.
需要说明的是，在形成第三线路图形层319之后，通过重复执行形成塑封材料层、形成导通孔、在导通孔中形成导电柱、以及在塑封材料层上形成线路图形层的步骤，可以形成包括互联的多层线路图形层的互联体。互联体中线路图形层的图形不限于图31中所示的图形。It should be noted that after the third circuit pattern layer 319 is formed, by repeatedly performing the steps of forming a molding material layer, forming a via hole, forming a conductive pillar in the via hole, and forming a circuit pattern layer on the molding material layer, An interconnect may be formed that includes interconnected multi-layer line pattern layers. The pattern of the line pattern layer in the interconnect is not limited to the pattern shown in Fig. 31.
上述形成互联体中的导电柱均是通过反面导通电镀的方法形成，所谓反 面导通电镀是指以导通孔底部的导电层作为导电种子层，从导通孔的孔底朝向孔口电镀形成填满导通孔的导电柱的电镀方法。传统的化镀、电镀只能将深孔的孔壁镀铜，无法将整个孔填满，本申请采用反面导通电镀的方式形成互联体中的导电柱，使得导电柱可以完全将导通孔填满填平，尤其是能够将深孔填满填平，保证了孔内导电材料(如铜)的截面积大小满足需求，从而使得每颗互联体均具备良好的通流能力，还可以避免深孔镭射电镀的众多限制，且可以避免深孔电镀孔底干膜残留、孔内铜不连续、电镀无法填满深孔和框架类植入等一系列影响产品性能及良率的问题，有利于建立稳定的互联通道，提高产品良率。The conductive pillars in the above-mentioned interconnects are all formed by reverse conduction plating. The so-called reverse Surface conduction plating refers to a plating method that uses the conductive layer at the bottom of the via hole as a conductive seed layer and plating from the bottom of the via hole toward the hole opening to form a conductive pillar that fills the via hole. Traditional chemical plating and electroplating can only plate copper on the walls of deep holes and cannot fill the entire hole. This application uses reverse conduction plating to form conductive pillars in the interconnect, so that the conductive pillars can completely cover the conductive holes. Filling and leveling, especially the ability to fill and level deep holes, ensures that the cross-sectional area of the conductive material (such as copper) in the hole meets the requirements, so that each interconnect has good flow capacity and can also avoid There are many limitations of deep-hole laser plating, and it can avoid a series of problems that affect product performance and yield, such as dry film residue at the bottom of deep-hole plating holes, discontinuous copper in the holes, inability of plating to fill deep holes, and frame-like implantation, etc. It is conducive to establishing a stable interconnection channel and improving product yield.
以下以图17中的互联体305为例继续对本申请的面板级扇出型双面互联的封装方法进行说明。但不限于此，互联体还可以是其它结构。The packaging method of the panel-level fan-out double-sided interconnection of the present application will be described below by taking the interconnection body 305 in FIG. 17 as an example. But it is not limited to this, the interconnector can also be other structures.
在形成互联体305，以及提供第三载板300c之后，执行步骤S2，如图19所示，将芯片306和所述互联体305粘贴在所述第三载板300c的顶面上，所述互联体305的一端面粘贴在所述第三载板300c上，其中，所述导电柱304的一端面也粘贴在所述第三载板300c上。After the interconnect 305 is formed and the third carrier 300c is provided, step S2 is performed. As shown in FIG. 19 , the chip 306 and the interconnect 305 are pasted on the top surface of the third carrier 300 c. One end surface of the interconnect 305 is pasted on the third carrier board 300c, wherein one end surface of the conductive pillar 304 is also pasted on the third carrier board 300c.
具体的，第三载板300c上形成有第三粘结层301c，芯片306和互联体305通过第三粘结层301c与第三载板300c固定。所述第三粘结层301c为可解键的粘结层。所述芯片306的正面形成有芯片引脚306a。一些实施例中，芯片306的背面为接触垫。本实施例中，粘贴在第三载板300c上的芯片306和互联体305的数量均为多个。Specifically, a third adhesive layer 301c is formed on the third carrier board 300c, and the chip 306 and the interconnect 305 are fixed to the third carrier board 300c through the third adhesive layer 301c. The third adhesive layer 301c is a debondable adhesive layer. Chip pins 306a are formed on the front side of the chip 306. In some embodiments, the backside of chip 306 is a contact pad. In this embodiment, the number of chips 306 and interconnects 305 pasted on the third carrier board 300c is multiple.
优选的，如图19所示，步骤S2中，使所述芯片306的正面朝向所述第三载板300c，即将芯片306正面朝下的粘贴在第三载板300c的顶面上。但不限于此，在其它实施例中，也可以将芯片306背面朝下的粘贴在第三载板300c的顶面上。Preferably, as shown in FIG. 19 , in step S2, the front side of the chip 306 is directed toward the third carrier plate 300c, that is, the chip 306 is pasted face down on the top surface of the third carrier plate 300c. But it is not limited to this. In other embodiments, the chip 306 can also be pasted on the top surface of the third carrier 300c with the back side facing downward.
执行步骤S3，在所述第三载板300c顶面形成第一塑封层，所述第一塑封层至少包覆所述芯片306的侧面以及所述互联体305的侧面。Step S3 is performed to form a first plastic sealing layer on the top surface of the third carrier board 300c. The first plastic sealing layer covers at least the side of the chip 306 and the side of the interconnect 305.
作为示例，如图20所示，步骤S3中，形成的第一塑封层307覆盖所述第三载板300c的顶面、所述芯片306的背面和所述互联体305的另一端面。 第一塑封层307可以通过层压的方式形成。As an example, as shown in FIG. 20 , in step S3 , the first plastic encapsulation layer 307 is formed to cover the top surface of the third carrier 300 c , the back surface of the chip 306 and the other end surface of the interconnect 305 . The first plastic sealing layer 307 can be formed by lamination.
热膨胀系数(CTE)不同的材料相互包封后，在可靠性测试中表现出不同的收缩率，所造成的内部应力差异过大时会导致芯片失效，例如，在加温后不同热膨胀系数的材料的膨胀收缩尺寸不同，造成在不同材料分界区形成开裂和/或分层等缺陷。为了提高产品的可靠性，所述第一塑封层307的材料的热膨胀系数和所述互联体305中塑封材料的热膨胀系数可以相近。由于物理性质和化学性质相同的材料相互包封后，经过各类可靠性测试时所表现出来的实际性能相同或相近，因此互联体305中的塑封材料与第一塑封层307的物理性质和化学性质可以相同。优选的，第一塑封层307的材质和互联体305中塑封材料的材质相同，例如可以均为环氧树脂模塑料(MC－Epoxy Molding Compound，EMC)。After materials with different coefficients of thermal expansion (CTE) are encapsulated with each other, they show different shrinkage rates in reliability tests. When the internal stress difference is too large, it will cause chip failure. For example, materials with different coefficients of thermal expansion after heating The expansion and contraction dimensions are different, causing defects such as cracking and/or delamination in the boundary areas of different materials. In order to improve the reliability of the product, the thermal expansion coefficient of the material of the first plastic sealing layer 307 and the thermal expansion coefficient of the plastic sealing material in the interconnection body 305 can be similar. Since the actual performance shown by materials with the same physical and chemical properties after being encapsulated with each other is the same or similar after various reliability tests, the physical and chemical properties of the plastic packaging material in the interconnect 305 and the first plastic packaging layer 307 The properties can be the same. Preferably, the material of the first plastic sealing layer 307 is the same as the material of the plastic sealing material in the interconnect 305 , for example, they can both be epoxy resin molding compound (MC-Epoxy Molding Compound, EMC).
需要说明的是，将芯片306正面朝下的粘贴在第三载板300c上，后续在去除第三载板300c和第三粘结层301c后即可露出芯片306正面上的芯片引脚306a，其中不需要研磨第一塑封层307，从而芯片306的正面能够得到有效地保护，有利于提高封装成品率。It should be noted that the chip 306 is pasted face down on the third carrier board 300c, and the chip pins 306a on the front surface of the chip 306 can be exposed after removing the third carrier board 300c and the third adhesive layer 301c. There is no need to grind the first plastic encapsulation layer 307, so that the front side of the chip 306 can be effectively protected, which is beneficial to improving the packaging yield.
步骤S3之后，形成与所述芯片306正面和所述互联体305电连接的第一再布线层。After step S3, a first rewiring layer electrically connected to the front surface of the chip 306 and the interconnect 305 is formed.
具体的，参考图20和图21，去除所述第三载板300c和第三粘结层301c，露出所述芯片306正面上的芯片引脚306a以及所述互联体305的一端面。其中，为了防止第一塑封层307翘曲而影响产品良率，在去除第三载板300c和第三粘结层301c之前，可以在第一塑封层的正面3071依次设置第四粘结层301d和第四载板300d。Specifically, referring to FIGS. 20 and 21 , the third carrier board 300c and the third adhesive layer 301c are removed to expose the chip pins 306a on the front side of the chip 306 and one end surface of the interconnect 305 . Among them, in order to prevent the first plastic sealing layer 307 from warping and affecting the product yield, before removing the third carrier board 300c and the third adhesive layer 301c, a fourth adhesive layer 301d can be sequentially provided on the front surface 3071 of the first plastic sealing layer. and fourth carrier plate 300d.
如图21所示，在所述芯片306的正面形成第一再布线层308，所述第一再布线层308与所述芯片引脚306a和互联体305的导电结构(例如导电柱304)相连接。As shown in Figure 21, a first rewiring layer 308 is formed on the front side of the chip 306. The first rewiring layer 308 is in contact with the chip pins 306a and the conductive structures (such as conductive pillars 304) of the interconnect 305. connect.
在形成第一再布线层308之前，还可以进行翻板，使得芯片306的正面朝上。形成第一再布线层308的方法可以包括：形成种子层，该种子层覆盖第一塑封层的背面3072、芯片引脚306a和互联体305的端面；在该种子层上 形成图形化的掩模层，以该图形化的掩模层为掩模，电镀形成电镀层；去除图形化的掩模层，刻蚀去除露出的种子层，形成第一再布线层308。第一再布线层308的材料可以包括铜。Before forming the first rewiring layer 308, the chip 306 may be turned over so that the front side of the chip 306 faces upward. The method of forming the first rewiring layer 308 may include: forming a seed layer covering the backside 3072 of the first molding layer, the chip pins 306a and the end surfaces of the interconnect 305; on the seed layer A patterned mask layer is formed, and the patterned mask layer is used as a mask to perform electroplating to form an electroplating layer; the patterned mask layer is removed, and the exposed seed layer is etched to form the first rewiring layer 308 . The material of the first rewiring layer 308 may include copper.
如图22所示，在形成第一再布线层308之后，可以在所述芯片306的正面一侧形成第二塑封层309，所述第二塑封层309覆盖所述第一再布线层308以及第一塑封层的背面3072(即第一塑封层307靠近所述第一再布线层308的表面)。优选的，第二塑封层309的材料与第一塑封层307的材料相同。第二塑封层309可以通过层压的方式形成。As shown in FIG. 22 , after the first rewiring layer 308 is formed, a second plastic encapsulation layer 309 may be formed on the front side of the chip 306 , and the second plastic encapsulation layer 309 covers the first rewiring layer 308 and The back side 3072 of the first molding layer (that is, the surface of the first molding layer 307 close to the first rewiring layer 308). Preferably, the material of the second plastic sealing layer 309 is the same as the material of the first plastic sealing layer 307 . The second plastic sealing layer 309 can be formed by lamination.
具体的，参考图22和图23，在形成第二塑封层309之后，在第二塑封层309背向第一塑封层307的表面依次设置第五粘结层301e和第五载板300e；去除第四载板300d和第四粘结层301d，露出第一塑封层的正面3071。Specifically, referring to Figures 22 and 23, after the second plastic sealing layer 309 is formed, the fifth adhesive layer 301e and the fifth carrier plate 300e are sequentially provided on the surface of the second plastic sealing layer 309 facing away from the first plastic sealing layer 307; remove The fourth carrier plate 300d and the fourth adhesive layer 301d expose the front side 3071 of the first plastic sealing layer.
接着，形成与所述芯片306背面和所述互联体305电连接的第二再布线层。需要说明的是，本申请以先形成第一再布线层308后形成第二再布线层为例进行说明，但不限于此，第一再布线层308也可以在形成第二再布线层之后形成。Next, a second rewiring layer electrically connected to the backside of the chip 306 and the interconnect 305 is formed. It should be noted that this application takes the example of forming the first rewiring layer 308 first and then forming the second rewiring layer. However, it is not limited to this. The first rewiring layer 308 can also be formed after the second rewiring layer is formed. .
优选的，互联体305的原始厚度大于芯片306的原始厚度。形成与所述芯片306背面和所述互联体305电连接的第二再布线层，包括：如图23所示，研磨第一塑封层的正面3071，即研磨第一塑封层307远离芯片306正面的表面，去除第一塑封层307的部分厚度，露出互联体305的另一端面；如图24所示，在第一塑封层中形成盲孔310，所述盲孔310露出所述芯片306的部分背面；如图25所示，形成与所述芯片306背面和所述互联体305电连接的第二再布线层311，第二再布线层311填充盲孔310且覆盖盲孔310的内表面。该实施例中，研磨第一塑封层的正面3071去除第一塑封层307的部分厚度的过程中，还可以研磨去除所述互联体305的部分厚度，使得芯片306背面上剩余的第一塑封层的厚度在设定范围内，有助于减小盲孔310的深度以及减小产品厚度，同时，第一塑封层307的研磨面离芯片306背面有一定的距离，可有效地保护芯片306的背面。Preferably, the original thickness of the interconnect 305 is greater than the original thickness of the chip 306 . Forming a second rewiring layer electrically connected to the back side of the chip 306 and the interconnect 305 includes: as shown in Figure 23, grinding the front side 3071 of the first plastic encapsulation layer, that is, grinding the first plastic encapsulation layer 307 away from the front side of the chip 306 surface, remove part of the thickness of the first plastic sealing layer 307 to expose the other end surface of the interconnect 305; as shown in Figure 24, a blind hole 310 is formed in the first plastic sealing layer, and the blind hole 310 exposes the chip 306 Part of the backside; as shown in Figure 25, a second rewiring layer 311 electrically connected to the backside of the chip 306 and the interconnect 305 is formed. The second rewiring layer 311 fills the blind hole 310 and covers the inner surface of the blind hole 310. . In this embodiment, during the process of grinding the front side 3071 of the first plastic layer to remove part of the thickness of the first plastic layer 307, part of the thickness of the interconnect 305 can also be ground and removed, so that the remaining first plastic layer on the back of the chip 306 The thickness is within the set range, which helps to reduce the depth of the blind hole 310 and reduce the thickness of the product. At the same time, the grinding surface of the first plastic sealing layer 307 is at a certain distance from the back of the chip 306, which can effectively protect the chip 306. back.
一实施例中，互联体305的原始厚度大于芯片306的原始厚度。形成与 所述芯片306背面和所述互联体305电连接的第二再布线层311，包括：研磨第一塑封层的正面3071去除所述第一塑封层307的部分厚度，露出所述互联体305的另一端面；继续研磨所述第一塑封层307和所述互联体305的另一端面，直至露出所述芯片306的背面；形成与所述芯片306背面和所述互联体305电连接的第二再布线层311。In one embodiment, the original thickness of the interconnect 305 is greater than the original thickness of the chip 306 . formed with The second rewiring layer 311 electrically connected to the back of the chip 306 and the interconnect 305 includes: grinding the front 3071 of the first plastic layer to remove part of the thickness of the first plastic layer 307 to expose the interconnect 305 The other end face; continue to grind the first plastic encapsulation layer 307 and the other end face of the interconnector 305 until the backside of the chip 306 is exposed; form a third electrically connected backside of the chip 306 and the interconnection body 305 Second rewiring layer 311.
一实施例中，所述互联体305的原始厚度等于所述芯片306的原始厚度。形成与所述芯片306背面和所述互联体305电连接的第二再布线层311，包括：研磨所述第一塑封层的正面3071去除所述第一塑封层307的部分厚度，同时露出所述芯片306的背面以及所述互联体305的另一端面；形成与所述芯片306背面和所述互联体305电连接的第二再布线层311。In one embodiment, the original thickness of the interconnect 305 is equal to the original thickness of the chip 306 . Forming the second rewiring layer 311 electrically connected to the backside of the chip 306 and the interconnect 305 includes: grinding the front side 3071 of the first plastic encapsulation layer to remove part of the thickness of the first plastic encapsulation layer 307 while exposing all The back surface of the chip 306 and the other end surface of the interconnect 305 form a second rewiring layer 311 electrically connected to the back surface of the chip 306 and the interconnect 305 .
一实施例中，所述互联体305的原始厚度小于所述芯片306的原始厚度。形成与所述芯片306背面和所述互联体305电连接的第二再布线层311，包括：研磨所述第一塑封层的正面3071去除所述第一塑封层307的部分厚度，露出所述芯片306的背面；以及继续研磨所述第一塑封层的正面3071和所述芯片306的背面，露出所述互联体305的另一端面；形成与所述芯片306背面和所述互联体305电连接的第二再布线层311。需要说明的是，该实施例中，芯片306的背面需允许研磨，否则研磨芯片的背面可能导致芯片报废。In one embodiment, the original thickness of the interconnect 305 is smaller than the original thickness of the chip 306 . Forming the second rewiring layer 311 electrically connected to the backside of the chip 306 and the interconnect 305 includes: grinding the front side 3071 of the first plastic encapsulation layer to remove part of the thickness of the first plastic encapsulation layer 307 to expose the The back side of the chip 306; and continue to grind the front side 3071 of the first plastic sealing layer and the back side of the chip 306 to expose the other end surface of the interconnect 305; forming an electrical connection with the back side of the chip 306 and the interconnect 305. Connected second rewiring layer 311. It should be noted that in this embodiment, the backside of the chip 306 needs to be allowed to be ground, otherwise grinding the backside of the chip may cause the chip to be scrapped.
形成第一再布线层308和第二再布线层311之后，本实施例的面板级扇出型双面互联的封装方法还可以包括：形成第三塑封层(图中未示出)，第三塑封层覆盖第二再布线层311。After forming the first rewiring layer 308 and the second rewiring layer 311, the panel-level fan-out double-sided interconnection packaging method of this embodiment may also include: forming a third plastic encapsulation layer (not shown in the figure), a third The plastic encapsulation layer covers the second rewiring layer 311.
图32为利用本发明一实施例的面板级扇出型双面互联的封装方法封装形成的半导体结构示意图。一实施例中，芯片306和互联体的数量均为多个，多个互联体包括多个第一互联体320和多个第二互联体321；参考图32，在芯片306的背面一侧形成第二再布线层311之后，部分数量的芯片306与对应的第一互联体320或第二互联体321电连接，部分数量的芯片306与对应的第一互联体320和第二互联体321电连接。但不限于此，另一实施例中，每颗芯片均具有对应的第一互联体320和第二互联体321；在芯片306的背面一侧形成第二再布线层311之后，每颗芯片306与对应的第一互联体320和 第二互联体321电连接。FIG. 32 is a schematic diagram of a semiconductor structure packaged using a panel-level fan-out double-sided interconnection packaging method according to an embodiment of the present invention. In one embodiment, there are multiple chips 306 and multiple interconnects. The multiple interconnects include a plurality of first interconnects 320 and a plurality of second interconnects 321. Referring to Figure 32, a plurality of interconnects are formed on the back side of the chip 306. After the second rewiring layer 311, a portion of the chips 306 are electrically connected to the corresponding first interconnects 320 or the second interconnects 321, and a portion of the chips 306 are electrically connected to the corresponding first interconnects 320 and the second interconnects 321. connect. But it is not limited to this. In another embodiment, each chip has a corresponding first interconnect 320 and a second interconnect 321; after forming the second rewiring layer 311 on the back side of the chip 306, each chip 306 with the corresponding first interconnect 320 and The second interconnect 321 is electrically connected.
本申请中，所述芯片306对应的互联体数量也不仅限于一个或是两个，还可以是三个以上。所述芯片306对应的互联体种类也不仅限于一种或是两种，还可以是三种以上。In this application, the number of interconnects corresponding to the chip 306 is not limited to one or two, but can also be three or more. The types of interconnects corresponding to the chip 306 are not limited to one or two types, but may also be three or more types.
与现有技术相比，本申请的面板级扇出型双面互联的封装方法具有以下优势：(1)现有技术中深孔镭射电镀技术受限条件及因素过多，对于产品良率影响过大，且通流能力低，容易导致芯片报废；本申请利用预先制备的互联体实现芯片306的双面互联，可以避免采用传统深孔镭射电镀的方式实现双面互联，进而可以避免深孔电镀孔底干膜残留和孔内铜不连续等影响产品性能及良率的问题，有利于建立稳定的互联通道，提高产品良率；(2)现有技术中为了实现双面互联，需对每张粘贴有芯片的载板上的塑封层进行深孔镭射电镀，生产效率低，而本发明中互联体在芯片306封装前提前制作，并且芯片306和提前准备的互联体采用贴片(Die Bond)的方式粘贴在第三载板300c的顶面上，从而一次制作的多个互联体可用于数批芯片封装，且避免了对每张粘贴有芯片306的载板上的塑封层，即第一塑封层307，进行深孔镭射电镀，保证了封装中互联通道的稳定性并极大地加快了芯片封装的加工速度，有利于缩短封装周期，提高生产效率；(3)互联体的通用性强，针对类似产品可以通用同一种互联体，无需为每种产品设计特定的互联体，只需更改第一再布线层308和/或第二再布线层311的引线即可，极大地节省了设计成本；(4)因提前制作的互联体可以为任意厚度，还可以在封装过程中去除部分厚度的互联体，从而可以适应不同芯片306的需求，使得封装过程中芯片厚度不受限制。Compared with the existing technology, the panel-level fan-out double-sided interconnection packaging method of the present application has the following advantages: (1) In the existing technology, the deep-hole laser plating technology is limited by too many conditions and factors, which affects the product yield. If it is too large and has low flow capacity, it will easily lead to chip scrapping; this application uses pre-prepared interconnects to realize double-sided interconnection of chip 306, which can avoid the use of traditional deep-hole laser plating to achieve double-sided interconnection, thereby avoiding deep holes. Problems such as dry film residue at the bottom of plating holes and copper discontinuity in the holes that affect product performance and yield are conducive to establishing stable interconnection channels and improving product yields; (2) In order to achieve double-sided interconnection in the existing technology, it is necessary to The plastic sealing layer on each carrier board with a chip pasted is subjected to deep-hole laser plating, which results in low production efficiency. However, in the present invention, the interconnector is made in advance before the chip 306 is packaged, and the chip 306 and the interconnector prepared in advance are made of die. Bond) method is pasted on the top surface of the third carrier board 300c, so that multiple interconnectors produced at one time can be used for several batches of chip packaging, and the plastic sealing layer on each carrier board with the chip 306 pasted is avoided, that is, The first plastic encapsulation layer 307 is subjected to deep-hole laser plating, which ensures the stability of the interconnection channels in the package and greatly speeds up the processing speed of chip packaging, which is beneficial to shortening the packaging cycle and improving production efficiency; (3) Versatility of the interconnector Strong, the same interconnect can be used for similar products. There is no need to design a specific interconnect for each product. You only need to change the leads of the first rewiring layer 308 and/or the second rewiring layer 311, which greatly saves money. Design cost; (4) Because the interconnects produced in advance can be of any thickness, part of the thickness of the interconnects can also be removed during the packaging process, thereby adapting to the needs of different chips 306, so that the chip thickness is not limited during the packaging process.
本申请还提供一种包封结构。该包封结构可以利用上述的面板级扇出型双面互联的封装方法形成。This application also provides an encapsulation structure. The encapsulation structure can be formed using the above-mentioned panel-level fan-out double-sided interconnection encapsulation method.
参考图25，包封结构包括芯片306、互联体305、第一塑封层307、第一再布线层308和第二再布线层311。具体的，互联体305和第一塑封层307在不同的步骤中形成。互联体305包括导电结构304和隔离导电结构304的塑封材料，互联体305的两个相对端面均露出部分导电结构304。第一塑封层 307至少包覆芯片306的侧面以及互联体305的侧面。第一再布线层308位于第一塑封层的背面3072一侧，与芯片306正面和互联体305电连接。第二再布线层311位于第一塑封层的正面3071一侧，与芯片306背面和互联体305电连接。Referring to FIG. 25 , the encapsulation structure includes a chip 306 , an interconnect 305 , a first plastic encapsulation layer 307 , a first rewiring layer 308 and a second rewiring layer 311 . Specifically, the interconnector 305 and the first plastic encapsulation layer 307 are formed in different steps. The interconnect 305 includes a conductive structure 304 and a plastic encapsulation material isolating the conductive structure 304. Part of the conductive structure 304 is exposed on two opposite end surfaces of the interconnect 305. first plastic sealing layer 307 covers at least the sides of the chip 306 and the sides of the interconnect 305 . The first rewiring layer 308 is located on the back side 3072 of the first plastic encapsulation layer and is electrically connected to the front side of the chip 306 and the interconnect 305 . The second rewiring layer 311 is located on the front side 3071 of the first plastic encapsulation layer and is electrically connected to the back side of the chip 306 and the interconnect 305 .
需要说明的是，本说明书采用递进的方式描述，在后描述的包封结构重点说明的都是与在前描述的面板级扇出型双面互联的封装方法的不同之处，各个部分之间相同和相似的地方互相参见即可。It should be noted that this description is described in a progressive manner. The encapsulation structure described later focuses on the differences from the panel-level fan-out double-sided interconnection encapsulation method described previously. Just refer to each other for the same and similar places.
上述描述仅是对本发明较佳实施例的描述，并非对本发明权利范围的任何限定，任何本领域技术人员在不脱离本发明的精神和范围内，都可以利用上述揭示的方法和技术内容对本发明技术方案做出可能的变动和修改，因此，凡是未脱离本发明技术方案的内容，依据本发明的技术实质对以上实施例所作的任何简单修改、等同变化及修饰，均属于本发明技术方案的保护范围。 The above description is only a description of the preferred embodiments of the present invention, and does not limit the scope of rights of the present invention. Any person skilled in the art can use the methods and technical contents disclosed above to improve the present invention without departing from the spirit and scope of the present invention. Possible changes and modifications are made to the technical solution. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention, all belong to the technical solution of the present invention. protected range.

Claims (15)

  1. 一种面板级扇出型双面互联的封装方法，其特征在于，包括：A packaging method for panel-level fan-out double-sided interconnection, which is characterized by including:
    提供互联体和第三载板，所述互联体包括导电结构和隔离所述导电结构的塑封材料，所述互联体的两个相对端面均露出部分所述导电结构；Provide an interconnection body and a third carrier board, the interconnection body includes a conductive structure and a plastic packaging material isolating the conductive structure, and both opposite end surfaces of the interconnection body expose part of the conductive structure;
    将芯片和所述互联体粘贴在所述第三载板的顶面上，所述互联体的一端面粘贴在所述第三载板上；Paste the chip and the interconnect on the top surface of the third carrier board, and paste one end surface of the interconnect on the third carrier board;
    在所述第三载板顶面形成第一塑封层，所述第一塑封层至少包覆所述芯片的侧面以及所述互联体的侧面；以及A first plastic sealing layer is formed on the top surface of the third carrier board, and the first plastic sealing layer covers at least the side of the chip and the side of the interconnect; and
    形成与所述芯片正面和所述互联体电连接的第一再布线层，以及形成与所述芯片背面和所述互联体电连接的第二再布线层。A first rewiring layer electrically connected to the chip front side and the interconnect body is formed, and a second rewiring layer electrically connected to the chip back side and the interconnect body is formed.
  2. 如权利要求1所述的封装方法，其特征在于，所述将芯片和所述互联体粘贴在所述第三载板的顶面上，包括：使所述芯片的正面朝向所述第三载板；The packaging method of claim 1, wherein pasting the chip and the interconnect on the top surface of the third carrier includes: making the front side of the chip face the third carrier. plate;
    所述形成与所述芯片正面和所述互联体电连接的第一再布线层，包括：The formation of a first rewiring layer electrically connected to the front side of the chip and the interconnect includes:
    去除所述第三载板，露出所述芯片正面上的芯片引脚以及所述互联体的一端面；在所述芯片的正面一侧形成第一再布线层，所述第一再布线层与所述芯片引脚和所述导电结构相连接。The third carrier board is removed to expose the chip pins on the front side of the chip and one end surface of the interconnect; a first rewiring layer is formed on the front side of the chip, and the first rewiring layer is The chip pins are connected to the conductive structure.
  3. 如权利要求1所述的封装方法，其特征在于，所述导电结构包括导电柱；所述提供互联体的方法包括：The packaging method of claim 1, wherein the conductive structure includes conductive pillars; the method of providing interconnects includes:
    提供第一载板，并在所述第一载板的顶面形成塑封板，所述塑封板的背面朝向所述第一载板；Provide a first carrier board, and form a plastic sealing plate on the top surface of the first carrier board, with the back side of the plastic sealing board facing the first carrier board;
    形成导电层，所述导电层覆盖所述塑封板的正面；Forming a conductive layer covering the front surface of the plastic sealing board;
    在所述导电层远离所述塑封板的一侧设置第二载板，并去除所述第一载板，露出所述塑封板的背面；A second carrier plate is provided on the side of the conductive layer away from the plastic sealing board, and the first carrier board is removed to expose the back side of the plastic sealing board;
    在所述塑封板中形成多个导通孔，所述多个导通孔贯穿所述塑封板且露出部分所述导电层； A plurality of via holes are formed in the plastic packaging board, and the plurality of via holes penetrate the plastic packaging board and expose part of the conductive layer;
    以所述导电层作为导电种子层，从所述多个导通孔的孔底朝向孔口电镀形成所述多个导电柱，所述导电柱填满对应的所述导通孔；以及Using the conductive layer as a conductive seed layer, the plurality of conductive pillars are formed by electroplating from the bottom of the plurality of via holes toward the hole openings, and the conductive pillars fill the corresponding via holes; and
    去除所述第二载板和所述导电层，切割所述塑封板，形成多个所述互联体。The second carrier board and the conductive layer are removed, and the plastic sealing board is cut to form a plurality of interconnections.
  4. 如权利要求3所述的封装方法，其特征在于，所述以所述导电层作为导电种子层，从所述多个导通孔的孔底朝向孔口电镀形成所述多个导电柱，包括：The packaging method according to claim 3, wherein the conductive layer is used as a conductive seed layer, and the plurality of conductive pillars are formed by electroplating from the bottom of the plurality of via holes toward the hole opening, including :
    以所述导电层作为导电种子层，从所述多个导通孔的孔底朝向孔口电镀形成电镀材料层，且所述电镀材料层凸出所述导通孔的孔口；以及Using the conductive layer as a conductive seed layer, electroplating from the bottom of the plurality of via holes toward the openings forms an electroplating material layer, and the electroplating material layer protrudes from the openings of the via holes; and
    去除所述电镀材料层凸出于所述导通孔孔口的部分，形成所述多个导电柱。The portion of the electroplating material layer protruding from the opening of the via hole is removed to form the plurality of conductive pillars.
  5. 如权利要求1所述的封装方法，其特征在于，所述导电结构包括互联的多层线路图形层；所述提供互联体的方法包括：The packaging method of claim 1, wherein the conductive structure includes an interconnected multi-layer circuit pattern layer; the method of providing interconnects includes:
    提供塑封板，所述塑封板具有相对的正面和背面；Provide a plastic sealing board, the plastic sealing board has an opposite front and a back;
    在所述塑封板的正面形成第一线路图形层；Form a first circuit pattern layer on the front side of the plastic sealing board;
    在所述塑封板中形成多个第一导通孔，所述多个第一导通孔贯穿所述塑封板且均露出部分所述第一线路图形层；A plurality of first via holes are formed in the plastic packaging board, and the plurality of first via holes penetrate the plastic packaging board and expose part of the first circuit pattern layer;
    以所述第一线路图形层作为导电种子层，从所述多个第一导通孔的孔底朝向孔口电镀形成所述多个第一导电柱，所述第一导电柱填满对应的所述第一导通孔；Using the first circuit pattern layer as a conductive seed layer, the plurality of first conductive pillars are electroplated from the bottom of the plurality of first via holes toward the hole openings, and the first conductive pillars fill the corresponding the first via hole;
    在所述塑封板的背面形成第二线路图形层，所述第二线路图形层与所述多个第一导电柱相连接；A second circuit pattern layer is formed on the back side of the plastic board, and the second circuit pattern layer is connected to the plurality of first conductive pillars;
    形成覆盖所述第二线路图形层的塑封材料层；Forming a plastic sealing material layer covering the second circuit pattern layer;
    在所述塑封材料层中形成多个第二导通孔，所述多个第二导通孔均露出部分所述第二线路图形层；A plurality of second via holes are formed in the plastic sealing material layer, and each of the plurality of second via holes exposes part of the second circuit pattern layer;
    以所述第二线路图形层作为导电种子层，从所述多个第二导通孔的孔底朝向孔口电镀形成所述多个第二导电柱，所述第二导电柱填满对应的所述第二导通孔； Using the second circuit pattern layer as a conductive seed layer, the plurality of second conductive pillars are electroplated from the bottom of the plurality of second via holes toward the hole openings, and the second conductive pillars fill the corresponding the second via hole;
    在所述塑封材料层背向所述第二线路图形层的表面形成第三线路图形层，所述第三线路图形层与所述多个第二导电柱相连接；以及A third circuit pattern layer is formed on the surface of the plastic sealing material layer facing away from the second circuit pattern layer, and the third circuit pattern layer is connected to the plurality of second conductive pillars; and
    执行切割工艺，形成多个所述互联体。A cutting process is performed to form a plurality of interconnected bodies.
  6. 如权利要求5所述的封装方法，其特征在于，所述在所述塑封材料层背向所述第二线路图形层的表面形成第三线路图形层之后，重复执行形成塑封材料层、形成导通孔、在导通孔中形成导电柱、以及在塑封材料层上形成线路图形层的步骤，以形成多层的互联体。The packaging method according to claim 5, wherein after the third circuit pattern layer is formed on the surface of the plastic sealing material layer facing away from the second circuit pattern layer, the forming of the plastic sealing material layer and the formation of the conductor pattern layer are repeated. The steps of forming a through hole, forming a conductive pillar in the through hole, and forming a circuit pattern layer on the molding material layer to form a multi-layered interconnect.
  7. 如权利要求2所述的封装方法，其特征在于，所述在所述第三载板顶面形成第一塑封层，所述第一塑封层至少包覆所述芯片的侧面以及所述互联体的侧面，包括：形成第一塑封层，所述第一塑封层覆盖所述第三载板的顶面、所述芯片的侧面和背面以及所述互联体的侧面和另一端面。The packaging method of claim 2, wherein a first plastic sealing layer is formed on the top surface of the third carrier board, and the first plastic sealing layer covers at least the side of the chip and the interconnector. The side surface includes: forming a first plastic encapsulation layer, the first plastic encapsulation layer covering the top surface of the third carrier board, the side and back of the chip, and the side and other end surface of the interconnector.
  8. 如权利要求7所述的封装方法，其特征在于，所述互联体的原始厚度大于所述芯片的原始厚度；所述形成与所述芯片背面和所述互联体电连接的第二再布线层，包括：研磨所述第一塑封层远离所述芯片正面的表面去除所述第一塑封层的部分厚度，同时去除所述互联体的部分厚度，露出所述互联体的另一端面，在所述第一塑封层中形成盲孔，所述盲孔露出所述芯片的部分背面，以及形成与所述芯片背面和所述互联体电连接的第二再布线层，所述第二再布线层填充所述盲孔且覆盖所述盲孔的内表面；The packaging method of claim 7, wherein the original thickness of the interconnect is greater than the original thickness of the chip; and forming a second rewiring layer electrically connected to the backside of the chip and the interconnect , including: grinding the surface of the first plastic layer away from the front surface of the chip to remove part of the thickness of the first plastic layer, and simultaneously removing part of the thickness of the interconnect, exposing the other end surface of the interconnect, where Blind holes are formed in the first plastic encapsulation layer, the blind holes expose part of the back side of the chip, and a second rewiring layer electrically connected to the back side of the chip and the interconnect is formed, and the second rewiring layer Filling the blind hole and covering the inner surface of the blind hole;
    或者，or,
    所述互联体的原始厚度等于所述芯片的原始厚度；所述形成与所述芯片背面和所述互联体电连接的第二再布线层，包括：研磨所述第一塑封层远离所述芯片正面的表面去除所述第一塑封层的部分厚度，同时露出所述芯片的背面以及所述互联体的另一端面，形成与所述芯片背面和所述互联体电连接的第二再布线层；The original thickness of the interconnect is equal to the original thickness of the chip; forming a second rewiring layer electrically connected to the backside of the chip and the interconnect includes: grinding the first plastic layer away from the chip The front surface removes part of the thickness of the first plastic encapsulation layer, while exposing the back side of the chip and the other end surface of the interconnect, forming a second rewiring layer electrically connected to the back side of the chip and the interconnect. ;
    或者，or,
    所述互联体的原始厚度大于所述芯片的原始厚度；所述形成与所述芯片背面和所述互联体电连接的第二再布线层，包括：研磨所述第一塑封层远离所述芯片正面的表面去除所述第一塑封层的部分厚度，露出所述互联体的另 一端面；继续研磨所述第一塑封层和所述互联体的另一端面，直至露出所述芯片的背面，形成与所述芯片背面和所述互联体电连接的第二再布线层；The original thickness of the interconnect is greater than the original thickness of the chip; forming a second rewiring layer electrically connected to the backside of the chip and the interconnect includes: grinding the first plastic layer away from the chip The front surface removes part of the thickness of the first plastic sealing layer, exposing the other side of the interconnect One end surface; continue grinding the first plastic encapsulation layer and the other end surface of the interconnect until the back of the chip is exposed, forming a second rewiring layer electrically connected to the back of the chip and the interconnect;
    或者，or,
    所述互联体的原始厚度小于所述芯片的厚度；所述形成与所述芯片背面和所述互联体电连接的第二再布线层，包括：研磨所述第一塑封层远离所述芯片正面的表面去除所述第一塑封层的部分厚度，露出所述芯片的背面，继续研磨所述芯片的背面和所述第一塑封层，露出所述互联体的另一端面，形成与所述芯片背面和所述互联体电连接的第二再布线层。The original thickness of the interconnect is smaller than the thickness of the chip; forming a second rewiring layer electrically connected to the back of the chip and the interconnect includes: grinding the first plastic layer away from the front of the chip Remove part of the thickness of the first plastic sealing layer from the surface to expose the back of the chip. Continue grinding the back of the chip and the first plastic sealing layer to expose the other end surface of the interconnector to form a connection with the chip. A second redistribution layer electrically connected to the interconnect on the back side.
  9. 如权利要求1至权利要求8任意一项所述的封装方法，其特征在于，所述第一塑封层的材质和所述互联体中塑封材料的材质相同。The packaging method according to any one of claims 1 to 8, wherein the material of the first plastic layer is the same as the material of the plastic material in the interconnect body.
  10. 如权利要求1至权利要求8任意一项所述的封装方法，其特征在于，所述芯片和所述互联体的数量均为多个，多个所述互联体包括多个第一互联体和多个第二互联体；The packaging method according to any one of claims 1 to 8, characterized in that the number of the chips and the interconnectors is multiple, and the plurality of interconnectors include a plurality of first interconnectors and Multiple second interconnections;
    所述形成与所述芯片正面和所述互联体电连接的第一再布线层，以及形成与所述芯片背面和所述互联体电连接的第二再布线层之后，部分数量的所述芯片与对应的所述第一互联体或所述第二互联体电连接，部分数量的所述芯片与对应的所述第一互联体和所述第二互联体电连接；或者，每颗所述芯片均与对应的所述第一互联体和所述第二互联体电连接。After forming the first rewiring layer electrically connected to the front side of the chip and the interconnection body, and forming the second rewiring layer electrically connected to the backside of the chip and the interconnection body, a partial number of the chips are electrically connected to the corresponding first interconnector or the second interconnector, and a partial number of the chips are electrically connected to the corresponding first interconnector and the second interconnector; or, each of the chips Each chip is electrically connected to the corresponding first interconnection body and the second interconnection body.
  11. 一种包封结构，其特征在于，所述包封结构包括：An encapsulation structure, characterized in that the encapsulation structure includes:
    芯片；chip;
    互联体，所述互联体包括导电结构和隔离所述导电结构的塑封材料，所述互联体的两个相对端面均露出部分所述导电结构；An interconnection body, the interconnection body includes a conductive structure and a plastic sealing material isolating the conductive structure, and both opposite end surfaces of the interconnection body expose part of the conductive structure;
    第一塑封层，所述第一塑封层至少包覆所述芯片的侧面以及所述互联体的侧面；所述互联体和所述第一塑封层在不同的步骤中形成；A first plastic encapsulation layer, the first plastic encapsulation layer covers at least the side of the chip and the side of the interconnect; the interconnect and the first plastic encapsulation layer are formed in different steps;
    第一再布线层，与所述芯片正面和所述互联体电连接；以及A first rewiring layer electrically connected to the chip front side and the interconnect; and
    第二再布线层，与所述芯片背面和所述互联体电连接。The second rewiring layer is electrically connected to the backside of the chip and the interconnect.
  12. 一种用于半导体封装的互联体的制备方法，其特征在于，包括： A method for preparing interconnects for semiconductor packaging, which is characterized by including:
    提供第一载板，并在所述第一载板的顶面形成塑封板，所述塑封板的背面朝向所述第一载板；Provide a first carrier board, and form a plastic sealing plate on the top surface of the first carrier board, with the back side of the plastic sealing board facing the first carrier board;
    形成导电层，所述导电层覆盖所述塑封板的正面；Forming a conductive layer covering the front surface of the plastic sealing board;
    在所述导电层远离所述塑封板的一侧设置第二载板，并去除所述第一载板，露出所述塑封板的背面；A second carrier plate is provided on the side of the conductive layer away from the plastic sealing board, and the first carrier board is removed to expose the back side of the plastic sealing board;
    在所述塑封板中形成多个导通孔，所述多个导通孔贯穿所述塑封板且露出部分所述导电层；A plurality of via holes are formed in the plastic packaging board, and the plurality of via holes penetrate the plastic packaging board and expose part of the conductive layer;
    以所述导电层作为导电种子层，从所述多个导通孔的孔底朝向孔口电镀形成所述多个导电柱，所述导电柱填满对应的所述导通孔；以及Using the conductive layer as a conductive seed layer, the plurality of conductive pillars are formed by electroplating from the bottom of the plurality of via holes toward the hole openings, and the conductive pillars fill the corresponding via holes; and
    去除所述第二载板和所述导电层，切割所述塑封板，形成多个所述互联体。The second carrier board and the conductive layer are removed, and the plastic sealing board is cut to form a plurality of interconnections.
  13. 如权利要求12所述的用于半导体封装的互联体的制备方法，其特征在于，所述以所述导电层作为导电种子层，从所述多个导通孔的孔底朝向孔口电镀形成所述多个导电柱，包括：The method for preparing an interconnect for semiconductor packaging according to claim 12, wherein the conductive layer is used as a conductive seed layer and is formed by electroplating from the bottom of the plurality of via holes toward the hole opening. The plurality of conductive pillars include:
    以所述导电层作为导电种子层，从所述多个导通孔的孔底朝向孔口电镀形成电镀材料层，且所述电镀材料层凸出所述导通孔的孔口；以及Using the conductive layer as a conductive seed layer, electroplating from the bottom of the plurality of via holes toward the openings forms an electroplating material layer, and the electroplating material layer protrudes from the openings of the via holes; and
    去除所述电镀材料层凸出于所述导通孔孔口的部分，形成所述多个导电柱。The portion of the electroplating material layer protruding from the opening of the via hole is removed to form the plurality of conductive pillars.
  14. 一种用于半导体封装的互联体的制备方法，其特征在于，包括：A method for preparing interconnects for semiconductor packaging, which is characterized by including:
    提供塑封板，所述塑封板具有相对的正面和背面；Provide a plastic sealing board, the plastic sealing board having opposite front and back sides;
    在所述塑封板的正面形成第一线路图形层；Form a first circuit pattern layer on the front side of the plastic sealing board;
    在所述塑封板中形成多个第一导通孔，所述多个第一导通孔贯穿所述塑封板且均露出部分所述第一线路图形层；A plurality of first via holes are formed in the plastic packaging board, and the plurality of first via holes penetrate the plastic packaging board and expose part of the first circuit pattern layer;
    以所述第一线路图形层作为导电种子层，从所述多个第一导通孔的孔底朝向孔口电镀形成所述多个第一导电柱，所述第一导电柱填满对应的所述第一导通孔；Using the first circuit pattern layer as a conductive seed layer, the plurality of first conductive pillars are electroplated from the bottom of the plurality of first via holes toward the hole openings, and the first conductive pillars fill the corresponding the first via hole;
    在所述塑封板的背面形成第二线路图形层，所述第二线路图形层与所述多个第一导电柱相连接； A second circuit pattern layer is formed on the back side of the plastic board, and the second circuit pattern layer is connected to the plurality of first conductive pillars;
    形成覆盖所述第二线路图形层的塑封材料层；Forming a plastic sealing material layer covering the second circuit pattern layer;
    在所述塑封材料层中形成多个第二导通孔，所述多个第二导通孔均露出部分所述第二线路图形层；A plurality of second via holes are formed in the plastic sealing material layer, and each of the plurality of second via holes exposes part of the second circuit pattern layer;
    以所述第二线路图形层作为导电种子层，从所述多个第二导通孔的孔底朝向孔口电镀形成所述多个第二导电柱，所述第二导电柱填满对应的所述第二导通孔；Using the second circuit pattern layer as a conductive seed layer, the plurality of second conductive pillars are electroplated from the bottom of the plurality of second via holes toward the hole openings, and the second conductive pillars fill the corresponding the second via hole;
    在所述塑封材料层背向所述第二线路图形层的表面形成第三线路图形层，所述第三线路图形层与所述多个第二导电柱相连接；以及A third circuit pattern layer is formed on the surface of the plastic sealing material layer facing away from the second circuit pattern layer, and the third circuit pattern layer is connected to the plurality of second conductive pillars; and
    执行切割工艺，形成多个所述互联体。A cutting process is performed to form a plurality of interconnected bodies.
  15. 如权利要求14所述的用于半导体封装的互联体的制备方法，其特征在于，所述在所述塑封材料层背向所述第二线路图形层的表面形成第三线路图形层之后，重复执行形成塑封材料层、形成导通孔、在导通孔中形成导电柱、以及在塑封材料层上形成线路图形层的步骤，以形成多层的互联体。 The method for preparing an interconnect for semiconductor packaging according to claim 14, wherein after forming a third circuit pattern layer on the surface of the plastic sealing material layer facing away from the second circuit pattern layer, repeat The steps of forming a molding material layer, forming via holes, forming conductive pillars in the via holes, and forming a circuit pattern layer on the molding material layer are performed to form a multi-layer interconnect.
PCT/CN2023/088661 2022-06-27 2023-04-17 Panel-level fan-out double-sided interconnection packaging method and encapsulation structure WO2024001432A1 (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105140213A (en) * 2015-09-24 2015-12-09 中芯长电半导体（江阴）有限公司 Chip packaging structure and chip packaging method
CN108389823A (en) * 2018-01-31 2018-08-10 浙江卓晶科技有限公司 For multi-chip wafer scale fan-out-type 3 D stereo encapsulating structure and its packaging technology
US20210098375A1 (en) * 2019-09-27 2021-04-01 Loke Yip Foo Embedded dual-sided interconnect bridges for integrated-circuit packages
WO2022095695A1 (en) * 2020-11-04 2022-05-12 矽磐微电子(重庆)有限公司 Mcm encapsulation structure and manufacturing method therefor
WO2022105160A1 (en) * 2020-11-17 2022-05-27 江苏长电科技股份有限公司 Antenna packaging structure, and manufacturing method for antenna packaging structure

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105140213A (en) * 2015-09-24 2015-12-09 中芯长电半导体（江阴）有限公司 Chip packaging structure and chip packaging method
CN108389823A (en) * 2018-01-31 2018-08-10 浙江卓晶科技有限公司 For multi-chip wafer scale fan-out-type 3 D stereo encapsulating structure and its packaging technology
US20210098375A1 (en) * 2019-09-27 2021-04-01 Loke Yip Foo Embedded dual-sided interconnect bridges for integrated-circuit packages
WO2022095695A1 (en) * 2020-11-04 2022-05-12 矽磐微电子(重庆)有限公司 Mcm encapsulation structure and manufacturing method therefor
WO2022105160A1 (en) * 2020-11-17 2022-05-27 江苏长电科技股份有限公司 Antenna packaging structure, and manufacturing method for antenna packaging structure

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