WO2024022273A1

WO2024022273A1 - Fanout system-level packaging structure and manufacturing method therefor

Info

Publication number: WO2024022273A1
Application number: PCT/CN2023/108819
Authority: WO
Inventors: 霍炎; 周文武
Original assignee: 矽磐微电子(重庆)有限公司
Priority date: 2022-07-25
Filing date: 2023-07-24
Publication date: 2024-02-01
Also published as: CN117525061A

Abstract

In a fanout system-level packaging structure and manufacturing method therefor provided by the present application, each interconnect comprises an electrically conductive structure and a plastic packaging material, a portion of the electrically conductive structure being exposed at two opposite end faces of each interconnect; a first plastic packaging layer at least covers a side face of multiple chips and a side face of the multiple interconnects; a redistribution layer comprises a first redistribution layer located at a front face of the multiple chips and a second redistribution layer located at a back face of the multiple chips, the first redistribution layer being electrically connected to the front face of the multiple chips and one end face of the multiple interconnects, the second redistribution layer being electrically connected to another end face of the multiple interconnects, and multiple electrical components being mounted on the redistribution layer.

Description

Fan-out system-level packaging structure and manufacturing method thereof

Technical field

The present application relates to the field of semiconductor packaging technology, and in particular to a fan-out system-level packaging structure and a manufacturing method thereof.

Background technique

With the continuous improvement of chip technology, the number of signals accommodated per unit area continues to increase, and the number of IOs (Input Output, input and output) of the chip continues to increase, resulting in the continuous reduction of the distance between the signal IOs of the chip. The Printed Circuit Board (PCB) industry lags behind the development of the chip industry. PCB-based packaging technology is limited by the process capabilities of PCB. The line width and line spacing cannot be too small, so it cannot meet the needs of today's high-density chip systems. level design requirements.

Contents of the invention

This application provides a method for manufacturing a fan-out system-level packaging structure. The production method includes:

Provide a third carrier board and provide a plurality of interconnectors, each of the interconnectors includes a conductive structure and a molding material that encapsulates the conductive structure, and two opposite end surfaces of each of the interconnectors expose part of the conductive structure ;

Paste and arrange a plurality of chips and the plurality of interconnects on the top surface of the third carrier board;

A first plastic sealing layer is formed on the top surface of the third carrier board, and the first plastic sealing layer covers at least the sides of the plurality of chips and the sides of the plurality of interconnects;

A rewiring layer is formed on the surface of the first plastic encapsulation layer. The rewiring layer includes a first rewiring layer located on the front side of the plurality of chips and a second rewiring layer located on the back side of the plurality of chips. , the first rewiring layer is electrically connected to the front surfaces of the plurality of chips and one end surface of the plurality of interconnections, and the second rewiring layer is electrically connected to the other end surface of the plurality of interconnections; as well as

A plurality of electrical components are mounted on the redistribution layer, and the plurality of electrical components are electrically connected to the redistribution layer.

Optionally, the conductive structure includes conductive pillars; the multiple interconnectors are provided, including:

Provide a first carrier plate, and form a plastic sealing plate on the top surface of the first carrier plate, the plastic sealing plate has an opposite front and a back, and the front of the plastic sealing plate is away from the first carrier plate;

Forming a conductive layer covering the front surface of the plastic sealing board;

A second carrier plate is provided on the side of the conductive layer away from the plastic sealing board, and the first carrier board is removed to expose the back side of the plastic sealing board;

A plurality of via holes are formed in the plastic packaging board, and the plurality of via holes penetrate the plastic packaging board and expose part of the conductive layer;

Using the conductive layer as a conductive seed layer, the plurality of conductive pillars are formed by electroplating in the plurality of via holes, and the end surfaces of the conductive pillars are flush with the back surface of the plastic packaging board; and

The second carrier board and the conductive layer are removed, and the plastic sealing board is cut to form a plurality of interconnections.

Optionally, the conductive structure includes interconnected multi-layer circuit pattern layers and conductive pillars; the multiple interconnectors are provided, including:

Provide a plastic sealing board, the plastic sealing board has an opposite front and a back, and a first circuit pattern layer is formed on the front of the plastic sealing board;

A plurality of first via holes are formed in the plastic packaging board, and the plurality of first via holes penetrate the plastic packaging board and expose part of the first circuit pattern layer;

Using the first circuit pattern layer as a conductive seed layer, a plurality of first conductive pillars are formed by electroplating from the bottom of the plurality of first via holes toward the hole openings, and the top surfaces of the plurality of first conductive pillars are The back side of the plastic sealing board is flush;

A second circuit pattern layer is formed on the back side of the plastic board, and the second circuit pattern layer is connected to the plurality of first conductive pillars;

Forming a plastic material layer covering the second circuit pattern layer, forming a plurality of second via holes in the plastic material layer, each of the plurality of second via holes exposing part of the second circuit pattern layer;

Using the second circuit pattern layer as a conductive seed layer, a plurality of second conductive pillars are formed by electroplating from the bottom of the plurality of second via holes toward the hole openings. The plurality of second conductive pillars are in contact with the plastic sealing layer. The surface of the material layer away from the plastic sealing board is flush, and a third circuit pattern layer is formed on the surface of the plastic sealing material layer away from the second circuit pattern layer. The third circuit pattern layer is in contact with the plurality of second circuit pattern layers. The conductive pillars are connected;

A cutting process is performed to form a plurality of interconnected bodies.

Optionally, pasting and arranging the plurality of chips and the plurality of interconnects on the top surface of the third carrier board includes: pasting the plurality of chips face down on the third carrier board. on the top surface of the carrier board, and one end surface of the plurality of interconnectors is pasted on the top surface of the third carrier board.

Optionally, forming a rewiring layer on the surface of the first plastic encapsulation layer includes: removing the third carrier board to expose the micro-bumps on the front surfaces of the multiple chips and exposing the end faces of the interconnectors; The first rewiring layer is formed on the front side of the plurality of chips; and the second rewiring layer is formed on the back side of the plurality of chips.

Optionally, the original thickness of the interconnect is greater than the thickness of the chip; in the step of forming a first plastic sealing layer on the top surface of the third carrier board, the first plastic sealing layer covers the plurality of The back side of the chip and the end surfaces of the plurality of interconnectors away from the third carrier board;

Forming a rewiring layer on the surface of the first plastic encapsulation layer includes: after forming the first rewiring layer on the front side of the plurality of chips, removing a part of the thickness of the first plastic encapsulation layer, Expose the end surfaces of the plurality of interconnects away from the first rewiring layer; continue to remove part of the thickness of the first plastic layer and simultaneously remove part of the thickness of the plurality of interconnects; The second rewiring layer is formed on the side.

Optionally, mounting the plurality of electrical components on the rewiring layer includes: mounting the plurality of electrical components on one of the first rewiring layer and the second rewiring layer. element.

Optionally, the manufacturing method includes: after mounting a plurality of electrical components on the rewiring layer, disposing on the other of the first rewiring layer and the second rewiring layer Solder balls.

Optionally, the manufacturing method includes: after mounting the plurality of electrical components on the rewiring layer, forming a second plastic sealing layer, and the second plastic sealing layer covers the side surfaces of the plurality of electrical components. And the surface of the plurality of electrical components away from the first plastic sealing layer.

Optionally, the plurality of electrical components include two or more electrical components.

This application also provides a fan-out system-level packaging structure. The fan-out system-level packaging structure includes:

A plurality of chips and interconnects, the interconnects include a conductive structure and a plastic sealing material that encapsulates the conductive structures, and both opposite end surfaces of the interconnects expose part of the conductive structures;

A first plastic encapsulation layer covers at least the side surfaces of the plurality of chips and the side surfaces of the interconnector; the interconnector and the first plastic encapsulation layer are formed separately;

A rewiring layer formed on the surface of the first plastic encapsulation layer. The rewiring layer includes a first rewiring layer located on the front side of the plurality of chips and a second rewiring layer located on the back side of the plurality of chips. layer, the first rewiring layer is electrically connected to the front surfaces of the plurality of chips and one end surface of the interconnect body, and the second rewiring layer is electrically connected to the other end surface of the interconnect body; and

A plurality of electrical components are mounted on the rewiring layer.

Optionally, the conductive structure includes conductive pillars, the plastic packaging material includes a plastic packaging plate, a plurality of conductive holes penetrating the plastic packaging plate are formed in the plastic packaging plate, and the plurality of conductive pillars are formed on the plastic packaging plate through electroplating. In the plurality of via holes, the end surfaces of the plurality of conductive pillars are flush with the surface of the plastic sealing board.

Optionally, the conductive structure includes interconnected multi-layer circuit pattern layers and conductive pillars, and the plastic packaging material includes a plastic packaging board and a plastic packaging material layer;

The plastic sealing board has an opposite front and a back, and the first circuit pattern layer is formed on the front of the plastic sealing board;

A plurality of first conductive pillars are formed by electroplating in the plurality of first via holes, and the top surfaces of the plurality of first conductive pillars are in contact with each other. The back side of the plastic sealing board is flush;

A second circuit pattern layer is formed on the back of the plastic board, and the second circuit pattern layer is connected to the plurality of first conductive pillars;

The plastic sealing material layer covers the second circuit pattern layer, and a plurality of second conductive holes are formed in the plastic sealing material layer, and the plurality of second conductive holes each expose part of the second circuit pattern. layer;

A plurality of second conductive pillars are formed by electroplating in the plurality of second via holes. The plurality of second conductive pillars are flush with the surface of the plastic sealing material layer away from the plastic sealing board, and are in the plastic sealing material layer. A third circuit pattern layer is formed on a surface of the layer away from the second circuit pattern layer, and the third circuit pattern layer is connected to the plurality of second conductive pillars.

Description of drawings

Figure 1 is a schematic diagram of a fan-out system-level packaging structure.

Figure 2 is a schematic diagram of a fan-out system-level packaging structure.

Figure 3 is a schematic diagram of a fan-out system-level packaging structure.

FIG. 4 is a flow chart of a method for manufacturing a fan-out system-in-package structure according to an embodiment of the present application.

5 to 10 are schematic diagrams of the manufacturing process of an interconnect according to an embodiment of the present application.

11 to 16 are schematic diagrams of the manufacturing process of an interconnect according to another embodiment of the present application.

17 to 32 are step-by-step structural diagrams of manufacturing a fan-out system-in-package structure according to an embodiment of the present application.

FIG. 33 is a schematic cross-sectional view of a fan-out system-in-package structure according to an embodiment of the present application.

Explanation of reference symbols:
(Figure 1 to Figure 3) 101-chip; 102-conductive metal block; 103-electrical component; 104-printed circuit board; 105-
Front rewiring layer; 106-back rewiring layer; 107-interconnect hole;
(Figure 5 to Figure 33) 200a-first carrier board; 200b-second carrier board; 201a-first adhesive layer; 201b-second adhesive layer; 202-plastic board; 2021-front side of plastic board; 2022 -The back side of the plastic board; 202a-via hole; 203-conductive layer; 204-conductive pillar; 205-interconnect; 206-first circuit pattern layer; 207-first via hole; 208-first conductive pillar; 209-The second circuit pattern layer; 210-Plastic material layer; 211-The second via hole; 212-The second conductive pillar; 213-The third circuit pattern layer; 300-The third carrier board; 301-The third bonding layer; 302-chip; 303-dielectric protective layer; 304-first plastic encapsulation layer; 305-fourth carrier board; 306-fourth adhesive layer; 307-first rewiring layer; 308-first dielectric layer ; 309-fifth carrier board; 310-fifth adhesive layer; 311-second rewiring layer; 312-second dielectric layer; 313-electrical component; 314-second plastic encapsulation layer; 315-solder ball.

Detailed ways

The fan-out system-level packaging structure and its manufacturing method proposed in this application will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present application will become clearer from the following description. It should be noted that the drawings are in a very simplified form and use imprecise proportions, and are only used to conveniently and clearly assist in explaining the embodiments of the present application.

It should be understood that, unless otherwise specified or pointed out, the terms "first", "second", "third" and other descriptions in the specification are only used to distinguish various components, elements, steps, etc. in the specification, rather than to It is used to express the logical relationship or sequential relationship between various components, elements, steps, etc. Spatial relational terms such as "under", "under", "under", "under", "on", "above", etc., in It may be used herein for convenience of description to describe the relationship of one element or feature to other elements or features shown in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "under" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "under" may include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

Compared with system integration on PCB, System Level Package (SIP) can optimize system performance to the maximum extent, avoid repeated packaging, shorten the development cycle, reduce costs, improve integration, and solve the problem of signal IO spacing and chip signal IO spacing. The problem of PCB line width and line spacing not matching well. Existing fan-out system-in-package Technology, especially the technology where chips and electrical components are stacked and packaged in two layers, there are about three implementation solutions for stacking and interconnecting chips and electrical components.

Figure 1 is a schematic diagram of a fan-out system-level packaging structure. Referring to Figure 1, the first solution is to mount the conductive metal block 102 at the same time when the first layer chip 101 is mounted. The conductive metal block 102 is, for example, a copper sheet, and the conductive metal block 102 serves as the first layer chip 101 and the second layer. The layers of electrical components 103 are interconnected by channels. When using the first solution, there are many technical restrictions on the size of the conductive metal block 102 and the mounting spacing during the mounting process. Generally, the conductive metal block 102 with a width below 0.5 mm cannot be mounted, and the mounting spacing generally cannot be less than 0.1 mm, but in actual applications, in order to reduce the package size, the width of the conductive metal blocks 102 needs to be smaller, and the spacing between the conductive metal blocks 102 also needs to be smaller; moreover, the mounted conductive metal blocks 102 need to be molded in the subsequent plastic packaging, etc. Problems such as tilting are prone to occur during processing, resulting in greater yield losses.

Figure 2 is a schematic diagram of a fan-out system-level packaging structure. Referring to Figure 2, the second solution is to mount the printed circuit board 104 at the same time as the first layer chip 101 is mounted. The printed circuit board 104 serves as a channel for interconnection between the first layer chip 101 and the second layer electrical component 103. When using the second solution, when the thickness of the first layer chip 101 is different, printed circuit boards 104 of different thicknesses need to be made, and for different interconnection requirements, different printed circuit boards 104 need to be made to embed interconnections. Therefore, the use of printed circuit board interconnects makes packaging costly.

Figure 3 is a schematic diagram of a fan-out system-level packaging structure. Referring to Figure 3, the third solution is to create a front re-distribution layer (RDL) 105 (Re-Distribution Layer, RDL) on the front of the first-layer chip 101, then open blind holes on the back and make a back re-distribution layer 106 to achieve interconnection. If the third solution is adopted, when the thickness of the first-layer chip 101 is thicker, the corresponding interconnection hole 107 that needs to be opened is also deeper. Usually the depth of the interconnection hole 107 exceeds 150mm. During the fan-out packaging process, for such a Plating deep holes is more difficult, resulting in greater yield loss and the risk of poor reliability.

Therefore, for the fan-out system-level packaging structure, there is an urgent need to solve how to reduce the difficulty and cost of production and improve product yield.

In order to reduce the difficulty and cost of manufacturing a fan-out system-level packaging structure and improve product yield, this application provides a method for manufacturing a fan-out system-level packaging structure. As shown in Figure 4, the manufacturing method of the fan-out system-level packaging structure includes:

S1, provide a third carrier board and provide a plurality of interconnectors, each of the interconnectors includes a conductive structure and a plastic sealing material that encapsulates the conductive structure, and two opposite end surfaces of each of the interconnectors partially expose the conductive structures;

S2. Paste and arrange multiple chips and the plurality of interconnects on the top surface of the third carrier board;

S3, forming a first plastic sealing layer on the top surface of the third carrier board, the first plastic sealing layer covering at least the sides of the plurality of chips and the sides of the plurality of interconnects;

S4. Form a rewiring layer on the surface of the first plastic encapsulation layer. The rewiring layer includes a first rewiring layer located on the front side of the multiple chips and a second rewiring layer located on the back side of the multiple chips. A wiring layer, the first rewiring layer is electrically connected to the front surfaces of the plurality of chips and one end surface of the plurality of interconnections, and the second rewiring layer is electrically connected to the other end surface of the plurality of interconnections. connect;

S5: Mount multiple electrical components on the rewiring layer, and the multiple electrical components are electrically connected to the rewiring layer.

It should be understood that although various steps in the flowchart of FIG. 4 are shown in sequence as indicated by arrows, these steps are not necessarily executed in the order indicated by arrows. Unless explicitly stated in this article, there is no strict order restriction on the execution of these steps, and these steps can be executed in other orders. Moreover, at least some of the steps in Figure 4 may include multiple steps or stages. These steps or stages are not necessarily executed at the same time, but may be executed at different times. The execution order of these steps or stages is also It does not necessarily need to be performed sequentially, but may be performed in turn or alternately with other steps or at least part of steps or stages in other steps.

In order to improve the versatility of the interconnect, in some embodiments, the conductive structure of the interconnect includes conductive pillars, and the number of conductive pillars in an interconnect is one or more. Referring to FIGS. 5 to 10 , a method of providing interconnections may include step-by-step Steps S11 to S16.

Sub-step S11: As shown in Figure 5, a first carrier plate 200a is provided, and a plastic sealing plate 202 is formed on the top surface of the first carrier plate 200a. The plastic sealing plate 202 has an opposite front and a back, and the front 2021 of the plastic sealing plate is far away from The first carrier board 200a. Specifically, a first adhesive layer 201a is provided between the first carrier plate 200a and the plastic sealing plate 202, that is, the plastic sealing plate 202 is pasted on the first carrier plate 200a through the first adhesive layer 201a. It should be noted that the “adhesive layer” mentioned in this application is a “debondable adhesive layer”. For example, the first carrier plate 200a and the plastic sealing plate 202 fixed by the first adhesive layer 201a can subsequently be connected to each other. Detach.

Step S12: As shown in Figure 6, a conductive layer 203 is formed, and the conductive layer 203 covers the front surface 2021 of the plastic sealing plate. The formation method of the conductive layer 203 may include: forming a thin film layer on the front side 2021 of the plastic board through a sputtering process or an electroless plating process. The thin film layer is, for example, a titanium layer, a copper layer or a titanium-copper layer, and then electroplating on the thin film layer. Copper forms the conductive layer 203 of a set thickness. Through the combination of the sputtering process and the electroplating process or the combination of the chemical plating process and the electroplating process, the conductive layer 203 with a certain thickness can be formed quickly, which helps to ensure the conductive effect of the conductive layer 203. In this embodiment, the thin film layer is electroplated with copper; but it is not limited to this. In other embodiments, the thin film layer is electroplated with nickel or other metals. The conductive layer 203 may also be formed only through a sputtering process or a chemical plating process.

Substep S13: Referring to Figures 6 and 7, set a second carrier plate 200b on the side of the conductive layer 203 away from the plastic sealing plate 202, and remove the first carrier plate 200a and the first adhesive layer 201a, Expose the backside 2022 of the plastic sealing board. A second adhesive layer 201b may be disposed between the second carrier plate 200b and the conductive layer 203.

Sub-step S14: Continuing to refer to FIG. 7 , a plurality of conductive holes 202 a are formed in the plastic sealing plate 202 , and the plurality of conductive holes 202 a penetrate the plastic sealing plate 202 and expose part of the conductive layer 203 . Specifically, a plurality of the conductive holes 202a can be formed by opening holes from the side of the plastic sealing plate 202 away from the second carrier plate 200b toward the second carrier plate 200b through a laser process, and the conductive layer 203 can serve as a barrier for laser openings. layer.

Sub-step S15: As shown in FIG. 8, using the conductive layer 203 as a conductive seed layer, electroplating the plurality of conductive pillars 204 in the plurality of via holes 202a. The end surfaces of the conductive pillars 204 are in contact with the conductive pillars 204. The backside 2022 of the plastic sealing board is flush. It should be noted that “flush” in this application can indicate that the height difference between the electrical pillar 204 and the backside 2022 of the plastic board is within a small range.

In order to ensure that the end surfaces of the conductive pillars 204 are flush with the back surface 2022 of the plastic packaging board, in some embodiments, the method of forming the multiple conductive pillars 204 may include: using the conductive layer 203 as a conductive seed layer, from the multiple via holes 202a The bottom of the hole is electroplated toward the hole opening to form a layer of electroplating material, and the layer of electroplating material protrudes from the opening of the via hole 202a; the portion of the layer of electroplating material that protrudes from the opening of the via hole 202a is removed by grinding to form multiple conductive pillars. 204.

In some embodiments, the method of forming the plurality of conductive pillars 204 may include: using the conductive layer 203 as a conductive seed layer, electroplating from the bottom of the plurality of via holes 202a toward the hole opening to form an electroplating material layer, and the electroplating material layer The via holes 202a are not filled; grinding removes part of the thickness of the plastic board 202 to reduce the depth of the via holes 202a, so that the plating material layers in all via holes 202a are flush with the backside 2022 of the plastic board. After grinding During the process, part of the thickness of the layer of electroplated material can be removed.

Step S16: As shown in FIGS. 8 to 10 , remove the second carrier board 200b, the second adhesive layer 201b and the conductive layer 203, and cut the plastic sealing board 202 to form a plurality of interconnectors 205. After removing the second carrier plate 200b and the second adhesive layer 201b, the conductive layer 203 can be polished and removed using a chemical mechanical polishing process. But it is not limited to this, other suitable processes can be selected to remove the conductive layer 203 according to the material of the conductive layer 203 .

The cross-sectional shape of the conductive pillars 204 in the interconnect 205 may be circular. But it is not limited thereto. The cross-sectional shape of the conductive pillar 204 may also be square or elliptical. The dimensions (such as length, width, and thickness) of the interconnect 205 and the dimensions of the conductive pillars 204 inside the interconnect 205 can be designed according to product requirements, and the number of the conductive pillars 204 in the interconnect 205 can also be set as needed.

In order to increase the product diversity of advanced board level packaging, in some embodiments, the conductive structure in the interconnect body may include interconnected multi-layer circuit pattern layers. Referring to Figures 11 to 16, a method of providing multiple interconnects may include:

As shown in Figure 11, a plastic sealing board 202 is provided, and the plastic sealing board 202 has an opposite front and a back; a first circuit pattern layer 206 is formed on the front surface 2021 of the plastic sealing board. As an example, the first circuit pattern layer 206 may include many A conductive pad, which can subsequently be interconnected with one end of the chip;

As shown in FIG. 12 , a plurality of first via holes 207 are formed in the plastic board 202 , and the plurality of first via holes 207 penetrate the plastic board 202 and expose part of the first circuit pattern layer. 206;

As shown in FIG. 13 , the first circuit pattern layer 206 is used as a conductive seed layer, and the plurality of first conductive pillars 208 are formed by electroplating from the bottom of the plurality of first via holes 207 toward the hole openings. The first conductive pillars 208 The top surface is flush with the back 2022 of the plastic board;

As shown in Figure 14, a second circuit pattern layer 209 is formed on the back surface 2022 of the plastic sealing board, and the second circuit pattern layer 209 is connected to the plurality of first conductive pillars 208;

As shown in FIG. 15 , a plastic sealing material layer 210 covering the second circuit pattern layer 209 can be formed by lamination or pressing, and a plurality of second via holes 211 are formed in the plastic sealing material layer 210 . Each second via hole 211 exposes part of the second circuit pattern layer 209;

As shown in FIG. 16 , using the second circuit pattern layer 209 as a conductive seed layer, a plurality of second conductive pillars 212 are formed by electroplating from the bottoms of the plurality of second via holes 211 toward the hole openings. The second conductive pillars 212 The third circuit pattern layer 213 is formed on the surface of the plastic sealing material layer 210 away from the second circuit pattern layer 209 and is flush with the surface of the plastic sealing material layer 210 away from the plastic sealing plate 202. The third circuit pattern layer 213 is in contact with the second circuit pattern layer 209. The plurality of second conductive pillars 212 are connected;

Then, a cutting process is performed to form a plurality of interconnected bodies. Specifically, divide the plastic sealing board 202, the plastic sealing material layer 210, the first circuit pattern layer 206, the plurality of first conductive pillars 208, the second circuit pattern layer 209, the plurality of second conductive pillars 212 and the third circuit pattern layer 213, Multiple interconnections are formed.

It should be noted that after the third circuit pattern layer 213 is formed, by repeatedly performing the steps of forming a molding material layer, forming a via hole, forming a conductive pillar in the via hole, and forming a circuit pattern layer on the molding material layer, Can form multi-layer interconnected structures.

The conductive pillars in the interconnect formed above, such as the conductive pillar 204, the first conductive pillar 208 and the second conductive pillar 212, are all formed by reverse conduction plating. The so-called reverse conduction plating refers to the conductive plating at the bottom of the via hole. The conductive layer serves as a conductive seed layer and is electroplated from the bottom of the via hole toward the hole opening to form a conductive pillar. Traditional electroless plating and electroplating can only plate copper on the walls of deep holes and cannot fill the entire hole. This application uses reverse conduction plating and a grinding process to form conductive pillars in the interconnect and make the conductive pillars The two end surfaces can be flush with the front and back of the plastic board respectively, ensuring that the cross-sectional area of the conductive material (such as copper) in the hole meets the requirements, so that each interconnector has good flow capacity, which is conducive to establishing a stable interconnection channels to improve product yield.

The manufacturing method of the fan-out system-level packaging structure of the present application will be continued to be described below with reference to FIGS. 17 to 32 . Among them, Figure 17 and Figure 29 are plan views, and the rest are cross-sectional views.

As shown in Figures 17 and 18, a plurality of chips 302 and a plurality of interconnects 205 are pasted and arranged on the top surface of the third carrier board 300, and one end surface of the plurality of interconnects 205 is pasted on on the top surface of the third carrier plate 300 .

A third adhesive layer 301 is formed on the top surface of the third carrier board 300. The plurality of chips 302 and the plurality of interconnects 205 are adhered and fixed to the top surface of the third carrier board 300 through the third adhesive layer 301, and the third adhesive layer 301 is formed on the top surface of the third carrier board 300. Layer 301 is a debondable adhesive layer.

In this embodiment, four chips 302 and subsequently installed electrical components use an interconnector 205 as an interconnection channel, that is, four chips 302 correspond to one interconnector 205, but it is not limited to this. The number of chips corresponding to an interconnect 205 can be set according to product needs.

The chip 302 may be a semiconductor chip, a passive component, a packaged package, or the like. The plurality of chips 302 pasted on the top surface of the third carrier board 300 may be the same, but are not limited thereto. The plurality of chips 302 pasted on the top surface of the third carrier board 300 may also be different.

As shown in FIG. 18 , a dielectric protective layer 303 is formed on the front surface of the chip 302 . The dielectric protection layer 303 can protect the micro-bumps on the front side of the chip 302 (not shown in the figure). The dielectric protective layer 303 can be a resin film, a build-up film (Ajinomoto Build-up film, ABF) or a PI film (Polyimide Film, polyimide film), etc. The micro-bumps may be solder pads and/or micro-bump structures located above the solder pads.

Preferably, in this embodiment, referring to FIG. 18 , the chip 302 is pasted face down on the third carrier board 300 , and one end surface of the plurality of interconnects 205 is pasted on the top of the third carrier board 300 . on the surface, and then remove the third After the board 300 and the third adhesive layer 301, the dielectric protective layer 303 on the front side of the chip 302 can be exposed. There is no need to grind the first plastic sealing layer, so that the front side of the chip 302 can be effectively protected, which is beneficial to improving the packaging yield. .

System-in-package chips generally do not require the backside of the chip to be connected to the rewiring layer. In order to protect the backside of the chip 302, preferably, in this embodiment, the original thickness of the interconnect 205 is greater than the thickness of the chip 302. In other embodiments, the original thickness of interconnect 205 may be equal to the thickness of chip 302 .

As shown in FIG. 19 , a first plastic sealing layer 304 is formed on the top surface of the third carrier board 300 . The first plastic sealing layer 304 at least covers the sides of the plurality of chips 302 and the plurality of interconnects 205 side. Specifically, the first plastic encapsulation layer 304 covers the back surfaces of the plurality of chips 302 and the end surfaces of the plurality of interconnects 205 away from the third carrier board 300 .

After materials with different coefficients of thermal expansion (CTE) are encapsulated with each other, they show different shrinkage rates in reliability tests. When the internal stress difference caused is too large, it will lead to chip failure. For example, after heating, Materials with different thermal expansion coefficients have different expansion and contraction dimensions, causing defects such as cracking and/or delamination in the boundary areas of different materials. In order to improve the reliability of the product, the thermal expansion coefficient of the material of the first plastic sealing layer 304 and the thermal expansion coefficient of the plastic sealing material in the interconnection body 205 can be similar. Since materials with the same physical and chemical properties are encapsulated with each other, the actual performance shown in various reliability tests is the same or similar, so the physical properties of the plastic packaging materials in the interconnect and the plastic packaging materials used in chip packaging are the same. Chemically identical. Preferably, the material of the first plastic sealing layer 304 is the same as the material of the plastic sealing material in the interconnect 205 , for example, they can both be epoxy resin molding compound (MC-Epoxy Molding Compound, EMC).

Referring to Figure 28, a rewiring layer is formed on the surface of the first plastic encapsulation layer 304. The rewiring layer includes a first rewiring layer 307 located on the front side of the plurality of chips 302 and a first rewiring layer 307 located on the back side of the plurality of chips 302. The second rewiring layer 311 on one side, the first rewiring layer 307 is electrically connected to the front surfaces of the plurality of chips 302 and one end surface of the plurality of interconnects 205, and the second rewiring layer 311 is The other end faces of the plurality of interconnectors 205 are electrically connected.

Specifically, referring to FIGS. 19 and 20 , the third carrier 300 and the third adhesive layer 301 are removed to expose the micro-bumps (not shown in the figure) on the front surfaces of the multiple chips 302 and the end faces of the interconnectors 205 . . It should be noted that when the dielectric protective layer 303 is formed on the front surface of the chip 302, before forming the first rewiring layer 307, part of the dielectric protective layer 303 needs to be removed to expose the microbumps on the front surface of the chip. In order to prevent the first plastic sealing layer 304 from warping after removing the third carrier board 300, before removing the third carrier board 300, a fourth adhesive layer 306 and a fourth adhesive layer 306 are sequentially provided on the side of the first plastic sealing layer 304 away from the third carrier board 300. The fourth carrier board 305.

As shown in FIG. 21 , a first rewiring layer 307 is formed on the front side of the plurality of chips 302 . The method of forming the first rewiring layer 307 may include: forming a patterned circuit layer on the surface of the first plastic encapsulation layer 304 away from the fourth carrier board 305, and the patterned circuit layer is in contact with the micro bumps of the chip 302 and the interconnect 205. Connect, and then form multiple protruding solder pads on the patterned circuit layer. That is, the first rewiring layer 307 may include a patterned circuit layer and bonding pads located on the patterned circuit layer.

As shown in FIG. 22 , a first dielectric layer 308 is formed on the side of the first plastic encapsulation layer 304 away from the fourth carrier board 305 , and the first dielectric layer 308 covers the first rewiring layer 307 . The first dielectric layer 308 may include a resin film, a build-up film, a PI film, or the like.

As shown in FIG. 23 , a part of the thickness of the first dielectric layer 308 is removed by polishing or other methods to expose part of the first rewiring layer 307 , for example, the solder pads of the first rewiring layer 307 are exposed.

Next, the second rewiring layer 311 is formed on the back side of the plurality of chips 302 .

Specifically, referring to Figures 23 and 24, a fifth adhesive layer 310 and a fifth carrier plate 309 are sequentially formed on the first dielectric layer 308, and the fourth carrier plate 305 is turned upward, and then the fourth carrier plate is removed. 305 and the fourth adhesive layer 306. As shown in FIG. 25 , a part of the thickness of the first plastic encapsulation layer 304 is removed by grinding or other processes to expose the end surfaces of the plurality of interconnects 205 away from the first rewiring layer 307 ; as shown in FIG. 26 , in multiple A second rewiring layer 311 is formed on the back side of the chip 302 .

In some embodiments, after exposing the end surfaces of the plurality of interconnects 205 away from the first rewiring layer 307, depending on the thickness of the chip 302, a part of the thickness of the first plastic encapsulation layer can be removed without exposing the back side of the chip 302. 304 removes part of the thickness of multiple interconnects 205 at the same time, thus helping to reduce product thickness.

The method of forming the second rewiring layer 311 may include: forming a patterned circuit layer on a surface of the first plastic layer 304 away from the first rewiring layer 307, and the patterned circuit layer and the plurality of interconnects 205 are located away from the first rewiring layer. The end surfaces of layer 307 are connected to form multiple bonding pads on the patterned circuit layer.

After forming the second rewiring layer 311, as shown in FIG. 27, a second dielectric layer 312 is formed on the side of the first molding layer 304 away from the first rewiring layer 307. The second dielectric layer 312 covers the second rewiring layer 311. Wiring layer 311. As shown in FIG. 28 , part of the thickness of the second dielectric layer 312 is removed by polishing or other methods to expose part of the second rewiring layer 311 , for example, the solder pads of the second rewiring layer 311 are exposed.

Next, a plurality of electrical components are mounted on the rewiring layer (the first rewiring layer 307 or the second rewiring layer 311), and the multiple electrical components are electrically connected to the rewiring layer. The electrical components may be chips or/and passive devices.

In some embodiments, as shown in Figures 29 and 30, multiple electrical components 313 are mounted on the second rewiring layer 311, with the fronts of the multiple electrical components 313 facing down, and the multiple electrical components 313 are in contact with the second rewiring layer 311. The wiring layer 311 is electrically connected. A plurality of electrical components 313 may be mounted on the second rewiring layer 311 through soldering or other methods. The plurality of electrical components 313 may be electrical components of different types and sizes, that is, the multiple electrical components 313 include more than two types of electrical components, but are not limited thereto. The plurality of electrical components 313 may also be the same electrical component. The electrical component 313 may be a chip, a passive electrical component, a packaged package, or the like.

As shown in FIG. 31 , a second plastic sealing layer 314 is formed on the second dielectric layer 312 , and the second plastic sealing layer 314 covers the plurality of electrical components 313 .

Referring to FIGS. 31 and 32 , the fifth carrier board 309 and the fifth adhesive layer 310 are removed, and solder balls 315 are disposed on the first rewiring layer 307 . The solder balls 315 are arranged corresponding to the exposed pads of the first rewiring layer 307 .

In some embodiments, referring to FIG. 33 , a plurality of electrical components 313 are mounted on the first rewiring layer 307 , the front surfaces of the multiple electrical components 313 face the first rewiring layer 307 , and the multiple electrical components 313 are in contact with the first rewiring layer 307 . Layer 307 is electrically connected. The second plastic layer 314 is formed on the first dielectric layer 308 , and the second plastic layer 314 covers the plurality of electrical components 313 . Solder balls 315 are formed on the second rewiring layer 311 .

This application provides a fan-out system-level packaging structure. Referring to FIGS. 32 and 33 , the fan-out system-in-package structure includes a plurality of chips 302 , an interconnect 205 , a first plastic encapsulation layer 304 , a rewiring layer and a plurality of electrical components 313 .

Specifically, the interconnector 205 includes a conductive structure and a plastic sealing material that encapsulates the conductive structure, and both opposite end surfaces of the interconnector 205 expose part of the conductive structure. In some embodiments, the conductive structure of the interconnect 205 may be a conductive pillar. In some embodiments, the conductive structure of the interconnect includes interconnected multi-layer circuit pattern layers.

The first plastic encapsulation layer 304 covers at least the side surfaces of the plurality of chips 302 and the side surfaces of the interconnect 205 . The interconnector 205 and the first plastic encapsulation layer 304 are formed separately.

The rewiring layer includes a first rewiring layer 307 located on the front side of the plurality of chips 302 and a second rewiring layer 311 located on the back side of the plurality of chips 302. The first rewiring layer 307 The front surfaces of the plurality of chips 302 are electrically connected to one end surface of the interconnect body 205 , and the second rewiring layer 311 is electrically connected to the other end surface of the interconnect body 205 .

The fan-out system-in-package structure also includes a first dielectric layer 308 and a second dielectric layer 312 . The first dielectric layer covers part of the first redistribution layer 307 . The second dielectric layer 312 covers part of the second redistribution layer 311 .

In some embodiments, as shown in FIG. 32 , a plurality of electrical components 313 are mounted on the second rewiring layer 311 . The second plastic encapsulation layer 314 is formed on the second dielectric layer 312 and covers the plurality of electrical components 313 . A plurality of solder balls 315 are provided on the first rewiring layer 307 .

In some embodiments, as shown in FIG. 33 , a plurality of electrical components 313 are mounted on the first rewiring layer 307 . The second plastic encapsulation layer 314 is formed on the first dielectric layer 308 and covers the plurality of electrical components 313 . A plurality of solder balls 315 are provided on the second rewiring layer 311 .

Compared with the existing technology, the fan-out system-level packaging structure and its manufacturing method proposed in this application have the following advantages: (1) Using the interconnect 205 as the interconnection channel between the lower chip 302 and the upper electrical component 313 can improve product design flexibility, reduce the difficulty of processing operations, reduce product costs, and avoid the need for plastic packaging of conductive metal blocks in the prior art. The problem of easy tilting during the process and the avoidance of the traditional deep-hole laser plating process are beneficial to improving product yield and reliability; (2) The interconnect 205 including the conductive structure and plastic packaging material can be made in advance before packaging the chip, which can improve Packaging efficiency; (3) The interconnect 205 of the required size can be cut from the board including multiple conductive structures according to the needs of the product, and part of the thickness of the interconnect 205 can be removed during the packaging process, so that the interconnect 205 can be applied In different scenarios, it has high versatility, can also realize the packaging processing of thicker chips, and is conducive to reducing the packaging size of system integration products.

It should be noted that this description is described in a progressive manner. The fan-out system-level packaging structure described later focuses on the differences from the manufacturing method of the fan-out system-level packaging structure described previously. The same and similar parts between the various parts can be referred to each other.

Reference throughout this specification to "some embodiments" or "the present embodiment" means that a particular component, structure, or feature described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrases "some embodiments" or "this embodiment" in various places throughout this specification are not necessarily referring to the same embodiment. Furthermore, the particular components, structures or features may be combined in any suitable manner in one or more embodiments.

The above description is only a description of the preferred embodiments of the present application, and does not limit the scope of rights of the present application. Any person skilled in the art can use the methods and technical contents disclosed above to improve the present application without departing from the spirit and scope of the present application. Possible changes and modifications are made to the technical solution. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application shall belong to the technical solution of the present application. protected range.

Claims

A method for manufacturing a fan-out system-level packaging structure, which is characterized by including:

Provide a third carrier board and provide a plurality of interconnectors, each of the interconnectors includes a conductive structure and a molding material that encapsulates the conductive structure, and two opposite end surfaces of each of the interconnectors expose part of the conductive structure ;

Paste and arrange a plurality of chips and the plurality of interconnects on the top surface of the third carrier board;

A first plastic sealing layer is formed on the top surface of the third carrier board, and the first plastic sealing layer covers at least the sides of the plurality of chips and the sides of the plurality of interconnects;

A rewiring layer is formed on the surface of the first plastic encapsulation layer. The rewiring layer includes a first rewiring layer located on the front side of the plurality of chips and a second rewiring layer located on the back side of the plurality of chips. , the first rewiring layer is electrically connected to the front surfaces of the plurality of chips and one end surface of the plurality of interconnections, and the second rewiring layer is electrically connected to the other end surface of the plurality of interconnections; as well as

A plurality of electrical components are mounted on the redistribution layer, and the plurality of electrical components are electrically connected to the redistribution layer.
The manufacturing method of claim 1, wherein the conductive structure includes conductive pillars; and providing a plurality of interconnectors includes:

Provide a first carrier plate, and form a plastic sealing plate on the top surface of the first carrier plate, the plastic sealing plate has an opposite front and a back, and the front of the plastic sealing plate is away from the first carrier plate;

Forming a conductive layer covering the front surface of the plastic sealing board;

A second carrier plate is provided on the side of the conductive layer away from the plastic sealing board, and the first carrier board is removed to expose the back side of the plastic sealing board;

A plurality of via holes are formed in the plastic packaging board, and the plurality of via holes penetrate the plastic packaging board and expose part of the conductive layer;

Using the conductive layer as a conductive seed layer, the plurality of conductive pillars are formed by electroplating in the plurality of via holes, and the end surfaces of the conductive pillars are flush with the back surface of the plastic packaging board; and

The second carrier board and the conductive layer are removed, and the plastic sealing board is cut to form a plurality of interconnections.
The manufacturing method of claim 1, wherein the conductive structure includes interconnected multi-layer circuit pattern layers and conductive pillars; and providing a plurality of interconnectors includes:

Provide a plastic sealing board, the plastic sealing board has an opposite front and a back, and a first circuit pattern layer is formed on the front of the plastic sealing board;

A plurality of first via holes are formed in the plastic packaging board, and the plurality of first via holes penetrate the plastic packaging board and expose part of the first circuit pattern layer;

Using the first circuit pattern layer as a conductive seed layer, a plurality of first conductive pillars are formed by electroplating from the bottom of the plurality of first via holes toward the hole openings, and the top surfaces of the plurality of first conductive pillars are The back side of the plastic sealing board is flush;

A second circuit pattern layer is formed on the back side of the plastic board, and the second circuit pattern layer is connected to the plurality of first conductive pillars;

Forming a plastic material layer covering the second circuit pattern layer, forming a plurality of second via holes in the plastic material layer, each of the plurality of second via holes exposing part of the second circuit pattern layer;

Using the second circuit pattern layer as a conductive seed layer, a plurality of second conductive pillars are formed by electroplating from the bottom of the plurality of second via holes toward the hole openings. The plurality of second conductive pillars are in contact with the plastic sealing layer. The surface of the material layer away from the plastic sealing board is flush, and a third circuit pattern layer is formed on the surface of the plastic sealing material layer away from the second circuit pattern layer. The third circuit pattern layer is in contact with the plurality of second circuit pattern layers. The conductive pillars are connected;

A cutting process is performed to form a plurality of interconnected bodies.
The manufacturing method according to claim 1, wherein the pasting and arranging the plurality of chips and the plurality of interconnects on the top surface of the third carrier board includes:

The plurality of chips are pasted face down on the top surface of the third carrier board, and one end surface of the plurality of interconnects is pasted on the top surface of the third carrier board.
The manufacturing method according to claim 4, characterized in that: forming a further layer on the surface of the first plastic sealing layer Routing layers, including:

Remove the third carrier board to expose the micro-bumps on the front surfaces of the multiple chips and expose the end faces of the interconnects;

The first rewiring layer is formed on the front side of the plurality of chips; and

The second rewiring layer is formed on the back side of the plurality of chips.
The manufacturing method of claim 5, wherein the original thickness of the interconnect is greater than the thickness of the chip; in the step of forming the first plastic sealing layer on the top surface of the third carrier board, the The first plastic encapsulation layer covers the back surfaces of the plurality of chips and the end surfaces of the plurality of interconnects away from the third carrier board;

Forming a rewiring layer on the surface of the first plastic encapsulation layer includes: after forming the first rewiring layer on the front side of the plurality of chips, removing a part of the thickness of the first plastic encapsulation layer, Expose the end surfaces of the plurality of interconnects away from the first rewiring layer; continue to remove part of the thickness of the first plastic layer and simultaneously remove part of the thickness of the plurality of interconnects; The second rewiring layer is formed on the side.
The manufacturing method according to claim 1, wherein mounting a plurality of electrical components on the rewiring layer includes: in the first rewiring layer and the second rewiring layer. The multiple electrical components are mounted on one.
The manufacturing method according to claim 7, wherein the manufacturing method includes: after mounting the plurality of electrical components on the rewiring layer, between the first rewiring layer and the third rewiring layer Solder balls are placed on the other of the two rewiring layers.
The manufacturing method according to claim 1, characterized in that the manufacturing method includes: after mounting a plurality of electrical components on the rewiring layer, forming a second plastic sealing layer, the second plastic sealing layer The side surfaces covering the plurality of electrical components and the surfaces of the plurality of electrical components away from the first plastic encapsulation layer.
The manufacturing method according to any one of claims 1 to 8, wherein the plurality of electrical components include two or more electrical components.
A fan-out system-level packaging structure is characterized by including:

A plurality of chips and interconnects, the interconnects include a conductive structure and a plastic sealing material that encapsulates the conductive structures, and both opposite end surfaces of the interconnects expose part of the conductive structures;

A first plastic encapsulation layer covers at least the side surfaces of the plurality of chips and the side surfaces of the interconnector; the interconnector and the first plastic encapsulation layer are formed separately;

A rewiring layer formed on the surface of the first plastic encapsulation layer. The rewiring layer includes a first rewiring layer located on the front side of the plurality of chips and a second rewiring layer located on the back side of the plurality of chips. layer, the first rewiring layer is electrically connected to the front surfaces of the plurality of chips and one end surface of the interconnect body, and the second rewiring layer is electrically connected to the other end surface of the interconnect body; and

A plurality of electrical components are mounted on the rewiring layer.
The packaging structure of claim 11, wherein the conductive structure includes conductive pillars, the plastic packaging material includes a plastic packaging plate, and a plurality of via holes penetrating the plastic packaging plate are formed in the plastic packaging plate. Each of the conductive pillars is formed in the plurality of via holes through electroplating, and the end surfaces of the plurality of conductive pillars are flush with the surface of the plastic packaging board.
The packaging structure of claim 11, wherein the conductive structure includes interconnected multi-layer circuit pattern layers and conductive pillars, and the plastic packaging material includes a plastic packaging plate and a plastic packaging material layer;

The plastic sealing board has an opposite front and a back, and the first circuit pattern layer is formed on the front of the plastic sealing board;

A plurality of first via holes are formed in the plastic packaging board, and the plurality of first via holes penetrate the plastic packaging board and expose part of the first circuit pattern layer;

A plurality of first conductive pillars are formed by electroplating in the plurality of first via holes, and the top surfaces of the plurality of first conductive pillars are flush with the back surface of the plastic packaging board;

A second circuit pattern layer is formed on the back of the plastic board, and the second circuit pattern layer is connected to the plurality of first conductive pillars;

The plastic sealing material layer covers the second circuit pattern layer, and a plurality of second conductive holes are formed in the plastic sealing material layer, and the plurality of second conductive holes each expose part of the second circuit pattern. layer;

A plurality of second conductive pillars are formed by electroplating in the plurality of second via holes. The plurality of second conductive pillars are flush with the surface of the plastic sealing material layer away from the plastic sealing board, and are in the plastic sealing material layer. A third circuit pattern layer is formed on a surface of the layer away from the second circuit pattern layer, and the third circuit pattern layer is connected to the plurality of second conductive pillars.