CN104600059A - TSV (Through Silicon Via) hole structure with IPD and machining method thereof - Google Patents
TSV (Through Silicon Via) hole structure with IPD and machining method thereof Download PDFInfo
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- CN104600059A CN104600059A CN201510055003.XA CN201510055003A CN104600059A CN 104600059 A CN104600059 A CN 104600059A CN 201510055003 A CN201510055003 A CN 201510055003A CN 104600059 A CN104600059 A CN 104600059A
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Abstract
The invention provides a TSV (Through Silicon Via) hole structure with IPD. According to the TSV hole structure with the IPD, a traditional TSV technological process is adopted, the structure of the TSV hole is simple due to the structural design, a TSV adapter plate structure of a resistor, a capacitor and an inductor is achieved at the same time when the TSV hole is simply formed, the adapter plate performances are improved. The TSV hole structure with the IPD comprises a silicon wafer and is characterized in that a plurality of TSV through holes are formed in the silicon wafer; insulating layers are deposited inside the TSV through holes and on the surface of the silicon water; a transverse insulating layer is formed inside at least one TSV through hole to form into a partition separating the upper through hole and the lower through hole; metal layers are electroplated inside the TSV through holes; the upper ends and the lower ends of the metal layers in the TSV through holes are mutually connected in a stagger mode; an annular electroplating metal layer is formed in the surface of the silicon wafer surface; the annular electroplating metal layer and the electroplating metal layers inside the TSV through holes are mutually connected. The invention also provides a machining method for the TSV hole structure with the IPD.
Description
Technical field
The present invention relates to the technical field of the method for micro-electronic manufacturing or process semiconductor or solid state device, be specifically related to a kind of TSV pore structure with IPD and processing method thereof.
Background technology
Along with the continuous progress of microelectric technique, the characteristic size of integrated circuit constantly reduces, and interconnection density improves constantly.The requirement of user to high-performance low power consumption simultaneously improves constantly.In this case, by reducing the live width of interconnection line further to propose the restriction that high performance mode is subject to physical characteristics of materials and apparatus and process, the resistance capacitance (RC) of two-dimentional interconnection line postpones the bottleneck becoming the raising of restriction semiconductor core piece performance gradually.Silicon perforation (Through Silicon Via, being called for short TSV) technique forms metal upright post by being combined in wafer, and be equipped with metal salient point, can to realize between wafer (chip) or direct three-dimensional interconnection between chip and substrate, the limitation of conventional semiconductor chip two dimension wiring can be made up like this.This interconnection mode and traditional Stack Technology as have compared with bonding techniques the stacking density of three-dimensional large, encapsulate the advantages such as overall dimension is afterwards little, thus greatly improve the speed of chip and reduce power consumption.Current extensive use be 2.5D encapsulation based on TSV keyset, dissimilar chip, is linked to the substrate of below, greatly can improve interconnection density like this by TSV keyset, improve Mechanical Reliability and heat-sinking capability.TSV keyset is passive transition plate, mainly provide interconnecting channel, but in the integrated chip of some high frequencies, high speed, interconnect delay and parasitics serious, therefore by adding decoupling capacitor, inductance element, improve interconnection performance, existing decoupling capacitor, inductance element are added by the mode of interconnection usually, and this addition manner integrated circuit structure and its processing technology are all comparatively complicated.
Summary of the invention
For the problems referred to above, the invention provides a kind of TSV pore structure with IPD, adopt traditional TSV technological process, pass through structural design, make the structure in TSV hole simple, while guarantee TSV hole is simply shaping, achieves the TSV adapter plate structure of resistance, electric capacity, inductance, improves keyset performance, invention also provides a kind of processing method of the TSV pore structure with IPD.
Its technical scheme of the present invention is such: a kind of TSV pore structure with IPD, it comprises silicon wafer circle, it is characterized in that: described silicon wafer circle is provided with multiple TSV through hole, insulating barrier is deposited together with Silicon Wafer surface in described TSV through hole, lateral insulator is provided with at least one TSV through hole in described TSV through hole, form TSV through hole to cut off up and down, electroplated metal layer in described TSV through hole, the staggered interconnection of described metal level upper and lower side in described TSV through hole, the shaping ring-type electroplated metal layer in described Silicon Wafer surface, in described ring-type electroplated metal layer and described TSV through hole, electroplated metal layer interconnects.
It is further characterized in that: in the described TSV through hole of connection, electroplated metal layer is ring-type inductance shape metal level.
With a processing method for the TSV pore structure of IPD, it comprises the following steps:
(1), on silicon wafer circle, a multiple TSV deep hole is etched;
(2), depositing first insulator layer in a TSV deep hole and on silicon wafer circle;
(3), on the first insulating barrier deposited seed layer, on the seed layer electroplated metal layer, and the electroplated metal layer of forming section the one TSV deep hole interconnection;
(4), at the silicon wafer circle back side, a corresponding described TSV deep hole etches the second deep hole,
(5), in the 2nd TSV deep hole and on silicon wafer circle, the second insulating barrier is deposited;
(6), described first insulating barrier of the transverse direction of etched portions the 2nd TSV deep hole and described second insulating barrier, form a TSV deep hole and be communicated with the 2nd TSV deep hole;
(7), over the second dielectric deposited seed layer, in Seed Layer and the 2nd TSV deep hole electroplated metal layer, and the electroplated metal layer of forming section the 2nd TSV deep hole interconnection.
It improves further and is:
Shaping ring-type inductance shape metal level in the TSV through hole that a TSV deep hole is communicated with the 2nd TSV deep hole; At the shaping ring-type electroplated metal layer in described Silicon Wafer surface, form resistor-type metal level.
In said structure of the present invention, due to TSV hole shaping on silicon wafer circle, the electroplated metal layer of profiled insulation in TSV hole, form capacitance structure, shaping electroplated metal layer in TSV hole, form induction structure, the electroplated metal layer of shaping ring-type on silicon wafer circle, form electric resistance structure, the TSV adapter plate structure of resistance, electric capacity, inductance is achieved while guarantee TSV hole is simply shaping, avoid the assembling of follow-up passive component, decrease space and cost that element takies, improve the interconnection performance that encapsulation is overall.
Accompanying drawing explanation
Fig. 1 is TSV pore structure generalized section of the present invention;
Fig. 2 is etching the one TSV deep hole schematic diagram;
Fig. 3 is shaping first insulating barrier schematic diagram in a TSV deep hole;
Fig. 4 is deposited seed layer and electroplated metal layer schematic diagram on the first insulating barrier;
Fig. 5 is at etching the 2nd TSV deep hole schematic diagram;
Fig. 6 is shaping second insulating barrier schematic diagram in the 2nd TSV deep hole;
Fig. 7 is partial etching second insulating barrier schematic diagram;
Fig. 8 is deposited seed layer and electroplated metal layer schematic diagram over the second dielectric.
Embodiment
The invention will be further described with reference to the accompanying drawings:
See Fig. 1,
A kind of TSV structure with IPD, it comprises silicon wafer circle 1, silicon wafer circle 1 is provided with multiple TSV through hole 4, insulating barrier 2 is had together with silicon wafer circle 1 surface deposition in TSV through hole 4, lateral insulator 2a is provided with at least one TSV through hole 4a in TSV through hole 4, form TSV through hole 4a to cut off up and down, electroplated metal layer 3 in TSV through hole 4, in the TSV through hole 4 be communicated with, electroplated metal layer 3 is ring-type inductance shape metal level, the staggered interconnection of metal level 3 upper and lower side in TSV through hole 4, silicon wafer circle 1 surface forming ring-type electroplated metal layer 5, ring-type electroplated metal layer 5 interconnects with electroplated metal layer 3 in TSV through hole, due to TSV hole shaping on silicon wafer circle, the electroplated metal layer of profiled insulation in TSV hole, form capacitance structure, shaping electroplated metal layer in TSV hole, form induction structure, the electroplated metal layer of shaping ring-type on silicon wafer circle, form electric resistance structure, resistance is achieved while guarantee TSV hole is simply shaping, electric capacity, the TSV adapter plate structure of inductance, avoid the assembling of follow-up passive component, decrease space and cost that element takies, improve the interconnection performance that encapsulation is overall.
With a processing method for the TSV pore structure of IPD, it comprises the following steps:
See Fig. 2, (1), employing dry method or wet method etch a multiple TSV deep hole 4 on silicon wafer circle 1;
See Fig. 3, (2), in a TSV deep hole 4 and on silicon wafer circle 1, adopt the modes such as thermal oxidation, CVD deposition, spin coating, spraying to form the first insulating barrier 2;
See Fig. 4, (3), PVD deposition of adhesion and Seed Layer (not shown in FIG.), on the seed layer electroplated metal layer 3 on the first insulating barrier 2, by photoetching and metal dry method or wet-etching technology, at silicon wafer circle 1 surface forming ring-type electroplated metal layer 5, form resistor-type metal level, and the interconnection of the electroplated metal layer of forming section the one TSV deep hole 4;
See Fig. 5, (4), corresponding TSV deep hole 4 position at silicon wafer circle 1 back side, form the 2nd TSV deep hole 4-1 by double-sided overlay and wet method or dry etching,
See Fig. 6, (5), CVD deposition, spin coating or spraying formation second insulating barrier 2-1 in the 2nd TSV deep hole 4-1 and on silicon wafer circle 1;
See Fig. 7, (6), employing photoetching and dry method or wet processing, the first insulating barrier 2 and the second insulating barrier 2-1 of the transverse direction of etched portions the 2nd TSV deep hole 4, form a TSV deep hole 4 and be communicated with the 2nd TSV deep hole 4-1;
See Fig. 8, (7), over the second dielectric deposited seed layer, electroplated metal layer 3 in Seed Layer and the 2nd TSV deep hole 4-1, and the interconnection of the electroplated metal layer of forming section the 2nd TSV deep hole, in the through hole that one TSV deep hole 4 and the 2nd TSV deep hole 4-1 are disconnected by the first insulating barrier 2 and the second insulating barrier 2-1, electroplated metal layer 3 forms capacitance structure, shaping ring-type inductance shape metal level 3 in the through hole that a TSV deep hole 4 is communicated with the 2nd TSV deep hole 4-1.
The present invention with in the TSV pore structure of IPD and the said structure of processing method and process thereof,
(1), formed by TSV hole and surface wiring three-dimensional around induction structure;
(2), by forming insulating barrier in the middle of TSV hole, two ends form metal, form capacitance structure;
(3), electric resistance structure is formed on surface;
(4), simultaneously with the TSV pore structure of normal function.
TSV hole keyset, by elements such as integrated resistor, electric capacity, inductance, promotes the electrical property of interconnection further, thus realizes intelligent keyset.
Claims (8)
1. the TSV pore structure with IPD, it comprises silicon wafer circle, it is characterized in that: described silicon wafer circle is provided with multiple TSV through hole, insulating barrier is deposited together with Silicon Wafer surface in described TSV through hole, lateral insulator is provided with at least one TSV through hole in described TSV through hole, form TSV through hole to cut off up and down, electroplated metal layer in described TSV through hole, the staggered interconnection of described metal level upper and lower side in described TSV through hole, the shaping ring-type electroplated metal layer in described Silicon Wafer surface, in described ring-type electroplated metal layer and described TSV through hole, electroplated metal layer interconnects.
2. a kind of TSV pore structure with IPD according to claim 1: in the described TSV through hole of connection, electroplated metal layer is ring-type inductance shape metal level.
3., with a processing method for the TSV pore structure of IPD, it is characterized in that: it comprises the following steps:
(1), on silicon wafer circle, a multiple TSV deep hole is etched;
(2), depositing first insulator layer in a TSV deep hole and on silicon wafer circle;
(3), on the first insulating barrier deposited seed layer, on the seed layer electroplated metal layer, and the electroplated metal layer of forming section the one TSV deep hole interconnection;
(4), at the silicon wafer circle back side, a corresponding described TSV deep hole etches the 2nd TSV deep hole,
(5), in the 2nd TSV deep hole and on silicon wafer circle, the second insulating barrier is deposited;
(6), described first insulating barrier of the transverse direction of etched portions the 2nd TSV deep hole and described second insulating barrier, form a TSV deep hole and be communicated with the 2nd TSV deep hole;
(7), over the second dielectric deposited seed layer, in Seed Layer and the 2nd TSV deep hole electroplated metal layer, and the electroplated metal layer of forming section the 2nd TSV deep hole interconnection.
4. the processing method of a kind of TSV pore structure with IPD according to claim 3, is characterized in that: shaping ring-type inductance shape metal level in the TSV through hole that a TSV deep hole is communicated with the 2nd TSV deep hole.
5. the processing method of a kind of TSV pore structure with IPD according to claim 3 or 4, is characterized in that: at the shaping ring-type electroplated metal layer in described Silicon Wafer surface, forms resistor-type metal level.
6. the processing method of a kind of TSV pore structure with IPD according to claim 3, is characterized in that: adopt thermal oxidation, CVD deposition, spin coating, spraying method to form the first insulating barrier.
7. the processing method of a kind of TSV pore structure with IPD according to claim 3, is characterized in that: by photoetching and metal dry method or wet-etching technology, the shaping ring-type electroplated metal layer in Silicon Wafer surface.
8. the processing method of a kind of TSV pore structure with IPD according to claim 3, is characterized in that: form the 2nd TSV deep hole by double-sided overlay and wet method or dry etching.
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| CN105390480A (en) * | 2015-10-23 | 2016-03-09 | 西安理工大学 | Three-dimensional high-value integrated capacitor based on through-silicon-via array, and manufacturing method thereof |
| CN105470237A (en) * | 2015-12-09 | 2016-04-06 | 西安交通大学 | Three-dimensional capacitively coupled integrated interconnection structure based on through-silicon capacitor |
| CN105529299A (en) * | 2015-09-14 | 2016-04-27 | 上海交通大学 | Method for electroplating filling of TSV adapter plate |
| CN105679701A (en) * | 2016-01-18 | 2016-06-15 | 上海交通大学 | Method for efficiently electroplating and filling silicon-based TSV |
| CN105679734A (en) * | 2016-03-07 | 2016-06-15 | 中国科学院上海微系统与信息技术研究所 | Integrated passive component adapter plate and preparation method thereof |
| CN106057757A (en) * | 2016-07-08 | 2016-10-26 | 桂林电子科技大学 | Silicon through hole structure and manufacturing method thereeof |
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| CN109686707A (en) * | 2019-01-28 | 2019-04-26 | 南通大学 | Height heat dissipation silicon-based packaging substrate, production method and high heat-dissipation packaging structure |
| CN110581124B (en) * | 2019-09-12 | 2021-03-19 | 西安电子科技大学 | Preparation method of multi-level fused three-dimensional system integrated structure |
| CN110581124A (en) * | 2019-09-12 | 2019-12-17 | 西安电子科技大学 | preparation method of multi-level fused three-dimensional system integrated structure |
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| CN111403332A (en) * | 2020-02-28 | 2020-07-10 | 浙江集迈科微电子有限公司 | Manufacturing method of super-thick adapter plate |
| CN111403332B (en) * | 2020-02-28 | 2023-04-28 | 浙江集迈科微电子有限公司 | Manufacturing method of ultra-thick adapter plate |
| CN111554646A (en) * | 2020-05-19 | 2020-08-18 | 上海先方半导体有限公司 | Wafer-level chip structure, multi-chip stacking interconnection structure and preparation method |
| CN113066758A (en) * | 2021-03-23 | 2021-07-02 | 成都迈科科技有限公司 | TGV deep hole filling method |
| CN113066758B (en) * | 2021-03-23 | 2023-08-22 | 三叠纪(广东)科技有限公司 | TGV deep hole filling method |
| CN113161289A (en) * | 2021-04-22 | 2021-07-23 | 浙江集迈科微电子有限公司 | Electroplating process of TSV (through silicon via) metal column with high depth-to-width ratio |
| CN116960058A (en) * | 2023-09-20 | 2023-10-27 | 湖北江城芯片中试服务有限公司 | Preparation method of adapter plate and adapter plate |
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