CN111524820B - Wafer double-sided lead-tin alloy bump forming process - Google Patents
Wafer double-sided lead-tin alloy bump forming process Download PDFInfo
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- CN111524820B CN111524820B CN202010357057.2A CN202010357057A CN111524820B CN 111524820 B CN111524820 B CN 111524820B CN 202010357057 A CN202010357057 A CN 202010357057A CN 111524820 B CN111524820 B CN 111524820B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68372—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support a device or wafer when forming electrical connections thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
- H01L2224/1146—Plating
- H01L2224/11462—Electroplating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
Abstract
The invention discloses a process for forming a lead-tin alloy bump on the double surface of a wafer, which comprises the following steps: s1: a through silicon via process, in which a counter bore is formed by etching on the front surface of the wafer, S2: filling metal, namely filling metal in the counter bore, and S3: a front side photolithography process of performing a photolithography process on the front side of the wafer to form a front side redistribution layer on the front side of the wafer, S4: bonding, bonding the front side of the wafer on the glass carrier plate through an adhesive, and S5: thinning, namely thinning the back surface of the wafer to expose the counter bore to form a through hole, and S6: backside yellow light process, S7: windowing a glass carrier plate, S8, carrying out UBM on two sides, S9, carrying out a double-sided yellow light process, S10, carrying out double-sided electroplating, S11, removing photoresist, S12, removing UBM, S13: and (5) bonding removal. The double-sided lead-tin alloy bump forming process of the wafer carries out the simultaneous double-sided bump process through the window type glass carrier plate, does not need the coating and removing procedures of bumps, improves the quality and the productivity, reduces the generation of defective products and reduces the cost.
Description
Technical Field
The invention relates to the field of wafer production, in particular to a wafer double-sided lead-tin alloy bump forming process.
Background
Integrated circuit technology has evolved over the past few decades following moore's law, i.e., the number of transistors that can be accommodated per unit of integrated circuit area can be doubled approximately every 18 months. However, as the size of the transistor is reduced to the nanometer level, it is very difficult to improve the performance of the integrated circuit by reducing the size of the transistor, and as the quality of human life is improved and the diversity of the integrated circuit is developed, the final product is required to be developed according to the specification of being light, thin, small and fast, and in recent years, in the packaging technology, the traditional mode of connecting the lead wire to the die and then connecting the die to the printed circuit board has been developed to 2.5D and three-dimensional (3D) packaging technology. The maturation of the "Through-Silicon Vias" technology allows for the up and down alignment of the multi-layer stack, the bump technology addresses the interconnect requirements in the upper and lower layer stack. Compared with the traditional lead bonding interconnection package, the through silicon via technology and the bump technology are connected, so that the packaging structure has the advantages of good conductivity, low power consumption and small package volume.
In the production process, a Silicon channel (Through-Silicon Vias) technology is generally adopted, copper is adopted as a material of Through holes and redistribution lines, after the electroplating process of bumps on the front surface of the wafer is completed, a bump coating process is carried out, then a glass carrier plate is used for bonding, so that the wafer (20-200um) can be thinned after bonding, after the redistribution line process on the other surface is sequentially completed, the electroplating process of bumps on the other surface of the wafer is carried out, bonding is released, coating of the bumps is removed, and the subsequent processes are carried out.
In order to thin each layer of wafer thickness, so as to achieve the advantages of minimized thickness of final multilayer stack, good conductivity and low power consumption, a glass carrier plate is bonded, a wafer thinning process is performed, a front-stage process and a bump electroplating process are performed before the glass carrier plate is bonded, a front-side bump coating process is performed, and a back-side bump electroplating process is performed after thinning. And (4) bonding, removing the coating of the bump, and performing subsequent processes.
Disclosure of Invention
The invention aims to provide a process for forming lead-tin alloy bumps on both sides of a wafer, which implements a simultaneous double-sided bump process through a window-opening type glass carrier plate without the processes of coating and removing bumps, improves the quality and the productivity, reduces the generation of defective products and reduces the cost.
The purpose of the invention can be realized by the following technical scheme:
the forming process of the lead-tin alloy lug on the double surfaces of the wafer comprises the following steps:
s1: through silicon Via Process
And etching the front side of the wafer to form a counter bore.
S2: metal filling
And filling metal in the counter bore.
S3: front yellow light technology
And performing a yellow light process on the front surface of the wafer, and forming a front surface rewiring layer on the front surface of the wafer.
S4: bonding of
And bonding the front side of the wafer on the glass carrier plate through an adhesive.
S5: thinning
And thinning the back surface of the wafer to expose the counter bore to form a through hole.
S6: back side yellow light technology
And performing a yellow light process on the thinned surface of the wafer to form a back-surface rewiring layer.
S7: window with glass carrier plate
And etching a window on the glass carrier to form a window.
S8 formation of Under Bump Metallurgy (UBM) on both sides
And generating under bump metal layers on two sides of the wafer, forming a first bump metallization layer on the back redistribution layer, and forming a second bump metallization layer on the front redistribution layer in the window.
S9 double-sided yellow light process
And respectively carrying out a yellow light process on the front surface and the back surface of the wafer, forming a first light resistance layer on the first salient point metallization layer, and forming a second light resistance layer on the second salient point metallization layer.
S10 double-sided plating
And a first electroplated layer and a second electroplated layer are distributed on two sides of the wafer.
S11 removing the photoresist
Removing the first photoresist layer and the second photoresist layer on both sides of the wafer.
S12 UBM removal
And removing the first bump metallization layer and the second bump metallization layer on the two sides of the wafer.
S13: debonding
And debonding the wafer from the glass carrier plate.
Further, the metal is a copper/copper alloy.
Further, the wafer and the glass carrier plate are bonded together by the adhesive through UV bonding, the temperature is required to be 50-200 ℃, and the using time is below 30 minutes.
Further, the adhesive bonds the wafer and the glass carrier plate together by heating and bonding, the temperature is required to be 150 ℃ and 300 ℃, and the using time is less than 30 minutes.
Further, the position of the window in the window of the S7 glass carrier plate is opposite to the position of the die.
Furthermore, in the S10 double-sided electroplating, lead-tin alloy is used to plate both sides of the wafer.
Further, in the S10 double-sided electroplating, silver-tin alloy is used to plate both sides of the wafer.
Further, in the step of S13 debonding, a laser method is used for debonding.
Furthermore, in the S13 debonding, debonding is performed by means of thermal decomposition.
The invention has the beneficial effects that:
the double-sided lead-tin alloy bump forming process of the wafer carries out the simultaneous double-sided bump process through the window type glass carrier plate, does not need the coating and removing procedures of bumps, improves the quality and the productivity, reduces the generation of defective products and reduces the cost.
Drawings
The invention will be further described with reference to the accompanying drawings.
FIG. 1 is a schematic diagram of a through-silicon-via process of the present invention;
FIG. 2 is a schematic view of a metal fill structure of the present invention;
FIG. 3 is a schematic view of the front side photolithography process of the present invention;
FIG. 4 is a schematic view of a bonding configuration of the present invention;
FIG. 5 is a schematic view of a thinning structure of the present invention;
FIG. 6 is a schematic view of a backside photolithography process of the present invention;
FIG. 7 is a schematic view of a glazing structure of a glass carrier according to the present invention;
FIG. 8 is a schematic diagram of a two-sided UBM structure of the present invention;
FIG. 9 is a schematic diagram of a double-sided photolithography process according to the present invention;
FIG. 10 is a schematic view of a double-sided electroplating configuration of the present invention;
FIG. 11 is an enlarged partial view of the double-side plating according to the present invention;
FIG. 12 is a schematic view of a photoresist stripping structure according to the present invention;
FIG. 13 is a schematic view of a UBM removing structure according to the present invention;
FIG. 14 is a schematic illustration of an debonding structure of the present invention;
FIG. 15 is an enlarged view of a portion of the wafer structure of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The forming process of the lead-tin alloy lug on the double surfaces of the wafer comprises the following steps:
s1: through silicon Via Process
A counterbore 2 is etched into the front side of the wafer 1 as shown in figure 1.
S2: metal filling
The counterbore 2 is filled with metal 3, and the metal 3 is copper/copper alloy, as shown in fig. 2.
S3: front yellow light technology
A yellow light process is performed on the front surface of the wafer 1, and a front surface redistribution layer 4 is formed on the front surface of the wafer 1, as shown in fig. 3.
S4: bonding of
The front surface of the wafer 1 is bonded on the glass carrier plate 6 through the adhesive 5, the wafer 1 and the glass carrier plate 6 are bonded together through the adhesive 5 by UV bonding, the temperature is required to be 50-200 ℃, and the use time is below 30 minutes, or the wafer 1 and the glass carrier plate 6 are bonded together through the adhesive 5 by heating bonding, the temperature is required to be 150-300 ℃, and the use time is below 30 minutes.
As shown in fig. 4.
S5: thinning
The back side of the wafer 1 is thinned to expose the counter bore 2 to form a through hole, as shown in fig. 5.
S6: back side yellow light technology
A yellow light process is performed on the thinned surface of the wafer 1 to form a backside redistribution layer 7, as shown in fig. 6.
S7: window with glass carrier plate
A window 8 is formed on the glass carrier 6 by etching, and the position of the window is opposite to the position of the crystal grain, as shown in fig. 7.
S8 two-sided UBM
UBM is performed on both sides of the wafer 1, a first bump metallization layer 10 is formed on the back-side redistribution layer 7, and a second bump metallization layer 9 is formed on the front-side redistribution layer 4 within the window 8, as shown in fig. 8.
S9 double-sided yellow light process
The front side and the back side of the wafer 1 are respectively subjected to a yellow light process, a first photoresist layer 12 is formed on the first bump metallization layer 10, and a second photoresist layer 11 is formed on the second bump metallization layer 9, as shown in fig. 9.
S10 double-sided plating
Electroplating both sides of the wafer 1 with a lead-tin alloy/silver-tin alloy, and forming a first electroplated layer 13 and a second electroplated layer 14 on both sides of the wafer 1, as shown in fig. 10,
s11 removing the photoresist
The first photoresist layer 12 and the second photoresist layer 11 on both sides of the wafer 1 are removed as shown in fig. 11.
S12 UBM removal
The first bump metallization layer 10 and the second bump metallization layer 9 on both sides of the wafer 1 are removed as shown in fig. 12.
S13: debonding
The wafer 1 is debonded from the glass carrier 6 by laser/thermal decomposition, as shown in fig. 13.
In the description herein, references to the description of "one embodiment," "an example," "a specific example" or the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The foregoing shows and describes the general principles, essential features, and advantages of the invention. It will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, which are described in the specification and illustrated only to illustrate the principle of the present invention, but that various changes and modifications may be made therein without departing from the spirit and scope of the present invention, which fall within the scope of the invention as claimed.
Claims (8)
1. The forming process of the lead-tin alloy lug on the double surfaces of the wafer is characterized by comprising the following steps of:
s1: through silicon Via Process
Etching the front surface of the wafer (1) to form a counter bore (2);
s2: metal filling
Filling metal (3) in the counter bore (2);
s3: front yellow light technology
Performing a yellow light process on the front surface of the wafer (1), and forming a front surface rewiring layer (4) on the front surface of the wafer (1);
s4: bonding of
Bonding the front surface of the wafer (1) on a glass carrier plate (6) through an adhesive (5);
s5: thinning
Thinning the back surface of the wafer (1) to expose the counter bore (2) to form a through hole;
s6: back side yellow light technology
Performing a yellow light process on the thinned surface of the wafer (1) to form a back surface rewiring layer (7);
s7: window with glass carrier plate
Etching a window on the glass carrier plate (6) to form a window (8);
s8 two-sided UBM
UBM is carried out on two sides of a wafer (1), a first bump metallization layer (10) is formed on a back-side rewiring layer (7), and a second bump metallization layer (9) is formed on a front-side rewiring layer (4) in a window (8);
s9 double-sided yellow light process
Respectively carrying out a yellow light process on the front side and the back side of the wafer (1), forming a first light resistance layer (12) on the first salient point metallization layer (10), and forming a second light resistance layer (11) on the second salient point metallization layer (9);
s10 double-sided plating
A first electroplated layer (13) and a second electroplated layer (14) are distributed and formed on two surfaces of the wafer (1);
s11 removing the photoresist
Removing the first photoresist layer (12) and the second photoresist layer (11) on both sides of the wafer (1);
s12 UBM removal
Removing the first bump metallization layer (10) and the second bump metallization layer (9) which are not shielded by the electroplated layer on the two sides of the wafer (1);
s13: debonding
The wafer (1) is debonded from the glass carrier (6).
2. The wafer double-sided lead-tin alloy bump forming process according to claim 1, wherein the metal (3) is a copper/copper alloy.
3. The wafer double-sided lead-tin alloy bump forming process according to claim 1, wherein the adhesive (5) bonds the wafer (1) and the glass carrier plate (6) together by UV bonding, the temperature is required to be 50-200 ℃, and the use time is 30 minutes or less.
4. The wafer double-sided lead-tin alloy bump forming process as claimed in claim 1, wherein the adhesive (5) bonds the wafer (1) and the glass carrier (6) together by thermal bonding at a temperature of 150 ℃ and 300 ℃ for a time of 30 minutes or less.
5. The wafer double-sided lead-tin alloy bump forming process as claimed in claim 1, wherein the window opening position of the S7 glass carrier is opposite to the die position.
6. The wafer double-sided lead-tin alloy bump forming process as claimed in claim 1, wherein in the step of S10 double-sided electroplating, lead-tin alloy is adopted to electroplate the double sides of the wafer (1).
7. The wafer double-sided lead-tin alloy bump forming process as claimed in claim 1, wherein the S13 debonding is performed by laser debonding.
8. The wafer double-sided lead-tin alloy bump forming process as claimed in claim 1, wherein the S13 debonding is performed by thermal decomposition.
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| JP3067021B2 (en) * | 1998-09-18 | 2000-07-17 | インターナショナル・ビジネス・マシーンズ・コーポレ−ション | Method for manufacturing double-sided wiring board |
| US8202786B2 (en) * | 2010-07-15 | 2012-06-19 | Infineon Technologies Austria Ag | Method for manufacturing semiconductor devices having a glass substrate |
| US9117801B2 (en) * | 2013-05-15 | 2015-08-25 | Infineon Technologies Ag | Semiconductor devices having a glass substrate, and method for manufacturing thereof |
| CN105047630B (en) * | 2015-07-08 | 2018-05-22 | 华进半导体封装先导技术研发中心有限公司 | Active embedment encapsulating structure and its production technology are assembled after chip |
| DE102016116499B4 (en) * | 2016-09-02 | 2022-06-15 | Infineon Technologies Ag | Process for forming semiconductor devices and semiconductor devices |
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