CN112687618A - Wafer packaging method and wafer packaging assembly - Google Patents
Wafer packaging method and wafer packaging assembly Download PDFInfo
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- CN112687618A CN112687618A CN202011555786.5A CN202011555786A CN112687618A CN 112687618 A CN112687618 A CN 112687618A CN 202011555786 A CN202011555786 A CN 202011555786A CN 112687618 A CN112687618 A CN 112687618A
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- wafer
- front surface
- carrier plate
- packaging
- silicon via
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- 238000000034 method Methods 0.000 title claims abstract description 44
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 29
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 29
- 239000010703 silicon Substances 0.000 claims abstract description 29
- 239000002184 metal Substances 0.000 claims abstract description 22
- 229910052751 metal Inorganic materials 0.000 claims abstract description 22
- 239000010949 copper Substances 0.000 claims abstract description 20
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 17
- 229910052802 copper Inorganic materials 0.000 claims abstract description 17
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 16
- 238000009713 electroplating Methods 0.000 claims abstract description 13
- 238000004891 communication Methods 0.000 claims abstract description 12
- 239000000945 filler Substances 0.000 claims abstract description 12
- 238000000576 coating method Methods 0.000 claims abstract description 10
- 239000011248 coating agent Substances 0.000 claims abstract description 9
- 239000007888 film coating Substances 0.000 claims abstract description 7
- 238000009501 film coating Methods 0.000 claims abstract description 7
- 238000004519 manufacturing process Methods 0.000 claims abstract description 6
- 239000000853 adhesive Substances 0.000 claims description 9
- 230000001070 adhesive effect Effects 0.000 claims description 9
- 239000011521 glass Substances 0.000 claims description 9
- 238000007747 plating Methods 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 4
- 238000001020 plasma etching Methods 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- 238000000206 photolithography Methods 0.000 claims description 2
- 235000012431 wafers Nutrition 0.000 abstract description 76
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 16
- 238000010586 diagram Methods 0.000 description 10
- 239000010410 layer Substances 0.000 description 10
- 229910000679 solder Inorganic materials 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000012536 packaging technology Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 239000012790 adhesive layer Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Images
Abstract
The invention discloses a packaging method of a wafer and a wafer packaging assembly, wherein the packaging method of the wafer comprises the following steps: performing a through silicon via process on the front surface of the wafer to form a through silicon via, and filling a first metal filler in the through silicon via; performing yellow light and film coating processes on the front surface of the wafer, and forming a first rewiring layer and a first metal contact point on the front surface of the wafer; bonding the front surface of the wafer on the carrier plate; carrying out a thinning process on the back of the wafer; performing yellow light and film coating processes on the back surface of the wafer; manufacturing a TGV communication hole on the back of the carrier plate; coating photoresist on the surface of the carrier plate, and filling a second metal filler in the TGV communication hole by adopting electrode electroplating; removing the photoresist, coating the photoresist layer on the back of the wafer and the back of the carrier again, and reserving the position of the copper pillar bump; double-sided electroplating; and removing the double-sided photoresist. The packaging method realizes double-sided electroplating, simplifies the process procedure, improves the packaging efficiency, reduces the packaging cost and realizes the production of ultrathin wafers.
Description
Technical Field
The invention relates to the field of semiconductors, in particular to a wafer packaging method and a wafer packaging assembly.
Background
In the related art, in order to meet the requirements of light weight, thinness, compactness and rapid development of electronic products, the packaging technology has been developed from the traditional mode of connecting a lead wire to a die and then connecting a printed circuit board to a 2.5D and three-dimensional 3D packaging technology. In 2.5D and three-dimensional 3D packaging technologies, a Silicon channel Through-Silicon Vias technology is generally adopted to perform redistribution and bump electroplating processes, after the bump electroplating process on the front surface of the wafer is completed, a bump coating process is performed first, then a glass carrier plate is bonded, wafer thinning (thinning to 20-200um) is performed, a redistribution process on the other surface is performed, then an electroplating process on bumps on the other surface of the wafer is performed, debonding is performed, coating of the bumps is removed, and then subsequent processes are performed, so that the steps are complicated and the cost is high. Moreover, after the front surface of the solder ball/copper pillar is bonded to the glass carrier after the solder ball/copper pillar is completed, the height difference of more than 60 μm is formed on the front surface due to the height of the solder ball and the copper pillar, so that the glass bonding needs to use an adhesive layer of more than 100 μm to achieve a flat covering step, and the time steps of material selection and heating are very complicated. In addition, due to the difference of the solder ball/copper pillar sections on the front side, the limitation of back grinding thinning stress is caused, so that the thickness of the ultra-thin wafer (less than 150 μm) cannot be achieved, which seriously affects the aperture of the TSV opening and limits the fine density of the connecting lines.
Disclosure of Invention
The invention aims to provide a wafer packaging method and a wafer packaging assembly, which realize double-sided electroplating, simplify process procedures, improve packaging efficiency, reduce packaging cost and realize production of ultrathin wafers.
The purpose of the invention can be realized by the following technical scheme:
a packaging method of a wafer comprises the following steps:
s1, performing a through silicon via process on the front surface of the wafer to form a through silicon via, filling a first metal filler in the through silicon via, wherein the through silicon via is a counter bore;
s2, performing yellow light and film coating process on the front surface of the wafer to form a first redistribution layer and a first metal contact point on the front surface of the wafer;
s3, bonding the front surface of the wafer on the carrier plate, and bonding the front surface of the wafer on the carrier plate through an adhesive;
s4, thinning the back of the wafer to make the through-silicon-via penetrate the thinned wafer;
s5, performing yellow light and film coating process on the back surface of the wafer to form a second rewiring layer and a second metal contact point on the back surface of the wafer;
s6, manufacturing a TGV communication hole on the back of the carrier plate;
s7, forming a Ni/Pd/Cu seed layer on the surface of the carrier plate and on the side wall and the bottom of the TGV communication hole by using chemical plating;
s8, coating photoresist on the surface of the carrier plate, and filling a second metal filler in the TGV communication hole by adopting electrode electroplating;
s9, removing the photoresist, coating the photoresist layer on the back of the wafer and the back of the carrier again, and reserving the position of the copper pillar bump;
s10, double-sided electroplating is carried out, and copper pillar bumps are formed at the reserved positions;
s11: and removing the double-sided photoresist.
Furthermore, the through silicon via is formed by deep plasma etching.
Further, the wafer 1 and the glass carrier plate 7 are bonded together by the adhesive 6 through UV bonding, the temperature is required to be 50-200 ℃, and the using time is below 30 minutes.
Further, the adhesive 6 bonds the wafer 1 and the glass carrier 7 together by heating and bonding, the temperature is required to be 150 ℃ and 300 ℃, and the time of use is below 30 minutes.
Furthermore, the TGV communication hole is formed on the back surface of the carrier plate by a yellow light process or a Laser perforation combined etching technology.
Further, the aperture of the through silicon via is less than or equal to 5 microns.
A packaging assembly of a wafer comprises the wafer and a carrier plate;
the wafer is provided with at least one through silicon via, and the through silicon via is arranged on the wafer along the thickness direction of the wafer; the front surface of the wafer is provided with a first redistribution layer, at least one first metal contact point, and at least one copper pillar bump on the front surface and the back surface of the wafer, wherein the copper pillar bumps are in one-to-one correspondence with the second metal fillers.
Further, the thickness of the wafer is greater than or equal to 50 microns and less than or equal to 100 microns.
The invention has the beneficial effects that:
the packaging method realizes double-sided electroplating, simplifies the process procedure, improves the packaging efficiency, reduces the packaging cost and realizes the production of ultrathin wafers.
Drawings
The invention will be further described with reference to the accompanying drawings.
FIG. 1 is a schematic diagram of a through-silicon via formed on a wafer according to the present invention;
FIG. 2 is a schematic structural diagram of filling a first metal filler in a through-silicon via according to the present invention;
FIG. 3 is a schematic structural diagram of the wafer after step S2 according to the present invention;
FIG. 4 is a schematic structural diagram of the wafer after step S3 according to the present invention;
FIG. 5 is a schematic structural diagram of the wafer after step S4 according to the present invention;
FIG. 6 is a schematic structural diagram of the wafer after step S5 according to the present invention;
FIG. 7 is a schematic structural diagram of the wafer after step S6 according to the present invention;
FIG. 8 is a schematic structural diagram of the wafer after step S7 according to the present invention;
FIG. 9 is a schematic view of the wafer after step S8 according to the present invention;
FIG. 10 is a schematic view of the wafer after step S9 according to the present invention;
FIG. 11 is a schematic structural diagram of the wafer after step S10 according to the present invention;
fig. 12 is a schematic structural diagram of the wafer after step S11 according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
A packaging method of a wafer comprises the following steps:
s1, performing a through silicon via process on the front surface of the wafer 1, and forming a through silicon via 2 by deep plasma etching, wherein as shown in figures 1 and 2, the through silicon via 2 is filled with a first metal filler 3, and the through silicon via 2 is a counter bore;
s2, performing yellow light and film coating process on the front surface of the wafer 1, and forming a first redistribution layer 4 and a first metal contact point 5 on the front surface of the wafer 1 as shown in FIG. 3;
s3, bonding the front surface of the wafer 1 on the carrier plate 7, and bonding the front surface of the wafer 1 on the carrier plate 7 through the adhesive 6 as shown in FIG. 4;
the adhesive 6 bonds the wafer 1 and the glass carrier plate 7 together through UV bonding, the temperature is required to be 50-200 ℃, and the using time is below 30 minutes;
the adhesive 6 bonds the wafer 1 and the glass carrier plate 7 together by heating bonding, the temperature is required to be 150-300 ℃, and the using time is below 30 minutes.
S4, thinning the back of the wafer 1, and enabling the through silicon via 2 to penetrate through the thinned wafer 1 as shown in FIG. 5;
s5, performing yellow light and film coating process on the back surface of the wafer 1, and forming a second redistribution layer 8 and a second metal contact 9 on the back surface of the wafer 1 as shown in FIG. 6;
s6, fabricating TGV communication holes 10 on the back of the carrier 7 by photolithography process or Laser via-hole combined etching technique, as shown in FIG. 7;
s7, forming a Ni/Pd/Cu seed layer 11 on the surface of the carrier plate 7 and on the side walls and the bottom of the TGV through holes by using chemical plating, as shown in FIG. 8;
s8, coating photoresist on the surface of the carrier plate 7, and filling the second metal filler 12 in the TGV communication hole by adopting electrode plating, as shown in figure 9;
s9, removing the photoresist, coating the photoresist layer 13 again on the back of the wafer and the back of the carrier plate 7, and reserving the position of the copper pillar bump, as shown in FIG. 10;
s10, double-sided electroplating, and forming copper pillar bumps 14 at the reserved positions, as shown in FIG. 11;
s11: the double-sided photoresist is removed as shown in fig. 12.
A packaging assembly of a wafer comprises a wafer 1 and a carrier plate 7.
The wafer 1 is provided with at least one through silicon via 2, and the through silicon via 2 is arranged on the wafer 1 along the thickness direction of the wafer 1; the front surface of the wafer 1 is provided with a first redistribution layer 4, at least one first metal contact point 5, and at least one copper pillar bump 14 on both the front surface and the back surface of the wafer 1, wherein the copper pillar bumps 14 correspond to the second metal fillers 12 one by one;
the thickness of the wafer 1 is 50 micrometers or more and 100 micrometers or less.
The aperture of the through-silicon via 100 is 5 μm or less.
In the description herein, references to the description of "one embodiment," "an example," "a specific example" or the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The foregoing shows and describes the general principles, essential features, and advantages of the invention. It will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, which are described in the specification and illustrated only to illustrate the principle of the present invention, but that various changes and modifications may be made therein without departing from the spirit and scope of the present invention, which fall within the scope of the invention as claimed.
Claims (8)
1. A method for packaging a wafer is characterized by comprising the following steps:
s1, performing a Through Silicon Via (TSV) process on the front surface of the wafer (1) to form a TSV (2), filling a first metal filler (3) into the TSV (2), wherein the TSV (2) is a counter bore;
s2, performing yellow light and film coating processes on the front surface of the wafer (1) to form a first redistribution layer (4) and a first metal contact point (5) on the front surface of the wafer (1);
s3, bonding the front surface of the wafer (1) on a carrier plate (7), and bonding the front surface of the wafer (1) on the carrier plate (7) through an adhesive (6);
s4, thinning the back of the wafer (1) to enable the through silicon via (2) to penetrate through the thinned wafer (1);
s5, performing yellow light and film plating processes on the back surface of the wafer (1) to form a second rewiring layer (8) and a second metal contact point (9) on the back surface of the wafer (1);
s6, manufacturing a TGV communication hole (10) on the back of the carrier plate (7);
s7, forming a Ni/Pd/Cu seed layer (11) on the surface of the carrier plate (7) and on the side wall and the bottom of the TGV communication hole by using chemical plating;
s8, coating photoresist on the surface of the carrier plate (7), and filling a second metal filler (12) in the TGV communication hole by adopting electrode electroplating;
s9, removing the photoresist, coating a photoresist layer (13) on the back of the wafer and the back of the carrier plate (7) again, and reserving the position of the copper pillar bump;
s10, double-sided electroplating is carried out, and copper pillar bumps (14) are formed at the reserved positions;
s11: and removing the double-sided photoresist.
2. The method for packaging the wafer as claimed in claim 1, wherein the through silicon via (2) is formed by deep plasma etching.
3. The method for encapsulating a wafer as claimed in claim 1, characterized in that the adhesive (6) bonds the wafer (1) and the glass carrier plate (7) together by UV bonding at a temperature of 50-200 ℃ for a period of less than 30 minutes.
4. The method for packaging a wafer as claimed in claim 1, wherein the adhesive (6) bonds the wafer (1) and the glass carrier (7) together by thermal bonding at a temperature of 150 ℃ and 300 ℃ for a time of 30 minutes or less.
5. The method for packaging a wafer as claimed in claim 1, wherein the TGV communication hole (10) is formed on the back surface of the carrier (7) by photolithography or Laser via-etching combined with etching.
6. The method for packaging a wafer according to claim 1, wherein the aperture of the through silicon via (100) is less than or equal to 5 μm.
7. A package assembly based on the packaging method of the wafer according to any one of claims 1 to 6, characterized in that the package assembly comprises a wafer (1) and a carrier plate (7);
the wafer (1) is provided with at least one through silicon via (2), and the through silicon via (2) is arranged on the wafer (1) along the thickness direction of the wafer (1); the front surface of the wafer (1) is provided with a first redistribution layer (4), at least one first metal contact point (5), and at least one copper pillar bump (14) on the front surface and the back surface of the wafer (1), wherein the copper pillar bumps (14) correspond to the second metal fillers (12) one by one.
8. The package assembly according to claim 7, characterized in that the thickness of the wafer (1) is equal to or greater than 50 microns and equal to or less than 100 microns.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011555786.5A CN112687618A (en) | 2020-12-23 | 2020-12-23 | Wafer packaging method and wafer packaging assembly |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011555786.5A CN112687618A (en) | 2020-12-23 | 2020-12-23 | Wafer packaging method and wafer packaging assembly |
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| Publication Number | Publication Date |
|---|---|
| CN112687618A true CN112687618A (en) | 2021-04-20 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202011555786.5A Pending CN112687618A (en) | 2020-12-23 | 2020-12-23 | Wafer packaging method and wafer packaging assembly |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200727500A (en) * | 2006-01-11 | 2007-07-16 | Advanced Semiconductor Eng | Wafer level package for image sensor components and its fabricating method |
| CN201994289U (en) * | 2011-01-31 | 2011-09-28 | 江阴长电先进封装有限公司 | Wafer level adapter plate structure |
| CN111446159A (en) * | 2020-03-11 | 2020-07-24 | 绍兴同芯成集成电路有限公司 | Production method for cutting front surface and thinning back surface |
| CN111524819A (en) * | 2020-04-29 | 2020-08-11 | 绍兴同芯成集成电路有限公司 | Glass carrier plate windowing process and double-sided metallization process in 2.5D and 3D packaging |
| CN111524820A (en) * | 2020-04-29 | 2020-08-11 | 绍兴同芯成集成电路有限公司 | Wafer double-sided lead-tin alloy bump forming process |
| CN111799188A (en) * | 2020-07-17 | 2020-10-20 | 绍兴同芯成集成电路有限公司 | Thinning wafer packaging process utilizing TSV and TGV |
-
2020
- 2020-12-23 CN CN202011555786.5A patent/CN112687618A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200727500A (en) * | 2006-01-11 | 2007-07-16 | Advanced Semiconductor Eng | Wafer level package for image sensor components and its fabricating method |
| CN201994289U (en) * | 2011-01-31 | 2011-09-28 | 江阴长电先进封装有限公司 | Wafer level adapter plate structure |
| CN111446159A (en) * | 2020-03-11 | 2020-07-24 | 绍兴同芯成集成电路有限公司 | Production method for cutting front surface and thinning back surface |
| CN111524819A (en) * | 2020-04-29 | 2020-08-11 | 绍兴同芯成集成电路有限公司 | Glass carrier plate windowing process and double-sided metallization process in 2.5D and 3D packaging |
| CN111524820A (en) * | 2020-04-29 | 2020-08-11 | 绍兴同芯成集成电路有限公司 | Wafer double-sided lead-tin alloy bump forming process |
| CN111799188A (en) * | 2020-07-17 | 2020-10-20 | 绍兴同芯成集成电路有限公司 | Thinning wafer packaging process utilizing TSV and TGV |
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Application publication date: 20210420 |
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