CN116137232A - Preparation process and application of high-density copper pillar micro-bump for realizing ultra-narrow pitch interconnection - Google Patents
Preparation process and application of high-density copper pillar micro-bump for realizing ultra-narrow pitch interconnection Download PDFInfo
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- 239000010949 copper Substances 0.000 title claims abstract description 101
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 title claims abstract description 100
- 229910052802 copper Inorganic materials 0.000 title claims abstract description 98
- 238000002360 preparation method Methods 0.000 title claims abstract description 15
- 238000000034 method Methods 0.000 claims abstract description 35
- 238000004519 manufacturing process Methods 0.000 claims abstract description 22
- 238000005530 etching Methods 0.000 claims abstract description 7
- 238000001259 photo etching Methods 0.000 claims abstract description 6
- 238000005498 polishing Methods 0.000 claims abstract description 4
- 238000004544 sputter deposition Methods 0.000 claims abstract description 4
- 235000012431 wafers Nutrition 0.000 claims description 24
- 238000009713 electroplating Methods 0.000 claims description 17
- 239000002184 metal Substances 0.000 claims description 14
- 229910052751 metal Inorganic materials 0.000 claims description 14
- 239000000654 additive Substances 0.000 claims description 6
- 230000000996 additive effect Effects 0.000 claims description 6
- 238000009826 distribution Methods 0.000 claims description 6
- 239000003795 chemical substances by application Substances 0.000 claims description 4
- 239000003112 inhibitor Substances 0.000 claims description 4
- 229920002120 photoresistant polymer Polymers 0.000 claims description 4
- RBTBFTRPCNLSDE-UHFFFAOYSA-N 3,7-bis(dimethylamino)phenothiazin-5-ium Chemical compound C1=CC(N(C)C)=CC2=[S+]C3=CC(N(C)C)=CC=C3N=C21 RBTBFTRPCNLSDE-UHFFFAOYSA-N 0.000 claims description 3
- 238000004026 adhesive bonding Methods 0.000 claims description 3
- 229960000907 methylthioninium chloride Drugs 0.000 claims description 3
- 230000003746 surface roughness Effects 0.000 abstract description 3
- 238000005516 engineering process Methods 0.000 description 12
- 238000004806 packaging method and process Methods 0.000 description 9
- 238000000151 deposition Methods 0.000 description 5
- 230000010354 integration Effects 0.000 description 5
- 230000008021 deposition Effects 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000005219 brazing Methods 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 239000004033 plastic Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000035882 stress Effects 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 241000486634 Bena Species 0.000 description 1
- 241001391944 Commicarpus scandens Species 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- DJRKUXZQFQJGGN-UHFFFAOYSA-M [7-(dimethylamino)phenothiazin-3-ylidene]-dimethylazanium;hydroxide Chemical compound [OH-].C1=CC(=[N+](C)C)C=C2SC3=CC(N(C)C)=CC=C3N=C21 DJRKUXZQFQJGGN-UHFFFAOYSA-M 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- ALKZAGKDWUSJED-UHFFFAOYSA-N dinuclear copper ion Chemical compound [Cu].[Cu] ALKZAGKDWUSJED-UHFFFAOYSA-N 0.000 description 1
- PCHPORCSPXIHLZ-UHFFFAOYSA-N diphenhydramine hydrochloride Chemical compound [Cl-].C=1C=CC=CC=1C(OCC[NH+](C)C)C1=CC=CC=C1 PCHPORCSPXIHLZ-UHFFFAOYSA-N 0.000 description 1
- 239000003814 drug Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 238000007731 hot pressing Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000002105 nanoparticle Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
- H01L21/603—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving the application of pressure, e.g. thermo-compression bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
- H01L2021/60007—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process
- H01L2021/60022—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process using bump connectors, e.g. for flip chip mounting
- H01L2021/60097—Applying energy, e.g. for the soldering or alloying process
- H01L2021/60135—Applying energy, e.g. for the soldering or alloying process using convection, e.g. reflow oven
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/11001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
- H01L2224/1146—Plating
- H01L2224/11462—Electroplating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/1147—Manufacturing methods using a lift-off mask
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- General Physics & Mathematics (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses a preparation process and application of a high-density copper pillar micro-bump for realizing ultra-narrow pitch interconnection, wherein the preparation process comprises the following steps: s1, sputtering a seed layer on a wafer; s2, manufacturing a sacrificial layer; s3, manufacturing a mask layer, photoetching and developing to obtain a soft mask pattern; a plurality of slotted holes are formed between the lines of the soft mask pattern, and extend downwards to the lower surface of the sacrificial layer; s4, preparing copper columns in the slotted holes, wherein the tops of the copper columns protrude out of the upper surface of the mask layer to form bonding parts; s5, polishing the surface of the copper column to a set height; s6, stripping the sacrificial layer and the mask layer; and S7, etching the seed layer, forming a bonding pad at the bottom of each copper column, and completing the preparation of the high-density copper column micro-salient points. The invention greatly reduces the surface roughness of the copper column, lays a condition foundation for realizing the low-temperature low-pressure bump bonding interconnection process, and realizes ultra-narrow pitch high-density interconnection.
Description
[ field of technology ]
The invention belongs to the technical field of chip packaging, and particularly relates to a preparation process and application of a high-density copper pillar micro-bump for realizing ultra-narrow pitch interconnection.
[ background Art ]
With the development of integrated circuit chip manufacturing technology nodes, the chip manufacturing technology following moore's law gradually approaches to physical limit, and correspondingly, the cost performance of the chip is also poorer and worse, on the other hand, the integration level of electronic packages required by the internet of things, big data, cloud computing and the like is higher and higher, the electrical connection between the chips is shorter and shorter, and the chips are continuously developed towards the high-density and light-weight directions.
With the increasing bandwidth of IC chips, there is a need to bring out more and more I/O ports. Conventional micro bump technology and wire bonding technology have difficulty meeting the requirements of high bandwidth IC chips. Therefore, fine pitch, high density micro bump technology is beginning to be widely used. With the development of micro-bump and micro-assembly technology, the micro-bump size and pitch are required to be continuously reduced in order to improve the integration level of 2.5D/3D stacked package.
At present, the micro-bump interconnection technology among chips with small-size fine pitch mainly adopts a copper column and a tin cap to realize bonding interconnection, and the process steps mainly relate to copper column preparation, solder deposition, hot-pressing reflow and the like, and the processes are mutually independent and very complicated and cannot be integrally and rapidly completed; and the high temperature and high pressure environment involved in the bonding interconnection process can cause thermal stress to the device, so that the reliability of the device is affected. Particularly for copper stud bumps with large aspect ratio, it is difficult to meet the requirements of low-temperature metal bonding processes. As disclosed in the prior art with patent publication number CN105023854a, a process for preparing a fine pitch copper pillar micro bump comprises the steps of: 1) Electroplating a seed layer on the surface of the wafer; 2) Depositing a copper layer; 3) Preparing a brazing filler metal layer; 4) Coating a mask layer; 5) Making an opening on the photoetching layer; 6) Etching the brazing material layer, the copper layer and the seed layer at the opening; 7) Stripping the residual mask layer; 8) And finally, forming copper column micro-bumps on the copper layer by a reflow process. The micro-bump manufacturing process cannot meet the requirement of the copper-copper bonding process due to the fact that the surface roughness of the copper column produced by the electroplating process is large after the seed layer is manufactured, the bonding surface smoothness requirement is very strict, the micro-bump manufactured by the electroplating process is poor in flatness, and when the depth-to-width ratio of the copper column is large, the flatness and strength of the pure metal copper column cannot meet the requirement of 12 inch wafer bonding, so that the overall bonding quality can be influenced.
Therefore, it is necessary to provide a new high-density copper pillar micro bump manufacturing process for realizing ultra-narrow pitch interconnection and application thereof to solve the above problems.
[ invention ]
The invention mainly aims to provide a preparation process of high-density copper pillar micro-bumps for realizing ultra-narrow pitch interconnection, which greatly reduces the surface roughness of copper pillars, lays a condition foundation for realizing a low-temperature low-pressure bump bonding interconnection process, and realizes ultra-narrow pitch high-density interconnection.
The invention realizes the aim through the following technical scheme: a preparation process of high-density copper pillar micro-bumps for realizing ultra-narrow pitch interconnection comprises the following steps:
s1, sputtering a seed layer on the upper surface of a wafer;
s2, manufacturing a sacrificial layer, wherein the sacrificial layer covers the seed layer;
s3, manufacturing a mask layer on the upper surface of the sacrificial layer, and carrying out photoetching and developing to obtain a needed soft mask pattern; a plurality of slotted holes are formed between the lines of the soft mask pattern, and extend downwards from the upper surface of the mask layer to the lower surface of the sacrificial layer; the number distribution of the slotted holes is consistent with the number distribution of copper columns to be prepared;
s4, preparing copper columns in the slotted holes, wherein the tops of the copper columns protrude out of the upper surface of the mask layer to form bonding parts;
s5, polishing the upper surface of the copper column to a set height;
s6, stripping the sacrificial layer and the mask layer;
and S7, etching the seed layer, forming a bonding pad at the bottom of each copper column, and completing the preparation of the high-density copper column micro-salient points.
Further, the seed layer is a Ti/Cu seed layer.
Further, the sacrificial layer is photoresist and is coated on the seed layer in a gluing mode.
Further, the diameter of the slot hole is 10-20 μm, and the depth is 100-150 μm.
Further, the copper pillar includes a pillar portion located in the slot and the bonding portion protruding out of the slot.
Further, the diameter of the bonding portion is larger than the diameter of the column portion.
Further, the copper pillar in the step S4 is prepared by an electroplating process, wherein the electroplating solution in the electroplating process comprises a base solution and an additive, the base solution is methylene blue, and the additive comprises an accelerator, an inhibitor, a leveling agent and benala green B.
Another object of the present invention is to provide an application of the high-density copper pillar micro-bump, which comprises the step of interconnecting two wafers with the high-density copper pillar micro-bump together by adopting a low-temperature low-pressure metal bonding process.
Further, the bonding temperature in the low-temperature low-pressure metal bonding process is 250-400 ℃; the dwell time is 30-45 min, and the dwell pressure is 30-45 mPa.
Compared with the prior art, the preparation process for the high-density copper pillar micro-bump for realizing ultra-narrow pitch interconnection has the beneficial effects that: firstly, forming slotted holes corresponding to the copper columns one by one on the mask layer, then forming the copper columns in the slotted holes in an electroplating mode, enabling the roots of the copper columns to extend to the seed layer and form strong connection with the seed layer, and guaranteeing the position stability and the adhesion firmness of the copper columns; the top of the copper column protrudes out of the mask layer to form a bonding part, and then the surface of the bonding part is polished, so that the surface flatness is improved, and the height consistency of the surfaces of all the copper columns is ensured; stripping the mask layer and the sacrificial layer, and finally etching to form a metal bonding pad at the bottom of the copper column; the process can realize high-density interconnection of copper columns with the minimum diameter of 10 mu m and the minimum pitch of 20 mu m, and realize ultra-narrow pitch high-density interconnection technology; the interconnection bonding between the wafer and the wafer can be realized by forming the copper column micro-bumps arranged in the lattice mode on the wafer, and the single chip can be embedded into the silicon substrate for plastic packaging while the overall packaging thickness is not increased, so that the problem of higher packaging thickness is solved; the wafer micro-bump copper and copper are bonded at low temperature, so that the stress problem between wafers can be reduced, and the uniformity and packaging yield of the whole wafer are improved; the single chip has larger size and larger line interval and the problem of low integration level is solved, so that the thickness of the package is reduced, the size of the chip is reduced, the overall electrical performance of the packaged device is improved, and the advantages of wafer-level stacking and TSV technology short interconnection are fully exerted.
[ description of the drawings ]
FIG. 1 is a process flow diagram of an embodiment of the present invention;
FIGS. 2-7 are schematic views illustrating structural changes of a wafer during a manufacturing process according to embodiments of the present invention;
the figures represent the numbers:
1-wafer; 2-seed layer, 21-pad; 3-a sacrificial layer; 4-mask layers, 41-slotted holes; 5-copper pillars, 51-bonding portions.
[ detailed description ] of the invention
In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system configurations, techniques, etc. in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.
The technical scheme provided by the application is explained in detail below with reference to specific embodiments.
Referring to fig. 1-7, the present embodiment is a process for preparing high-density copper pillar micro bump for realizing ultra-narrow pitch interconnection, which includes the following steps:
s1, sputtering a seed layer 2 on the upper surface of a wafer 1, wherein the seed layer 2 is a Ti/Cu seed layer;
s2, manufacturing a sacrificial layer 3 on the upper surface of the seed layer 2, wherein the sacrificial layer 3 is photoresist, and coating the photoresist on the seed layer 2 in a gluing mode;
s3, manufacturing a mask layer 4 on the sacrificial layer 3, and carrying out photoetching and developing to obtain a needed soft mask pattern; a plurality of slotted holes 41 are formed between the lines of the soft mask pattern, and the slotted holes 41 extend downwards from the upper surface of the mask layer 4 to the lower surface of the sacrificial layer 3; the number distribution of the slotted holes 41 is consistent with the number distribution of copper columns to be prepared;
s4, electroplating in the slotted hole 41 to obtain a copper column 5, wherein the top of the copper column 5 protrudes out of the upper surface of the mask layer 4 to form a bonding part 51, and the part of the copper column 5 filled in the slotted hole 41 forms a column part (not marked in the figure), wherein the diameter of the bonding part 51 is larger than that of the column part; the diameter of the slot 41 is 10-20 μm and the depth is 100-150 μm. Through set up the bigger bonding portion 51 of diameter at the top of copper post 5 for two wafers are more convenient to align when bonding, improve the area of contact when bonding, make the contact more abundant, improve bonding quality.
S5, polishing the upper surfaces of the copper columns 5, on one hand, ensuring the consistency of the heights of all the copper columns 5, ensuring that the tops of all the copper columns 5 are positioned in the same plane, on the other hand, reducing the roughness of the surfaces of the copper columns 5, and improving the smoothness of the surfaces of the copper columns so as to meet the requirements of a low-temperature metal bonding process;
s6, stripping the sacrificial layer 3 and the mask layer 4;
and S7, dry etching is adopted on the seed layer 2, a bonding pad 21 is formed at the bottom of each copper column 5, and the preparation of the high-density copper column micro-salient point is completed.
When the method is applied, two wafers with high-density copper pillar micro-bumps are interconnected together by adopting a copper-copper low-temperature low-pressure metal bonding process. Wherein the bonding temperature is 250-400 ℃; the dwell time is 30-45 min, and the dwell pressure is 30-45 mPa.
In step S4, since the diameter of the slot 41 is smaller and the aspect ratio is larger, the electroplating solution cannot sufficiently enter the slot 41, so that the metal is easy to be etched; the seed layer 2 is easy to break in electrical connection, the metal conducting layers are not mutually communicated, and the electrical performance is not connected; in order to solve the technical problem, in this embodiment, the copper pillar 5 is manufactured by an electroplating process, and the electroplating solution used in electroplating includes a base solution and an additive, wherein the base solution is methylene blue, and the additive includes an accelerator, an inhibitor, a leveling agent and bena green B. The methylene blue base solution is mainly used for providing nano twin crystal copper film deposition, and the accelerator is used for controlling the copper atom deposition rate; the inhibitor is used for controlling the production direction and the deposition rate of copper atoms; the leveling agent is used for controlling uniformity in the copper atom growth process; the Jianna green B is used for controlling the film forming quality of the copper film. By changing the copper molecular arrangement structure and adopting the nano-particle composite material (namely the deposited nano twin crystal copper film), the electroplating liquid medicine can smoothly enter the slotted hole 41 and fully fill the slotted hole 41, so that a compact and firm copper column 5 can be formed in the slotted hole 41, and the electric connection fracture failure of the metal conductive layer is avoided.
In the embodiment, firstly, slotted holes 41 corresponding to the copper columns 5 one by one are formed on the mask layer 4, then, the copper columns 5 are formed in the slotted holes 41 in an electroplating mode, the roots of the copper columns 5 extend to the seed layer 2 and form strong connection with the seed layer 2, so that the position stability and the adhesion firmness of the copper columns 5 are ensured; the top of the copper column 5 protrudes out of the mask layer 4, and then the surface of the copper column 5 is polished, so that the surface flatness is improved, and the height consistency of the surfaces of all the copper columns is ensured; stripping the mask layer 4 and the sacrificial layer 3, and finally etching to form a metal bonding pad at the bottom of the copper column 5; the process can realize high-density interconnection of copper columns with the minimum diameter of 10 mu m and the minimum pitch of 20 mu m, and realize ultra-narrow pitch high-density interconnection technology; the interconnection bonding between the wafer and the wafer can be realized by forming the copper column micro-bumps arranged in the lattice mode on the wafer, and the single chip can be embedded into the silicon substrate for plastic packaging while the overall packaging thickness is not increased, so that the problem of higher packaging thickness is solved; the wafer micro-bump copper and copper are bonded at low temperature, so that the stress problem between wafers can be reduced, and the uniformity and packaging yield of the whole wafer are improved; the single chip has larger size and larger line interval and the problem of low integration level is solved, so that the thickness of the package is reduced, the size of the chip is reduced, the overall electrical performance of the packaged device is improved, and the advantages of wafer-level stacking and TSV technology short interconnection are fully exerted.
The embodiment realizes the preparation of the high-density interconnection micro-bumps with the minimum diameter of 10 mu m and the minimum pitch of 20 mu m through inverse line photoetching and etching processes, reduces the overall thickness of the product and the total number of layers after encapsulation, and meets the urgent requirements of the electronic product on high integration level and high performance of the chip.
What has been described above is merely some embodiments of the present invention. It will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the spirit of the invention.
Claims (9)
1. A preparation process for realizing ultra-narrow pitch interconnection of high-density copper pillar micro-bumps is characterized by comprising the following steps of: which comprises the following steps:
s1, sputtering a seed layer on the upper surface of a wafer;
s2, manufacturing a sacrificial layer, wherein the sacrificial layer covers the seed layer;
s3, manufacturing a mask layer on the upper surface of the sacrificial layer, and carrying out photoetching and developing to obtain a needed soft mask pattern; a plurality of slotted holes are formed between the lines of the soft mask pattern, and extend downwards from the upper surface of the mask layer to the lower surface of the sacrificial layer; the number distribution of the slotted holes is consistent with the number distribution of copper columns to be prepared;
s4, preparing copper columns in the slotted holes, wherein the tops of the copper columns protrude out of the upper surface of the mask layer to form bonding parts;
s5, polishing the upper surface of the copper column to a set height;
s6, stripping the sacrificial layer and the mask layer;
and S7, etching the seed layer, forming a bonding pad at the bottom of each copper column, and completing the preparation of the high-density copper column micro-salient points.
2. The process for preparing the high-density copper pillar micro-bump for realizing ultra-narrow pitch interconnection according to claim 1, wherein the process comprises the following steps: the seed layer is a Ti/Cu seed layer.
3. The process for preparing the high-density copper pillar micro-bump for realizing ultra-narrow pitch interconnection according to claim 1, wherein the process comprises the following steps: the sacrificial layer is photoresist and is coated on the upper surface of the seed layer in a gluing mode.
4. The process for preparing the high-density copper pillar micro-bump for realizing ultra-narrow pitch interconnection according to claim 1, wherein the process comprises the following steps: the diameter of the slot hole is 10-20 mu m, and the depth is 100-150 mu m.
5. The process for preparing the high-density copper pillar micro-bump for realizing ultra-narrow pitch interconnection according to claim 1 or 4, which is characterized in that: the copper pillar includes a pillar portion located within the slot and the bonding portion protruding from the slot.
6. The process for preparing the high-density copper pillar micro-bump for realizing ultra-narrow pitch interconnection according to claim 5, wherein the process comprises the following steps of: the diameter of the bonding portion is larger than the diameter of the column portion.
7. The process for preparing the high-density copper pillar micro-bump for realizing ultra-narrow pitch interconnection according to claim 1, wherein the process comprises the following steps: the copper column in the step S4 is prepared by adopting an electroplating process, wherein the electroplating solution in the electroplating process comprises a base solution and an additive, the base solution is methylene blue, and the additive comprises an accelerator, an inhibitor, a leveling agent and benala green B.
8. The use of the high-density copper pillar micro bump according to claim 1, characterized in that: the method comprises the step of interconnecting two wafers with the high-density copper pillar micro-bumps together by adopting a low-temperature low-pressure metal bonding process.
9. The use of high-density copper pillar micro-bumps as set forth in claim 8, wherein: the bonding temperature in the low-temperature low-pressure metal bonding process is 250-400 ℃; the dwell time is 30-45 min, and the dwell pressure is 30-45 mPa.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117747455A (en) * | 2024-02-21 | 2024-03-22 | 北京大学 | Micro-bump substrate based on laser processing, preparation method and micro-bump interconnection structure |
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2023
- 2023-02-24 CN CN202310160698.2A patent/CN116137232A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117747455A (en) * | 2024-02-21 | 2024-03-22 | 北京大学 | Micro-bump substrate based on laser processing, preparation method and micro-bump interconnection structure |
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