CN113380752A - Semiconductor structure and manufacturing method thereof - Google Patents

Semiconductor structure and manufacturing method thereof Download PDF

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Publication number
CN113380752A
CN113380752A CN202110545063.5A CN202110545063A CN113380752A CN 113380752 A CN113380752 A CN 113380752A CN 202110545063 A CN202110545063 A CN 202110545063A CN 113380752 A CN113380752 A CN 113380752A
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Prior art keywords
layer
via hole
substrate
semiconductor structure
rewiring
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CN202110545063.5A
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Chinese (zh)
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吕文隆
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Priority to CN202110545063.5A priority Critical patent/CN113380752A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The present disclosure relates to semiconductor structures and methods of fabricating the same. The method comprises the steps of combining a die (such as a fine pillar fine/thin post) for defining a via opening (via opening) and a first heavy wiring layer (Fan-Out) which are formed in advance on an adhesive layer on a substrate, removing the die for defining the via opening to define the first via opening in the first heavy wiring layer, removing part of the adhesive layer to expose a liner of the substrate through plasma etching to define a second via opening, and finally filling a conductive material in the first via opening and the second via opening to form a via (via) for electrically connecting the first heavy wiring layer and the substrate, so that the stability of a semiconductor structure is improved, and the yield of products is improved.

Description

Semiconductor structure and manufacturing method thereof
Technical Field
The present disclosure relates to the field of semiconductor technology, and more particularly, to a semiconductor structure and a method for fabricating the same.
Background
The processing capability of semiconductor wafers is improved year by year, and the processing capability of semiconductor substrates can meet the requirement of the butt joint of chips and substrates only after the steps are carried out. FOCoS (Fan Out Chip on Substrate) is the main method for combining Fan-Out and Substrate at present, FOsub (Fan-Out Substrate) is another method for combining Fan-Out and Substrate, Fan-Out (RDL layer) and Substrate are combined through an adhesive layer (Adhesion film), and an electric channel between Fan-Out and Substrate is communicated through a via hole (via).
In the current FOSub process, after the Fan out structure is fixed to Substrate by an additive film, a hole is opened to form via, but the current limit of laser process capability (minimum aperture and maximum hole depth) is limited, and a small aperture cannot be prepared and the hole depth cannot be satisfied at one time. If plasma etching is selected, lateral erosion may occur, which may cause hole wall abnormality. The quality of via hole formation affects the electrical connection between the redistribution layer and the substrate, and the stability of the semiconductor structure.
Disclosure of Invention
The present disclosure provides semiconductor structures and methods of fabricating the same.
In a first aspect, the present disclosure provides a semiconductor structure comprising: a substrate having a pad; the bonding layer is arranged on the substrate; a first rewiring layer provided on the adhesive layer; and the through hole comprises a second through hole and a first through hole which are arranged from bottom to top, the first through hole extends from the first heavy wiring layer to the bonding layer, and the second through hole extends from the bonding layer to the liner of the substrate.
In some alternative embodiments, the lower end surfaces of the first via holes are located at the same horizontal position.
In some alternative embodiments, the heights of the second via holes are different.
In some optional embodiments, the first via hole includes a first seed layer, a second seed layer, and a conductive pillar.
In some optional embodiments, the second via hole includes the second seed layer and the conductive pillar.
In some alternative embodiments, the lower opening of the first via hole has a larger aperture than the aperture of the second via hole.
In some alternative embodiments, the second via hole gradually expands and then gradually contracts in a direction toward the substrate.
In some optional embodiments, the semiconductor structure further comprises: a second adhesive layer provided on the first rewiring layer; a second rewiring layer provided on the second adhesive layer; and a third via hole electrically connecting the first rewiring layer and the second rewiring layer.
In some optional embodiments, the semiconductor structure further comprises: the electronic element is electrically connected with the first rewiring layer and/or the second rewiring layer; and the bottom filling material is used for filling a gap between the electronic element and the second rewiring layer.
In a second aspect, the present disclosure provides a method of fabricating a semiconductor structure, the method comprising: providing a carrier, wherein the carrier comprises a via hole opening mold, a demolding layer, a first seed layer and a first rewiring layer; bonding a carrier to a substrate through an adhesive layer, the substrate having a liner; removing the via hole opening mold and the demolding layer to define a first via hole extending from the first rewiring layer to the bonding layer; removing part of the adhesive layer to expose the liner to define a second via opening extending from the adhesive layer to the substrate; and sequentially forming a second seed layer and a conductive column in the first via hole and the second via hole to form a via hole electrically connecting the first redistribution layer and the substrate.
In some alternative embodiments, the carrier is formed by: providing a wafer; etching the wafer to form a via hole opening mold; sequentially forming a demolding layer, a first seed layer and a first rewiring layer on the via hole opening mold; and etching part of the first seed layer to expose the tip of the demolding layer so as to form the carrier comprising the via hole opening mold, the demolding layer, the first seed layer and the first rewiring layer which are sequentially arranged.
In some optional embodiments, the method further comprises: providing a second rewiring layer; bonding a second rewiring layer onto the first rewiring layer through a second adhesive layer; a third via hole is formed on the second rewiring layer to electrically connect the first rewiring layer and the second rewiring layer.
In order to solve the problem that via holes are limited by the limit of the current laser (laser) process capability (minimum aperture and maximum aperture depth), small aperture cannot be prepared, and the hole depth cannot be satisfied at one time, or the side etching phenomenon occurs due to selective plasma (plasma) etching, causing abnormal hole wall, the semiconductor structure and the manufacturing method thereof provided by the present disclosure combine a pre-formed mold (e.g. pillar fine/thin post) for defining via hole opening (via opening) and a first redistribution layer (Fan-Out) onto an adhesive layer on a substrate, and define a first via hole in the first redistribution layer by removing the mold for defining via hole opening, and expose a liner of the substrate by plasma etching to define a second via hole, and finally fill a conductive material in the first via hole and the second via hole to form a via hole electrically connecting the first redistribution layer and the substrate (minimum aperture and maximum aperture depth) via), the stability of the semiconductor structure is improved, and the yield of products is improved. In addition, the liner of the substrate is exposed by removing part of the bonding layer through plasma etching to define the second via hole, so that the bottom of the via hole is easy to contact and match the liner with inconsistent thickness, and various electrical connection problems caused by inconsistent thickness of the liner of the substrate are avoided.
Drawings
Other features, objects and advantages of the disclosure will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:
fig. 1-10 are first through tenth structural schematics of one embodiment of a semiconductor structure according to the present disclosure;
fig. 11A to 11H are schematic structural views in the manufacturing process of a semiconductor structure according to the present disclosure.
Description of the symbols:
1-substrate, 2-adhesive layer, 21-particle, 3-first redistribution layer, 4-via, 41-first via, 411-first seed layer, 412-second seed layer, 413-conductive post, 42-second via, 5-second adhesive layer, 6-second redistribution, 7-third via, 8-electronic component, 9-carrier, 91-wafer, 92-via open-cell mold, 93-release layer, 10-underfill, 11-conductive line, 12-multilayer redistribution layer.
Detailed Description
The following description of the embodiments of the present disclosure will be provided in conjunction with the accompanying drawings and examples, and those skilled in the art can easily understand the technical problems and effects of the present disclosure. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant invention and not restrictive of the invention. In addition, for convenience of description, only portions related to the related invention are shown in the drawings.
It should be noted that the structures, proportions, and dimensions shown in the drawings and described in the specification are for the understanding and reading of the present disclosure, and are not intended to limit the conditions under which the present disclosure can be implemented, so they are not technically significant, and any modifications of the structures, changes in the proportions and adjustments of the dimensions should be made without affecting the efficacy and attainment of the same. In the present specification, the terms "upper", "first", "second" and "first" are used for clarity of description only, and are not intended to limit the scope of the present disclosure, and changes or modifications in relative relationships thereof should be construed as being within the scope of the present disclosure without substantial technical changes.
In addition, the embodiments and features of the embodiments in the present disclosure may be combined with each other without conflict. The present disclosure will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.
Referring to fig. 1-10, fig. 1-10 illustrate first through tenth structural schematic diagrams of a semiconductor structure according to an embodiment of the present disclosure.
Fig. 1 is a schematic structural diagram of one embodiment of a semiconductor structure according to the present disclosure. As shown in fig. 1, the semiconductor structure may include: substrate 1, adhesive layer 2, first redistribution layer 3, and at least one via 4. The substrate 1 has a spacer. The adhesive layer 2 is provided on the substrate 1. The first rewiring layer 3 is provided on the adhesive layer 2. The via hole 4 includes a second via hole 42 and a first via hole 41 provided from bottom to top, the first via hole 41 extending from the first rewiring layer 3 to the adhesive layer 2, and the second via hole 42 extending from the adhesive layer 2 to the liner of the substrate 1.
The substrate 1 may include organic and/or inorganic substances, and the organic substances may be, for example: polyamide fibers (Polyamide, PA), Polyimide (PI), Epoxy resins (Epoxy), Poly-p-Phenylene Benzobisoxazole (PBO) fibers, FR-4 Epoxy glass cloth laminates, PP (PrePreg, PrePreg or so-called PrePreg, PrePreg), ABF (Ajinomoto Build-up Film), and the like, and inorganic substances may be, for example, silicon (Si), glass (glass), ceramics (ceramic), silicon oxide, silicon nitride, tantalum oxide, and the like. The substrate 1 may be a PCB (Printed Circuit Board).
The adhesive layer 2 may be a structural layer that provides adhesion between structures.
Various wires, through holes, buried holes or blind holes may be provided in the first rewiring layer 3 to realize line connection. It should be noted that the size or direction of the through hole, buried hole or blind hole is not specifically limited. If a via, buried via or blind via is provided, the via, buried via or blind via may be filled with or contain a conductive material such as a metal or metal alloy. Here, the metal may be, for example, gold (Au), silver (Ag), aluminum (Al), copper (Cu), or an alloy thereof.
The via hole 4 may realize electrical connection between the substrate 1 and the first rewiring layer 3.
In some alternative embodiments, as shown in fig. 1, the lower end surfaces of the first via holes 41 may be located at the same horizontal position.
Here, since the first via holes 41 are defined by a mold formed in advance to define the openings of the via holes 4, the mold may have at least one thin pillar having the same height, the height of each of the defined first via holes 41 may be the same, and the lower end surfaces of each of the first via holes 41 may be located at the same horizontal position.
In some alternative embodiments, as shown in fig. 1, the height of each second via hole 42 may be different.
Here, since the liner thickness of the substrate 1 is not uniform, the liner of the substrate 1 is exposed by removing a portion of the adhesive layer 2 by plasma etching, and the height of the second via hole 42 defined may be different to expose the liner having a non-uniform thickness.
In some alternative embodiments, as shown in fig. 1, the first via hole 41 may include a first seed layer 411, a second seed layer 412, and a conductive pillar 413 disposed.
Here, the first via hole 41 is defined in the first redistribution layer 3, and the first redistribution layer 3 is formed in advance, and the first seed layer 411 is included in the formation process.
In some alternative embodiments, as shown in fig. 1, the second via 42 may include the second seed layer 412 and the conductive pillar 413 disposed.
In some alternative embodiments, as shown in fig. 10, the aperture of the lower opening of the first via hole 41 may be larger than the aperture of the second via hole 42.
In some alternative embodiments, as shown in fig. 10, the second via hole 42 may be gradually expanded and then gradually contracted in a direction toward the substrate 1.
In some alternative embodiments, as shown in fig. 2, the semiconductor structure may further include a second adhesive layer 5. The second adhesive layer 5 may be provided on the first rewiring layer 3. The second rewiring layer 6 may be provided on the second adhesive layer 5. The third via 7 may electrically connect the first rewiring layer 3 and the second rewiring layer 6.
In some alternative embodiments, as shown in fig. 5, the semiconductor structure may further include an electronic component 8 and an underfill material 10. The electronic component 8 may be electrically connected to the first redistribution layer 3 and/or the second redistribution layer 6. The underfill material 10 may fill a gap between the electronic element 8 and the second rewiring layer 6.
In some alternative embodiments, as shown in fig. 6, the semiconductor structure may further include a wire 11. The electrical connection may be made by wire bonding both ends of the wire 11 to the electronic element 8 and the second rewiring layer 6, respectively.
In some alternative embodiments, as shown in fig. 3, the first redistribution layer 3 may be a multi-layer redistribution layer 12.
In some alternative embodiments, as shown in fig. 4, the substrate 1 may be a rewiring layer.
In some alternative embodiments, as shown in fig. 7, the binding layer 2 may also include particles 21. The particles may be fillers (fillers), for example, to enhance structural strength.
In some alternative embodiments, as shown in fig. 8, the conductive pillar 413 may be incompletely filled, for example, a via may be provided in the center of the conductive pillar 413. The cost can be saved, and the problem that the electric effect is influenced because the gap is easily generated by complete filling is avoided.
In some alternative embodiments, as shown in fig. 9, the upper opening diameter D of the via hole 4 may be between 10 microns and 20 microns, the lower opening diameter D of the via hole 4 may be between 3 microns and 10 microns, and the ratio of the upper opening diameter D of the via hole 4 to the lower opening diameter D of the via hole 4 is between 0.65 and 1. Thickness t of first rewiring layer 31May be between 3 microns and 10 microns, the thickness t of the adhesive layer 22May be between 10 and 40 microns, the distance a of the adhesive layer 2 to the substrate 1 may be between 20 and 60 microns, the thickness h of the spacer may be between 5 and 20 microns, the height p of the first via 41 in the adhesive layer 2 is between 5 and 30 microns, and the height k of the second via 42 is between 5 and 20 microns. The side wall angle theta of the via hole 4 is 30 degrees to 80 degrees, and the thickness t of the first rewiring layer 31Thickness t of adhesive layer 22And the ratio of the sum of (a) to the upper opening hole diameter D of the via hole 4 is between 0.65 and 5.
The semiconductor structure provided by the present disclosure is formed by bonding a pre-formed mold (e.g., a pillar fin/thin post) for defining an opening (via opening) of a via hole 4 and a first redistribution layer 3(Fan-Out) to an adhesive layer 2 on a substrate 1, removing the via opening mold 92 for defining a via hole to define a first via hole 41 in the first redistribution layer 3, removing a portion of the adhesive layer 2 by plasma etching to expose a pad of the substrate 1 to define a second via hole 42, and finally filling a conductive material in the first via hole 41 and the second via hole 42 to form a via hole 4(via) electrically connecting the first redistribution layer 3 and the substrate 1, which improves the stability of the semiconductor structure and is beneficial to improving the yield of products. In addition, the liner of the substrate 1 is exposed by removing part of the adhesive layer 2 through plasma etching to define the opening of the second via hole 42, so that the bottom of the via hole 4 is easy to contact and match the liner with inconsistent thickness, and various electrical connection problems caused by inconsistent thickness of the liner of the substrate 1 are avoided.
Fig. 11A to 11H are schematic structural views in the manufacturing process of a semiconductor structure according to the present disclosure. The figures have been simplified for a better understanding of various aspects of the disclosure.
Referring to fig. 11D, a carrier 9 is provided, and the carrier 9 may include a via opening mold 92, a release layer 93, a first seed layer 411, and a first redistribution layer 3.
In some alternative embodiments, referring to fig. 11A-11D, the carrier 9 may be formed by: a wafer 91 is provided (fig. 11A). Wafer 91 is etched to form via opening mold 92 (fig. 11B). A mold release layer 93, a first seed layer 411, and a first rewiring layer 3 are sequentially formed on the via hole forming mold 92 (fig. 11C). A portion of the first seed layer 411 is etched to expose the tip of the release layer 93 to form the via opening mold 92, the release layer 93, the first seed layer 411, and the carrier 9 of the first rewiring layer 3 (fig. 11D).
Referring to fig. 11E, the carrier 9 is bonded to the substrate 1 through the adhesive layer 2, and the substrate 1 has a pad.
Referring to fig. 11F, the via opening mold 92 and the release layer 93 are removed to define a first via opening extending from the first redistribution layer 3 to the adhesive layer 2. A portion of the adhesive layer 2 is removed to expose the liner to define a second via opening extending from the adhesive layer 2 to the substrate 1.
Referring to fig. 11G, a second seed layer 412 and a conductive pillar 413 are sequentially formed in the first via hole and the second via hole to form a via hole 4 electrically connecting the first redistribution layer 3 and the substrate 1.
In some optional embodiments, referring to fig. 11H, the method may further include: a second rewiring layer 6 is provided. The second rewiring layer 6 is bonded to the first rewiring layer 3 by a second adhesive layer 5. A third via 7 is formed on the second rewiring layer 6 to electrically connect the first rewiring layer 3 and the second rewiring layer 6.
The method in this embodiment can achieve similar technical effects to the semiconductor package structure in the foregoing embodiments, and details are not repeated here.
While the present disclosure has been described and illustrated with reference to particular embodiments thereof, such description and illustration are not intended to limit the present disclosure. It will be clearly understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not be drawn to scale. There may be a difference between the technical reproduction in the present disclosure and the actual device due to variables in the manufacturing process and the like. There may be other embodiments of the disclosure that are not specifically illustrated. The specification and drawings are to be regarded in an illustrative rather than a restrictive sense. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to fall within the scope of the claims appended hereto. Although the methods disclosed herein have been described with reference to particular operations performed in a particular order, it should be understood that these operations may be combined, sub-divided, or reordered to form equivalent methods without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations is not a limitation of the present disclosure.

Claims (10)

1. A semiconductor structure, comprising:
a substrate having a pad;
the bonding layer is arranged on the substrate;
a first rewiring layer provided on the adhesive layer;
the through hole comprises a second through hole and a first through hole which are arranged from bottom to top, the first through hole extends from the first heavy wiring layer to the bonding layer, the second through hole extends from the bonding layer to the substrate liner, and the lower end face of each first through hole is located at the same horizontal position.
2. The semiconductor structure of claim 1, wherein a height of each of said second vias is different.
3. The semiconductor structure of claim 1 or 2, wherein the first via hole comprises a first seed layer, a second seed layer, and a conductive pillar.
4. The semiconductor structure of claim 3, wherein the second via comprises the second seed layer and the conductive pillar.
5. The semiconductor structure of claim 1 or 2, wherein the second via hole gradually expands and then gradually contracts in a direction toward the substrate.
6. The semiconductor structure of claim 1 or 2, wherein the semiconductor structure further comprises:
a second adhesive layer provided on the first rewiring layer;
a second rewiring layer provided on the second adhesive layer;
and a third via hole electrically connecting the first rewiring layer and the second rewiring layer.
7. The semiconductor structure of claim 6, wherein the semiconductor structure further comprises:
an electronic element electrically connected to the first redistribution layer and/or the second redistribution layer;
and an underfill material filling a gap between the electronic element and the second redistribution layer.
8. A method of fabricating a semiconductor structure, comprising:
providing a carrier, wherein the carrier comprises a via hole opening mold, a demolding layer, a first seed layer and a first rewiring layer;
bonding the carrier to a substrate through an adhesive layer, wherein the substrate has a liner;
removing the via opening mold and the release layer to define a first via opening extending from the first redistribution layer into the adhesion layer;
removing a portion of the adhesive layer to expose the pad to define a second via opening extending from the adhesive layer to the substrate;
and sequentially forming a second seed layer and a conductive column in the first via hole and the second via hole to form a via hole electrically connecting the first redistribution layer and the substrate.
9. The method of claim 8, wherein the carrier is formed by:
providing a wafer;
etching the wafer to form the via hole opening mold;
sequentially forming the demolding layer, the first seed layer and the first rewiring layer on the via hole punching mold;
and etching part of the first seed layer to expose the tip of the demolding layer so as to form the carrier of the via hole opening mold, the demolding layer, the first seed layer and the first rewiring layer which are sequentially arranged.
10. The method of claim 8 or 9, wherein the method further comprises:
providing a second rewiring layer;
bonding the second rewiring layer to the first rewiring layer through a second adhesive layer;
forming a third via hole on the second rewiring layer to electrically connect the first rewiring layer and the second rewiring layer.
CN202110545063.5A 2021-05-19 2021-05-19 Semiconductor structure and manufacturing method thereof Pending CN113380752A (en)

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Application Number Priority Date Filing Date Title
CN202110545063.5A CN113380752A (en) 2021-05-19 2021-05-19 Semiconductor structure and manufacturing method thereof

Publications (1)

Publication Number Publication Date
CN113380752A true CN113380752A (en) 2021-09-10

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