CN219917164U

CN219917164U - Semiconductor packaging device

Info

Publication number: CN219917164U
Application number: CN202320147933.8U
Authority: CN
Inventors: 吕文隆
Original assignee: Advanced Semiconductor Engineering Inc
Current assignee: Advanced Semiconductor Engineering Inc
Priority date: 2023-02-01
Filing date: 2023-02-01
Publication date: 2023-10-27
Anticipated expiration: 2033-02-01

Abstract

The utility model provides a semiconductor packaging device, comprising: a bottom layer rewiring layer; the first chip is provided with a first rewiring layer on the active surface and is arranged on the bottom rewiring layer with the active surface upwards; the active surface of the second chip is provided with a second rewiring layer, and the second chip is arranged on the bottom rewiring layer with the active surface upwards; the first chip and the second chip are respectively and electrically connected with the bottom layer rewiring layer through wire bonding. According to the utility model, the first re-wiring layer and the second re-wiring layer which are independent of each other are respectively arranged on the active surface of the first chip and the active surface of the second chip, so that the range of the re-wiring layer is limited to the surface area of each chip, and the phenomenon that stress of the re-wiring layer due to mismatch of CTE is accumulated in gaps between chips can be avoided, thereby eliminating stress accumulation of the continuous and large-area re-wiring layer, and being beneficial to improving the problems of warping of the re-wiring layer, extended line cracks, solder deformation cracks and the like.

Description

Semiconductor packaging device

Technical Field

The utility model relates to the technical field of semiconductor packaging, in particular to a semiconductor packaging device.

Background

In a semiconductor package apparatus, a rewiring layer (Redistributed layer, RDL) is included to connect a plurality of chips. RDL is a multi-layer structure, with more than one internal material, there is a problem of mismatch in coefficient of thermal expansion (CTE-mismatch) between the materials. For a Panel (Panel) with a large area, for example, a Panel with a surface of 300mm×300mm or 600mm×600mm, a wide range of RDL is formed, and a warp (warp) phenomenon is generated due to the fact that stress accumulated in each layer of material in RDL due to CTE-mismatch cannot be released, and the warp deformation phenomenon causes a Line crack (Line crack), a solder deformation crack (Solder deformation crack), and the like.

Disclosure of Invention

The utility model provides a semiconductor packaging device which is used for solving the problems of warping, circuit cracks, solder deformation cracks and the like caused by stress accumulated by mismatch of CTE (coefficient of thermal expansion) of large-area RDL.

In order to achieve the above purpose, the utility model adopts the following technical scheme: a semiconductor package apparatus comprising: a bottom layer rewiring layer; the first chip is provided with a first rewiring layer on the active surface and is arranged on the bottom rewiring layer with the active surface upwards; the active surface of the second chip is provided with a second rewiring layer, and the second chip is arranged on the bottom rewiring layer with the active surface upwards; the first chip and the second chip are respectively and electrically connected with the bottom layer rewiring layer through wire bonding.

In some alternative embodiments, the first and second redistribution layers are each provided with an electrical connection for external electrical connection, and the first and second redistribution layers are discontinuous.

In some alternative embodiments, the electrical connection has a solder bump between the electrical connection and the first or second redistribution layer.

In some alternative embodiments, one end of the wire bond is connected to the underlying rewiring layer, and the other end is connected to the active surface of the first chip or the active surface of the second chip.

In some alternative embodiments, one end of the wire bond is connected to the underlying rewiring layer, and the other end is connected to the first rewiring layer or the second rewiring layer.

In some alternative embodiments, the first and second redistribution layers are each a multilayer structure.

In some alternative embodiments, the number of layers of the first or second redistribution layer is greater than the number of layers of the underlying redistribution layer.

In some alternative embodiments, the bottom rerouting layer includes a layer of dielectric material and a layer of line pattern.

In some alternative embodiments, the thickness of the first chip and the second chip are different.

In some alternative embodiments, the semiconductor package apparatus further includes third and fourth chips disposed on the underlying redistribution layer with active sides facing upward, the first, second, third and fourth chips being arranged in an array.

The utility model provides a semiconductor packaging device for solving the problems of warping of large-area RDL caused by stress accumulated by mismatch of CTE, circuit cracks and solder deformation cracks which are extended by the large-area RDL. According to the utility model, the first re-wiring layer and the second re-wiring layer which are independent of each other are respectively arranged on the active surfaces of the first chip and the second chip, namely, the re-wiring layers are arranged on the active surfaces of different chips in a sectionalized manner, so that the range of the re-wiring layers is limited to the surface area of each chip, and the stress of the re-wiring layers due to mismatch of CTE is prevented from accumulating in gaps between the chips, thereby eliminating the stress accumulation of continuous and large-area re-wiring layers, and being beneficial to improving the problems of warping of the re-wiring layers, extended line cracks, solder deformation cracks and the like.

In addition, the first chip and the second chip are respectively arranged on the bottom layer rewiring layer and are respectively and electrically connected with the bottom layer rewiring layer through wire bonding, so that the height difference of the active surfaces of the chips or the thickness difference of the chips is not needed to be considered, and the chips with different thicknesses and types can be conveniently packaged into the same device.

In a further embodiment, the discrete re-wiring layers are used to respectively provide external electrical connectors of the chips, so that stress is prevented from accumulating between the chips when the external device is connected through the electrical connectors, and further, the problems of warpage of the re-wiring layers, and the problems of extended circuit cracks, solder deformation cracks and the like are improved.

Drawings

Other features, objects and advantages of the present utility model will become more apparent upon reading of the detailed description of non-limiting embodiments, made with reference to the accompanying drawings in which:

fig. 1 and 2 are a longitudinal sectional structural schematic view and a plan structural schematic view, respectively, of a semiconductor package apparatus 1a according to an embodiment of the present utility model;

fig. 3 is a schematic longitudinal sectional structure of a semiconductor package apparatus 3a according to an embodiment of the present utility model;

fig. 4 is a schematic longitudinal sectional structure of a semiconductor package apparatus 4a according to an embodiment of the present utility model;

fig. 5 is a schematic longitudinal sectional structure of a semiconductor package apparatus 5a according to an embodiment of the present utility model;

fig. 6 is a schematic longitudinal sectional structure of a semiconductor package apparatus 6a according to an embodiment of the present utility model;

fig. 7 is a schematic longitudinal sectional structure of a semiconductor package apparatus 7a according to an embodiment of the present utility model;

fig. 8 and 9 are schematic views of manufacturing steps of a chip of a semiconductor package apparatus according to an embodiment of the present utility model;

fig. 10 and 11 are schematic views of an assembly step of a semiconductor package apparatus according to an embodiment of the present utility model.

Reference numerals/symbol description:

1-a bottom rewiring layer; 101-bridging the line; 103-bonding pads; 2-a first chip; 3-a first rewiring layer; 4-a second chip; 5-a second redistribution layer; 6-wire bonding; 7-electrical connectors; 8-solder bumps; 9-molding a sealing material; 10-a third chip; 11-fourth chip; 12-underfill; 13-bonding pads; 14-copper columns; 20-wafer; 21-connection pads; 22-dielectric material; 23-seed layer; 24-a through hole; 25-photoresist; 26-line pattern; 30-carrier plate.

Detailed Description

The following description of the embodiments of the present utility model will be given with reference to the accompanying drawings and examples, and it is easy for those skilled in the art to understand the technical problems and effects of the present utility model. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant utility model and are not limiting of the utility model. In addition, for convenience of description, only parts related to the relevant utility model are shown in the drawings.

It should be readily understood that the meanings of "on", "above" and "above" in the present utility model should be interpreted in the broadest sense so that "on" means not only "directly on" but also "on" including intermediate components or layers that exist therebetween.

Further, spatially relative terms, such as "below," "under," "lower," "above," "upper," and the like, may be used herein for ease of description to describe one element or component's relationship to another element or component as illustrated in the figures. In addition to the orientations depicted in the drawings, the spatially relative terms are intended to encompass different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90 ° or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The term "layer" as used herein refers to a portion of material that includes regions having a certain thickness. The layers may extend over the entire underlying or overlying structure, or may have a degree less than the extent of the underlying or overlying structure. Furthermore, the layer may be a region of homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, the layer may be located between the top and bottom surfaces of the continuous structure or between any pair of horizontal planes therebetween. The layers may extend horizontally, vertically and/or along a tapered surface. The substrate (substrate) may be a layer, may include one or more layers therein, and/or may have one or more layers thereon, and/or thereon. One layer may comprise multiple layers. For example, the semiconductor layer may include one or more doped or undoped semiconductor layers, and may have the same or different materials.

The term "substrate" as used herein refers to a material to which subsequent layers of material are added. The substrate itself may be patterned. The material added to the top of the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials such as silicon, silicon carbide, gallium nitride, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafer, or the like. Further alternatively, the substrate may have a semiconductor device or a circuit formed therein.

It should be noted that, the structures, proportions, sizes, etc. shown in the drawings are only used for being matched with those described in the specification for understanding and reading, and are not intended to limit the applicable limitation of the present utility model, so that the present utility model has no technical significance, and any modification of structures, changes in proportions or adjustment of sizes, without affecting the efficacy and achievement of the present utility model, should still fall within the scope covered by the technical content disclosed in the present utility model. Also, the terms "upper", "first", "second", and "a" and the like are used herein for descriptive purposes only and are not intended to limit the scope of the utility model for which the utility model may be practiced, but rather for relative changes or modifications without materially altering the technical context.

It should be further noted that, in the embodiment of the present utility model, the corresponding longitudinal section may be a section corresponding to a front view direction, the corresponding transverse section may be a section corresponding to a right view direction, and the corresponding horizontal section may be a section corresponding to an upper view direction.

In addition, the embodiments of the present utility model and the features in the embodiments may be combined with each other without collision. The utility model will be described in detail below with reference to the drawings in connection with embodiments.

Referring to fig. 1-2, fig. 1-2 are a schematic longitudinal sectional structure and a schematic plan view structure, respectively, of a semiconductor package apparatus 1a according to an embodiment of the present utility model.

As shown in fig. 1 to 2, a semiconductor package apparatus 1a according to an embodiment of the present utility model includes: the device comprises a bottom rewiring layer 1 and a plurality of chips, wherein the chips at least comprise a first chip 2 and a second chip 4. The plurality of chips are disposed on the underlying redistribution layer 1 with active surfaces facing up, and the active surfaces are also respectively provided with a redistribution layer, such as a Fan Out (FO) structure or a Fan In (FI) structure, for convenience of explanation and understanding, the Fan Out (FO) structure will be used as an example if necessary. Wherein, the first chip 2 is arranged on the bottom layer rerouting layer 1 with an active surface upwards, and the active surface is provided with a first rerouting layer 3; the second chip 4 is disposed on the underlying rerouting layer 1 with its active face facing upwards, and its active face is provided with a second rerouting layer 5. The plurality of chips including the first chip 2 and the second chip 4 are electrically connected to the underlying rewiring layer 1 through the bonding wires 6, respectively.

Here, the chips, including the first Chip 2 and the second Chip 4, may be various kinds of chips (chips) having various functions. The first chip 2 and the second chip 4 may be arranged side by side on the underlying rewiring layer 1 with a gap therebetween. The thickness of the first chip 2 and the second chip 4 may be the same or different. Illustratively, the active surfaces of the first chip 2 and the second chip 4 are respectively provided with a rewiring layer as a fan-out structure, which may be called a fan-out chip.

The Wire bond 6, also referred to herein as a bond Wire or Wire bond, is a thin Wire made from a Bonding material (e.g., gold, silver, copper, aluminum, palladium, platinum, nickel, alloys thereof, etc.) that can be used to electrically connect the chip to other components during a Wire Bonding (Wire Bonding) process.

Here, the bottom rerouting layer 1 may include a bridge line 101, and the bridge line 101 may be located at a gap between the first chip 2 and the second chip 4. The first chip 2 and the second chip 4 may be electrically connected to the bridge circuit 101 through the wire bond 6, respectively, and the electrical connection is achieved through the bridge circuit 101.

Here, the first and second redistribution layers 3 and 5 may be a redistribution layer (Redistribution Layer, RDL) composed of a conductive material and a Dielectric material (Dielectric). It should be noted that the present utility model is not limited to the present utility model, and the process may use a currently known or future developed technique for forming the re-wiring layer, for example, but not limited to, photolithography, electroplating (plating), electroless plating (Electroless plating), etc. Here, the dielectric material may include organic and/or inorganic matters, wherein the organic matters may be, for example: polyamide fibers (PA), polyimide (PI), epoxy resins (Epoxy), poly-p-phenylene benzobisoxazole, PBO) fibers, FR-4 Epoxy glass laminates, PP (pre reg, prePreg, or semi-cured resins, prepregs), ABF (Ajinomoto Build-up Film), etc., while the inorganic material may be, for example, silicon (Si), glass, ceramics (ceramic), silicon oxide, silicon nitride, tantalum oxide, etc. The conductive material may include a seed layer and a metal layer. Here, the seed layer may be, for example, titanium (Ti), tungsten (W), nickel (Ni), or the like, and the metal layer may be, for example, gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu), or an alloy thereof.

In some alternative embodiments, the first and second redistribution layers 3 and 5 may be fine lines, and the line width may be less than 2 micrometers (μm) at a minimum, and the line spacing may be less than 2 micrometers (μm) at a minimum.

In some alternative embodiments, the width of the first redistribution layer 3 is smaller than the width of the first chip 2, and the first chip 2 is not completely covered, so that a part of the active surface of the first chip 2 is exposed outside the first redistribution layer 3; and the width of the second redistribution layer 5 is smaller than the width of the second chip 4, and the second chip 4 is not completely covered, so that a part of the active surface of the second chip 4 is exposed outside the second redistribution layer 5.

In some alternative embodiments, one end of the wire 6 is connected to the bridge circuit 101 of the bottom rerouting layer 1, and the other end is connected to the active surface of the first chip 2 or the active surface of the second chip 4, so as to achieve electrical connection and signal transmission between the first chip 2 and the second chip 4.

In some alternative embodiments, the first and second redistribution layers 3, 5 are discontinuous, spaced apart from each other, independent of each other, and are two distinct portions.

In some alternative embodiments, the first redistribution layer 3 and the second redistribution layer 5 are each provided with an electrical connection 7 for external electrical connection. The electrical connector 7 is configured to connect to an external device, such as a substrate or PCB (Printed Circuit Board ). Here, the electrical connector 7 includes, but is not limited to, a Solder ball (Solder ball). Alternatively, the electrical connector 7 may be provided with ACP/ACF (anisotropic conductive paste, anisotropic conductive paste/adhesive).

In some alternative embodiments, solder bumps (Solder bumps) 8 may be provided between the first redistribution layer 3 and the electrical connectors 7 thereon, and between the second redistribution layer 5 and the electrical connectors 7 thereon, respectively. By providing the solder bump 8, solder is added, which contributes to improving the soldering performance of the electrical connection member 7 for external connection and increasing the connection strength of the formed soldering structure.

In some alternative embodiments, the first and second redistribution layers 3 and 5 are each multilayer structures including the necessary circuitry and vias to enable signal transfer from the active face of the first chip 2 to the electrical connections 7, and from the active face of the second chip 4 to the electrical connections 7. Alternatively, in the multilayer structure of the first redistribution layer 3 and the second redistribution layer 5, the widths (or top view areas) of the respective layers may be the same or may be different, and the underlying wiring may be completely covered or partially exposed by the dielectric material of the upper layer.

In some alternative embodiments, the number of layers of the first rewiring layer 3 or the second rewiring layer 5 is greater than the number of layers of the underlying rewiring layer 1.

In some alternative embodiments, the bottom rerouting layer 1 is a 1P1M structure comprising a layer of dielectric material 22 and a layer of line pattern comprising the bridge line 101.

In some alternative embodiments, the line pattern of the bottom rerouting layer 1 further comprises pads 103 located under the respective chips, such as the first chip 2 or the second chip 4. The pads 103 may be configured to connect to an external device, whereby both sides of the semiconductor package apparatus 1a may be externally connected, thereby contributing to the realization of the enhanced 3D package structure. Alternatively, the pads 103 may also be configured for heat dissipation.

In some alternative embodiments, the back surfaces of the first chip 2 and the second chip 4 are on the same level.

In some alternative embodiments, the sum of the thicknesses of the first chip 2 and the first redistribution layer 3 is substantially equal to the sum of the thicknesses of the second chip 4 and the second redistribution layer 5. Therefore, the electric connectors 7 on the chips are on the same horizontal plane, and external connection is convenient.

In some alternative embodiments, the semiconductor package apparatus 1a of the embodiment of the present utility model further includes a mold seal 9, where the mold seal 9 encapsulates each of the chips including the first chip 2 and the second chip 4, and the rerouting layers such as the first rerouting layer 3 and the second rerouting layer 5 on each of the chips, and the wire bonds 6 connecting each of the chips, and the like. Alternatively, the individual chips and the wire bonds 6 may be protected by integral WL (wafer level) or PNL (panel level) molding.

In some alternative embodiments, the top surface of each solder bump 8 is exposed outside the mold seal 9, for example, flush with the surface of the mold seal 9, so that the electrical connector 7 is disposed, the electrical connector 7 protruding outside the mold seal 9.

In some alternative implementations, the semiconductor package apparatus 1a of the embodiment of the present utility model may further include more chips in addition to the first chip 2 and the second chip 4. Referring to fig. 2, the semiconductor package apparatus 1a may further include a third chip 10 and a fourth chip 11 disposed on the underlying rewiring layer 1 with active surfaces facing upward, and the first chip 2, the second chip 4, the third chip 10 and the fourth chip 11 may be arrayed in two rows and two columns. Referring to fig. 2, the semiconductor package apparatus 1a may further include 9 chips including a first chip 2, a second chip 4, a third chip 10, and a fourth chip 11, which are arrayed in three rows and three columns. Wherein the electrical connection 7 is not shown in fig. 2 for ease of illustration.

In some alternative implementations, the dimensions of the partial components in the semiconductor package apparatus 1a according to the embodiment of the present utility model range as follows:

a chip (including a first chip 2 and a second chip 4) having a width and a length of about several tens micrometers to several hundreds micrometers and a thickness of about 20 micrometers to 200 micrometers;

the thickness of the dielectric material 22 in the first and second redistribution layers 3 and 5 is about 10-30 microns, the thickness of the circuit is about 5-20 microns, and the thickness of the seed layer is about 0.1-1 micron;

the line width of the bridge circuit 101 is about 1 micron to 10 microns, and the line pitch is about 1 micron to 10 microns;

the wire bond 6 has a diameter of about 10 microns to 50 microns;

the solder bumps 8 have a diameter (height) of about 5 microns to about 30 microns and a pitch of about 10 microns to about 60 microns;

the diameter of the electric connector 7 is about 50-200 microns, and the distance is about 80-400 microns;

the thickness of the dielectric material 22 in the underlying re-wiring layer 1 is about 10 microns to 100 microns, and the thickness of the bonding pad 103 is about 5 microns to 20 microns;

the thickness of the mold seal material 9 is about 50 micrometers to 200 micrometers.

In some alternative embodiments, the semiconductor packaging apparatus 1a of the present utility model may use non-metal materials such as PI (Polyimide), epoxy, ABF (Ajinomoto Build-up Film), PP (prepreg/polypropylene), or/and acrylic resin for the following components: (a) Dielectric materials in each redistribution layer, (b) mold seal material 9, and the like.

In some alternative embodiments, the semiconductor package apparatus 1a of the present utility model may use a metal material such as Cu (copper), au (gold), ag (silver), al (aluminum), pd (palladium), pt (platinum), and Ni (nickel) and alloys thereof for the following components: (a) wires/pads/connection pads in each rewiring layer, (b) electrical connections 7, (c) wire bonds 6, etc.

In the above, the present utility model proposes a semiconductor package device 1a, a plurality of fan-out chips (FO chips) (each Chip has an FO structure on its active surface) are arranged, the chips (including a first Chip 2 and a second Chip 4) are electrically connected to a bridge circuit 101 in a bottom layer rerouting layer 1 through wires 6, and a communication path between each Chip and each Chip is formed by bonding pads (Pad) of the rerouting layer and the bridge circuit 101, wherein the wires 6 are wired on an I/O (input/output) or an I/O (Pad) of the active surface of the Chip.

The semiconductor package device 1a of the present utility model has the advantages that the range of the re-wiring layer is limited to the surface area of each chip, and the stress of the re-wiring layer due to CTE mismatch is prevented from accumulating in the gaps between chips, thereby eliminating the stress accumulation of the continuous and large-area re-wiring layer, and being helpful for improving the problems of warpage of the re-wiring layer, and the extended circuit cracks, solder deformation cracks, etc.

In addition, each chip is respectively arranged on the bottom layer rewiring layer 1 and is electrically connected with the bottom layer rewiring layer 1 through the wire bonding 6, so that the height difference of the active surfaces of each chip or the thickness difference of each chip is not needed to be considered, and chips with different thicknesses and types can be conveniently packaged into the same device. In addition, the wire bond 6 has better toughness, and can reduce stress impact. In addition, the connection by using the wire bonding 6 is also beneficial to the functional test of wafer (or panel) level manufacturing, thereby realizing lower cost, high yield and effectively reducing the loss problem caused by misuse of bad chips by using the selected KGD (Known Good Die).

In addition, the back surfaces of the individual chips lie on the same plane after all bonding is completed, which can avoid chip tilting and also means that there is a good adhesive interface between the chips after fabrication.

In a further embodiment, the discrete re-wiring layers are used to provide external electrical connectors 7 of the chips, so that when an external device is connected through the electrical connectors 7, stress is prevented from accumulating between the chips, and further, the problems of warpage of the re-wiring layers, and the problems of extended line cracks, solder deformation cracks and the like are improved. In addition, the rewiring layer is a fine line, and the electric connection pieces 7 are interconnected from the solder bumps 8, so that miniaturization of products is facilitated, and cost reduction is facilitated.

The semiconductor package apparatus 1a of the present utility model provides a good packaging solution for large area, multi-chip interconnect, semiconductor products for implementing multiple functions, such as FOCoSiP (Fan Out Chip on System in Package) structures with fan-out chips placed in a system-in-package).

Referring to fig. 3, fig. 3 is a schematic longitudinal sectional structure of a semiconductor package apparatus 3a according to an embodiment of the present utility model. The semiconductor packaging apparatus 3a shown in fig. 3 is similar to the semiconductor packaging apparatus 1a shown in fig. 1, except that:

in the semiconductor package apparatus 3a, one end of the wire 6 is connected to the bridge line 101 in the underlying rerouting layer 1, and the other end is connected to the first rerouting layer 3 on the active surface of the first chip 2 or to the second rerouting layer 5 on the active surface of the second chip 4.

In some alternative embodiments, the first redistribution layer 3 may completely cover the active face of the first chip 2, and the second redistribution layer 5 may completely cover the active face of the second chip 4.

Here, the first chip 2 is electrically connected to the second chip 4 through the first redistribution layer 3, the wire bonding 6, the bridge circuit 101, the wire bonding 6, and the second redistribution layer 5, so as to implement signal communication.

Referring to fig. 4, fig. 4 is a schematic longitudinal sectional structure of a semiconductor package apparatus 4a according to an embodiment of the present utility model. The semiconductor packaging apparatus 4a shown in fig. 4 is similar to the semiconductor packaging apparatus 1a shown in fig. 1, except that:

the semiconductor package apparatus 4a further includes an underfill material 12, where the underfill material 12 may be used to cover the sides of the respective chips, such as the first chip 2 and the second chip 4, and the gaps therebetween, and cover the underlying redistribution layer 1, especially the bridge circuit 101 therein, to provide better protection.

Here, the underfill 12 includes, but is not limited to, capillary underfill (CUF, capillary underfill).

Referring to fig. 5, fig. 5 is a schematic longitudinal sectional structure of a semiconductor package apparatus 5a according to an embodiment of the present utility model. The semiconductor packaging apparatus 5a shown in fig. 5 is similar to the semiconductor packaging apparatus 1a shown in fig. 1, except that:

in the semiconductor package apparatus 5a, the amount and volume of the mold compound 9 are greatly reduced, and the mold compound is mainly used for coating the wire bonds 6 and the bridge circuit 101, but not completely coating the chips and the rewiring layers, so as to be suitable for special application scenes.

Referring to fig. 6, fig. 6 is a schematic longitudinal sectional structure of a semiconductor package apparatus 6a according to an embodiment of the present utility model. The semiconductor packaging apparatus 6a shown in fig. 6 is similar to the semiconductor packaging apparatus 1a shown in fig. 1, except that:

in the semiconductor package apparatus 6a, the surface of the first redistribution layer 3 or the second redistribution layer 5 is provided with the pads 13, and the electrical connectors 7 may be bonded to the pads 13. Compared to the semiconductor package apparatus 1a shown in fig. 1, the solder bumps 8 are reduced.

Referring to fig. 7, fig. 7 is a schematic longitudinal sectional structure of a semiconductor package apparatus 7a according to an embodiment of the present utility model. The semiconductor packaging apparatus 7a shown in fig. 7 is similar to the semiconductor packaging apparatus 1a shown in fig. 1, except that:

in the semiconductor package apparatus 7a, the copper pillar 14 is provided on the surface of the first redistribution layer 3 or the second redistribution layer 5, and the electrical connector 7 may be bonded to the copper pillar 14. Compared to the semiconductor package apparatus 1a shown in fig. 1, the solder bumps 8 are reduced.

In some alternative embodiments, the thicknesses of the first and second redistribution layers 3 and 5 may be the same or different, and the heights of the copper pillars 14 on the first and second redistribution layers 3 and 5 may be the same or different.

In some alternative embodiments, the upper surfaces of all copper pillars 14 are substantially flush, in the same plane, to facilitate placement of electrical connectors 7.

Referring to fig. 8-9, fig. 8-9 are schematic diagrams of steps of manufacturing a chip of a semiconductor package apparatus according to an embodiment of the present utility model. As shown in fig. 8-9, the manufacturing steps of the chip according to the embodiment of the present utility model may include:

A1. a Wafer (Wafer) 20 is provided, the active side of the Wafer 20 having connection pads 21 for input/output (I/O).

A2. A layer of dielectric material 22 is laminated or coated on the active surface of the wafer 20, and the dielectric material 22 is patterned by photolithography.

A3. The dielectric material 22 is patterned by a development process to form the via 24, and a seed layer 23 is formed on the dielectric material 22 by, for example, a physical vapor deposition (Physical Vapor Deposition, PVD) process, the seed layer 23 covering the sidewalls of the via 24 to metalize it.

A4. A layer of photoresist 25 is disposed on the seed layer 23 in a lamination or coating process, and the photoresist 25 is patterned by photolithography.

A5. The photoresist 25 is patterned by a developing process, and a circuit pattern 26 is formed on the seed layer 23 by an electroplating process.

A6. The photoresist 25 is removed and the excess seed layer 23 is removed by etching, and then further layers of the line pattern 26 may be formed by repeating steps A2-A5.

A7. Through the above steps, a desired re-wiring layer is formed on the active surface of the wafer 20.

A8. A layer of dielectric material 22 is disposed over the formed redistribution layer and patterned by photolithography.

A9. The dielectric material 22 is patterned by a development process and a seed layer 23 is formed on the dielectric material 22 by, for example, a Physical Vapor Deposition (PVD) process.

A10. A layer of photoresist 25 is disposed on the seed layer 23 and patterned by photolithography.

A11. The photoresist 25 is patterned by a developing process and the solder bumps 8 are electroplated on the seed layer 23 by an electroplating process.

A12. Photoresist 25 is removed, and excess seed layer 23 is removed by etching, and the solder bump 8 may be melted and solidified by a thermal process such as a reflow process.

A13. A layer of dielectric material 22 is disposed on the back surface of the wafer 20, and the layer of dielectric material 22 may be, for example, an adhesive material. The wafer 20 is then singulated by a singulation process into a plurality of individual fan-out chips.

A14. The resulting structure of a fan-out chip, e.g. the first chip 2 or the second chip 4, is shown. Taking the first chip 2 as an example, a layer of dielectric material 22 is attached to the back surface of the first chip 2, the active surface has a first redistribution layer 3 and a connection pad 21 exposed outside the first redistribution layer 3, and the surface of the first redistribution layer 3 is provided with solder bumps 8. The second chip 4 is similar and will not be described again.

Referring to fig. 10 to 11, fig. 10 to 11 are schematic views illustrating an assembling step of a semiconductor package apparatus according to an embodiment of the present utility model. As shown in fig. 10 to 11, the assembling steps of the semiconductor package apparatus according to the embodiment of the present utility model may include:

s1, providing a carrier plate 30, and forming a seed layer 23 on the surface of the carrier plate 30.

S2, a layer of photoresist 25 is arranged on the seed layer 23 through a coating or laminating process and the photoresist 25 is patterned through a photoetching process.

S3, patterning the photoresist 25 through a developing process, and electroplating a layer of circuit pattern 26 on the seed layer 23 through an electroplating process.

S4, removing the photoresist 25, and forming the circuit pattern 26. The line pattern 26 includes bridge lines 101 at gaps between the reserved chip mounting areas.

S5, the first chip 2 with the first rerouting layer 3 on the active surface is arranged on the circuit pattern 26, and the dielectric material 22 attached to the back surface of the first chip 2 is combined with the circuit pattern 26 to form the bottom rerouting layer 1.

S6, the second chip is further arranged on the circuit pattern 26, and the active surface of the first chip 2 and the active surface of the second chip 4 are respectively and electrically connected to the bridge circuit 101 by using the wire bonding 6.

S7, completing the electrical connection of the wire bonding 6 and the first chip 2 and the electrical connection of the wire bonding 6 and the second chip 4.

S8, performing mold sealing by using the mold sealing material 9.

S9, after the molding, the respective chips such as the first chip 2 and the second chip 4, the first rewiring layer 3 and the second rewiring layer 5, the wire bond 6, and the like are encapsulated in a molding material 9. And exposing the solder bump 8 from the surface of the mold seal 9 for subsequent ball placement.

S10. removing the carrier plate 30 and removing the seed layer 23 by etching.

S11. shows the structure obtained after removal of the carrier plate 30 and removal of the seed layer 23.

S12, ball mounting is performed, and electric connectors 7 are arranged on the solder bumps 8, wherein the electric connectors 7 comprise, but are not limited to, solder balls.

S13, performing singulation treatment through a singulation process to obtain the semiconductor packaging device.

The steps for manufacturing the semiconductor package device according to the embodiment of the present utility model are described above with reference to fig. 8 to 11. In summary, the steps of manufacturing the semiconductor package apparatus according to the embodiment of the present utility model may include:

step 11, forming a re-wiring layer on the active surface of the wafer 20, forming solder bumps 8 on the surface of the re-wiring layer, and performing single-cutting to complete the prefabrication of fan-out chips (FO chips), wherein the re-wiring layer is supported by the chips (chips) at the moment, so as to obtain a first Chip 2 with the first re-wiring layer 3 on the active surface and a second Chip 4 with the second re-wiring layer 5 on the active surface.

Step 12. The bottom layer re-wiring layer 1 is formed on the surface of the Carrier 30, and the Bridge line 101 between chips is also formed, and the space for arranging chips is reserved.

And 13, placing the fan-out Chip (FO Chip) prefabricated in the step 11 in a space reserved for arranging the Chip in the step 12.

Step 14. Performing an Assembly process to electrically connect the active surface of the chip (including the first chip 2 and the second chip 4) with a Bridge line 101 formed in advance on a Carrier 30 through a bonding wire 6.

Step 15, molding the product after the step 14, and exposing the surface of the solder bump formed in step 11 from the Molding compound 9, wherein the underlying re-wiring layer 1 is supported by the carrier 30 and the Molding compound 9.

Step 16. An operation of removing the carrier (De-carrier) 30 is performed to separate the underlying rewiring layer 1 formed in step 12 from the carrier 30.

And 17, implanting balls on the solder bumps 8, and cutting into products after forming the electric connection pieces 7.

Thus, the semiconductor packaging device of the embodiment of the utility model is obtained.

While the utility model has been described and illustrated with reference to specific embodiments thereof, the description and illustration is not intended to limit the utility model. It will be apparent to those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof within the embodiments thereof without departing from the true spirit and scope of the utility model as defined by the appended claims. The illustrations may not be drawn to scale. There may be a distinction between technical reproduction and actual implementation in the present utility model due to variables in the manufacturing process, etc. Other embodiments of the utility model not specifically illustrated may exist. The specification and drawings are to be regarded in an illustrative rather than a restrictive sense. Modifications may be made to adapt a particular situation, material, composition of matter, method or process to the objective, spirit and scope of the present utility model. All such modifications are intended to fall within the scope of the claims appended hereto. Although the methods disclosed herein have been described with reference to particular operations being performed in a particular order, it should be understood that these operations may be combined, sub-divided, or reordered to form an equivalent method without departing from the teachings of the present disclosure. Thus, the order and grouping of the operations is not a limitation of the present utility model unless specifically indicated herein.

Claims

1. A semiconductor package apparatus, comprising:

a bottom layer rewiring layer;

the first chip is provided with a first rewiring layer on the active surface and is arranged on the bottom rewiring layer with the active surface upwards;

the active surface of the second chip is provided with a second rewiring layer, and the second chip is arranged on the bottom rewiring layer with the active surface upwards;

the first chip and the second chip are respectively and electrically connected with the bottom layer rewiring layer through wire bonding.

2. The semiconductor package apparatus according to claim 1, wherein an electrical connection for external electrical connection is provided on each of the first and second redistribution layers, and wherein the first and second redistribution layers are discontinuous.

3. The semiconductor package apparatus according to claim 2, wherein the electrical connector has a solder bump between the first redistribution layer or the second redistribution layer.

4. The semiconductor package apparatus according to claim 2, wherein one end of the wire bond is connected to the underlying rewiring layer, and the other end is connected to the active surface of the first chip or the active surface of the second chip.

5. The semiconductor package apparatus according to claim 2, wherein one end of the wire bond is connected to the underlying rerouting layer and the other end is connected to the first rerouting layer or the second rerouting layer.

6. The semiconductor package apparatus according to claim 1, wherein the first and second redistribution layers are each a multilayer structure.

7. The semiconductor package apparatus according to claim 6, wherein the number of layers of the first redistribution layer or the second redistribution layer is greater than the number of layers of the underlying redistribution layer.

8. The semiconductor package apparatus of claim 7, wherein the bottom rerouting layer comprises a layer of dielectric material and a layer of wiring pattern.

9. The semiconductor package apparatus according to claim 1, wherein the first chip and the second chip are different in thickness.

10. The semiconductor package apparatus according to claim 1, further comprising a third chip and a fourth chip disposed on the underlying rerouting layer with active sides facing upward, the first chip, the second chip, the third chip, and the fourth chip being arranged in an array.